diff --git a/hw/bsp/stm32h743eval/stm32h743eval.c b/hw/bsp/stm32h743eval/stm32h743eval.c
index d149c1230..836f1ecab 100644
--- a/hw/bsp/stm32h743eval/stm32h743eval.c
+++ b/hw/bsp/stm32h743eval/stm32h743eval.c
@@ -265,6 +265,7 @@ void board_init(void)
 #endif
 
 #if BOARD_DEVICE_RHPORT_NUM == 1
+
   // Despite being call USB2_OTG
   // OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
   __GPIOA_CLK_ENABLE();
@@ -316,6 +317,8 @@ void board_init(void)
   GPIO_InitStruct.Pull = GPIO_NOPULL;
   GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
   HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
+
+  // Enable ULPI clock
   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE();
 
   /* Enable USB HS Clocks */
@@ -325,12 +328,14 @@ void board_init(void)
   USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
 
   // Force device mode
-  // USB_OTG_HS->GUSBCFG &= ~USB_OTG_GUSBCFG_FHMOD;
-  // USB_OTG_HS->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
+  USB_OTG_HS->GUSBCFG &= ~USB_OTG_GUSBCFG_FHMOD;
+  USB_OTG_HS->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
 
   // B-peripheral session valid override enabl
-//  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-//  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
+  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
+  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
+
+  HAL_PWREx_EnableUSBVoltageDetector();
 #endif // rhport = 1
 
 }
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index f144cda73..d77893b6b 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -241,9 +241,9 @@ void tu_print_var(uint8_t const* buf, uint32_t bufsize)
   #define TU_LOG2             TU_LOG1
   #define TU_LOG2_MEM         TU_LOG1_MEM
   #define TU_LOG2_VAR         TU_LOG1_VAR
-  #define TU_LOG2_LOCATION()  TU_LOG1_LOCATION()
   #define TU_LOG2_INT         TU_LOG1_INT
   #define TU_LOG2_HEX         TU_LOG1_HEX
+  #define TU_LOG2_LOCATION()  TU_LOG1_LOCATION()
 #endif
 
 
@@ -277,6 +277,7 @@ static inline char const* lookup_find(lookup_table_t const* p_table, uint32_t ke
   #define TU_LOG1_VAR(...)
   #define TU_LOG1_INT(...)
   #define TU_LOG1_HEX(...)
+  #define TU_LOG1_LOCATION()
 #endif
 
 #ifndef TU_LOG2
@@ -285,6 +286,7 @@ static inline char const* lookup_find(lookup_table_t const* p_table, uint32_t ke
   #define TU_LOG2_VAR(...)
   #define TU_LOG2_INT(...)
   #define TU_LOG2_HEX(...)
+  #define TU_LOG2_LOCATION()
 #endif
 
 #ifdef __cplusplus
diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c
index 8ca67dbb4..fe6fe5cea 100644
--- a/src/portable/st/synopsys/dcd_synopsys.c
+++ b/src/portable/st/synopsys/dcd_synopsys.c
@@ -197,6 +197,8 @@ static void end_of_reset(uint8_t rhport)
   // However, keep for debugging and in case Low Speed is ever supported.
   uint32_t enum_spd = (dev->DSTS & USB_OTG_DSTS_ENUMSPD_Msk) >> USB_OTG_DSTS_ENUMSPD_Pos;
 
+  // TODO set turnaround in GUSBCFG accordingly to the speed
+
   // Maximum packet size for EP 0 is set for both directions by writing
   // DIEPCTL.
   if(enum_spd == 0x03) {
@@ -239,7 +241,8 @@ void dcd_init (uint8_t rhport)
     // Turn around time for Highspeed is 0x09
     usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
     usb_otg->GUSBCFG |= (0x09 << USB_OTG_GUSBCFG_TRDT_Pos);
-  }else
+  }
+  else
 #endif
   {
     // Turn around programmed for 32+ MHz is 0x06
@@ -256,8 +259,6 @@ void dcd_init (uint8_t rhport)
   // Force device mode
   usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
 
-  TU_LOG2_LOCATION();
-
   // Restart PHY clock
   *((volatile uint32_t *)(_dcd_rhport[rhport].regs + USB_OTG_PCGCCTL_BASE)) = 0;
 
@@ -282,8 +283,9 @@ void dcd_init (uint8_t rhport)
     dev->DCFG &= ~(3 << USB_OTG_DCFG_DSPD_Pos);
 
     // Transceiver delay, necessary for some ULPI PHYs
-    dev->DCFG |= (1 << 14);
+    //dev->DCFG |= (1 << 14);
   }
+  else
 #endif
   {
     // full speed with internal phy