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Use correct backend.

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This commit is contained in:
Tinic Uro
2024-05-30 13:26:14 -07:00
parent 2e946ac77a
commit 60d7fcb1ee
4 changed files with 49 additions and 20 deletions
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2
src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
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@@ -232,7 +232,7 @@ void dcd_init(uint8_t rhport)
}
USB->CNTR = 0; // Enable USB
#if !defined(STM32G0) && !defined(STM32H5) // BTABLE register does not exist any more on STM32G0, it is fixed to USB SRAM base address
#if !defined(STM32G0) && !defined(STM32H5) && !defined(STM32U5) // BTABLE register does not exist any more on STM32G0, it is fixed to USB SRAM base address
USB->BTABLE = DCD_STM32_BTABLE_BASE;
#endif
USB->ISTR = 0; // Clear pending interrupts