usb通信成功
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This commit is contained in:
@@ -340,6 +340,7 @@ uint16_t cdcd_open(uint8_t rhport, const tusb_desc_interface_t* itf_desc, uint16
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// Only support ACM subclass
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TU_VERIFY( TUSB_CLASS_CDC == itf_desc->bInterfaceClass &&
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CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass, 0);
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TU_LOG(2,"CDC Interface %u\r\n", itf_desc->bInterfaceNumber);
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// Find available interface
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cdcd_interface_t* p_cdc;
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@@ -35,6 +35,14 @@
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extern "C" {
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#endif
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// Enable device interrupt
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extern void dcd_int_enable (uint8_t rhport);
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// Disable device interrupt
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extern void dcd_int_disable(uint8_t rhport);
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//--------------------------------------------------------------------+
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// TASK API
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//--------------------------------------------------------------------+
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@@ -51,24 +59,21 @@ typedef struct rt_mutex osal_spinlock_t;
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osal_spinlock_t _name
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TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) {
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// rt_spin_lock_init(ctx);
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rt_mutex_init(ctx, "tusb", RT_IPC_FLAG_PRIO);
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}
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TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) {
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if (!TUP_MCU_MULTIPLE_CORE && in_isr) {
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return; // single core MCU does not need to lock in ISR
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}
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// rt_spin_lock(ctx);
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rt_mutex_take(ctx, RT_WAITING_FOREVER);
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dcd_int_disable(1);
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}
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TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) {
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if (!TUP_MCU_MULTIPLE_CORE && in_isr) {
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return; // single core MCU does not need to lock in ISR
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}
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// rt_spin_unlock(ctx);
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rt_mutex_release(ctx);
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dcd_int_enable(1);
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}
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//--------------------------------------------------------------------+
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@@ -163,7 +168,12 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, v
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TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr) {
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(void) in_isr;
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return rt_mq_send(qhdl, (void *)data, qhdl->msg_size) == RT_EOK;
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int ret;
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ret = rt_mq_send(qhdl, (void *) data, qhdl->msg_size);
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if (ret != RT_EOK) {
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rt_kprintf("osal_queue_send failed ret=%d\n", ret);
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}
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return ret == RT_EOK;
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}
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TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) {
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@@ -85,9 +85,9 @@ static void phy_fs_init(dwc2_regs_t* dwc2) {
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gusbcfg &= ~GUSBCFG_TRDT_Msk;
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gusbcfg |= 5u << GUSBCFG_TRDT_Pos;
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// force to device mode
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gusbcfg |= GUSBCFG_FDMOD;
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// gusbcfg |= GUSBCFG_FDMOD;
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dwc2->gusbcfg = gusbcfg;
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osal_task_delay(50);
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// osal_task_delay(50);
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// MCU specific PHY update post reset
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dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
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@@ -273,7 +273,7 @@ static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
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turnaround = 0xCu;
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}
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else if (SystemCoreClock >= 16000000u) {
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turnaround = 0xfu;
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turnaround = 0xdu;
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}
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else if (SystemCoreClock >= 15000000u) {
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turnaround = 0xEu;
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