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change tuh_max3421_spi_xfer_api() signature

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tested working with sam d21 and d51, not tested with nrf52, seem not
working with esp32
This commit is contained in:
hathach
2023-10-04 18:00:32 +07:00
parent f36e0b7b92
commit 67e34267a6
5 changed files with 88 additions and 60 deletions
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27
hw/bsp/samd21/family.c
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@@ -72,6 +72,7 @@ static void uart_init(void);
#define MAX3421_SERCOM TU_XSTRCAT(SERCOM, MAX3421_SERCOM_ID)
static void max3421_init(void);
#endif
void board_init(void) {
@@ -237,13 +238,13 @@ int board_uart_write(void const * buf, int len)
static void uart_init(void) {
}
int board_uart_read(uint8_t *buf, int len) {
int board_uart_read(uint8_t* buf, int len) {
(void) buf;
(void) len;
return 0;
}
int board_uart_write(void const *buf, int len) {
int board_uart_write(void const* buf, int len) {
(void) buf;
(void) len;
return 0;
@@ -261,6 +262,7 @@ void SysTick_Handler(void) {
uint32_t board_millis(void) {
return system_ticks;
}
#endif
//--------------------------------------------------------------------+
@@ -278,8 +280,8 @@ static void max3421_init(void) {
// Configure GCLK for SERCOM
// GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_SERCOM4_CORE | GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_CLKEN;
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(GCLK_CLKCTRL_ID_SERCOM0_CORE_Val+MAX3421_SERCOM_ID) |
GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_CLKEN;
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(GCLK_CLKCTRL_ID_SERCOM0_CORE_Val + MAX3421_SERCOM_ID) |
GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_CLKEN;
while (GCLK->STATUS.bit.SYNCBUSY);
Sercom* sercom = MAX3421_SERCOM;
@@ -293,7 +295,7 @@ static void max3421_init(void) {
// Set up SPI in master mode, MSB first, SPI mode 0
sercom->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_DOPO(MAX3421_TX_PAD) | SERCOM_SPI_CTRLA_DIPO(MAX3421_RX_PAD) |
SERCOM_SPI_CTRLA_MODE(3);
SERCOM_SPI_CTRLA_MODE(3);
sercom->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN;
while (sercom->SPI.SYNCBUSY.bit.CTRLB == 1);
@@ -366,6 +368,7 @@ void EIC_Handler(void) {
tuh_int_handler(1, true);
}
// API to enable/disable MAX3421 INTR pin interrupt
void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
(void) rhport;
@@ -376,24 +379,26 @@ void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
}
}
// API to control MAX3421 SPI CS
void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
(void) rhport;
gpio_set_pin_level(MAX3421_CS_PIN, active ? 0 : 1);
}
bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {
// API to transfer data with MAX3421 SPI
// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only
bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) {
(void) rhport;
Sercom* sercom = MAX3421_SERCOM;
size_t count = 0;
while (count < tx_len || count < rx_len) {
for (size_t count = 0; count < xfer_bytes; count++) {
// Wait for the transmit buffer to be empty
while (!sercom->SPI.INTFLAG.bit.DRE);
// Write data to be transmitted
uint8_t data = 0x00;
if (count < tx_len) {
if (tx_buf) {
data = tx_buf[count];
}
@@ -404,11 +409,9 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l
// Read received data
data = (uint8_t) sercom->SPI.DATA.reg;
if (count < rx_len) {
if (rx_buf) {
rx_buf[count] = data;
}
count++;
}
// wait for bus idle and clear flags