diff --git a/.gitignore b/.gitignore index 8f5bb6efd..c665d6c73 100644 --- a/.gitignore +++ b/.gitignore @@ -21,6 +21,8 @@ _build /examples/*/*/ses /examples/*/*/ozone /examples/obsolete +hw/bsp/**/cubemx/*/ +.mxproject # coverity intermediate files cov-int # cppcheck build directories diff --git a/.idea/cmake.xml b/.idea/cmake.xml index c9024715c..0f7649efc 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -2,9 +2,9 @@ - - - + + + @@ -29,7 +29,7 @@ - + @@ -38,6 +38,7 @@ + \ No newline at end of file diff --git a/.idea/runConfigurations/kl25.xml b/.idea/runConfigurations/kl25.xml new file mode 100644 index 000000000..add9a0d6b --- /dev/null +++ b/.idea/runConfigurations/kl25.xml @@ -0,0 +1,10 @@ + + + + + + + + + \ No newline at end of file diff --git a/.idea/runConfigurations/lpc1857.xml b/.idea/runConfigurations/lpc1857.xml new file mode 100644 index 000000000..f377d86f2 --- /dev/null +++ b/.idea/runConfigurations/lpc1857.xml @@ -0,0 +1,10 @@ + + + + + + + + + \ No newline at end of file diff --git a/.idea/runConfigurations/mcx947.xml b/.idea/runConfigurations/mcx947.xml new file mode 100644 index 000000000..038c87421 --- /dev/null +++ b/.idea/runConfigurations/mcx947.xml @@ -0,0 +1,10 @@ + + + + + + + + + \ No newline at end of file diff --git a/.idea/runConfigurations/mcx947_jlink.xml b/.idea/runConfigurations/mcx947_jlink.xml deleted file mode 100644 index 27661bec5..000000000 --- a/.idea/runConfigurations/mcx947_jlink.xml +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - \ No newline at end of file diff --git a/.idea/runConfigurations/nrf52840.xml b/.idea/runConfigurations/nrf52840.xml new file mode 100644 index 000000000..66473cc0e --- /dev/null +++ b/.idea/runConfigurations/nrf52840.xml @@ -0,0 +1,10 @@ + + + + + + + + + \ No newline at end of file diff --git a/.idea/runConfigurations/nrf5340.xml b/.idea/runConfigurations/nrf5340.xml new file mode 100644 index 000000000..403095d70 --- /dev/null +++ b/.idea/runConfigurations/nrf5340.xml @@ -0,0 +1,10 @@ + + + + + + + + + \ No newline at end of file diff --git a/.idea/runConfigurations/rt1010.xml b/.idea/runConfigurations/rt1010.xml new file mode 100644 index 000000000..6fabd8561 --- /dev/null +++ b/.idea/runConfigurations/rt1010.xml @@ -0,0 +1,10 @@ + + + + + + + + + \ No newline at end of file diff --git a/.idea/runConfigurations/rt1010_jlink.xml b/.idea/runConfigurations/rt1010_jlink.xml deleted file mode 100644 index 68ebb8885..000000000 --- a/.idea/runConfigurations/rt1010_jlink.xml +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - \ No newline at end of file diff --git a/.idea/runConfigurations/rt1060.xml b/.idea/runConfigurations/rt1060.xml new file mode 100644 index 000000000..218c2dfbc --- /dev/null +++ b/.idea/runConfigurations/rt1060.xml @@ -0,0 +1,10 @@ + + + + + + + + + \ No newline at end of file diff --git a/.idea/runConfigurations/rt1060_jlink.xml b/.idea/runConfigurations/rt1060_jlink.xml deleted file mode 100644 index 014a4d1b1..000000000 --- a/.idea/runConfigurations/rt1060_jlink.xml +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - \ No newline at end of file diff --git a/.idea/runConfigurations/stlink.xml b/.idea/runConfigurations/stlink.xml new file mode 100644 index 000000000..c27392ca5 --- /dev/null +++ b/.idea/runConfigurations/stlink.xml @@ -0,0 +1,10 @@ + + + + + + + + + \ No newline at end of file diff --git a/.idea/runConfigurations/stm32g474.xml b/.idea/runConfigurations/stm32g474.xml new file mode 100644 index 000000000..bbab2a5c5 --- /dev/null +++ b/.idea/runConfigurations/stm32g474.xml @@ -0,0 +1,10 @@ + + + + + + + + + \ No newline at end of file diff --git a/.idea/runConfigurations/stm32g474_jlink.xml b/.idea/runConfigurations/stm32g474_jlink.xml deleted file mode 100644 index c33829833..000000000 --- a/.idea/runConfigurations/stm32g474_jlink.xml +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - \ No newline at end of file diff --git a/.idea/runConfigurations/stm32h743.xml b/.idea/runConfigurations/stm32h743.xml new file mode 100644 index 000000000..7581ddf9b --- /dev/null +++ b/.idea/runConfigurations/stm32h743.xml @@ -0,0 +1,10 @@ + + + + + + + + + \ No newline at end of file diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index ec36df5c8..73e674c18 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -166,6 +166,11 @@ function(family_configure_common TARGET) endif () endif () + # ETM Trace + if (TRACE_ETM STREQUAL "1") + target_compile_definitions(${TARGET} PUBLIC TRACE_ETM) + endif () + endfunction() diff --git a/hw/bsp/lpc18/boards/mcb1800/board.h b/hw/bsp/lpc18/boards/mcb1800/board.h index 6111da975..5bfaa37cd 100644 --- a/hw/bsp/lpc18/boards/mcb1800/board.h +++ b/hw/bsp/lpc18/boards/mcb1800/board.h @@ -41,10 +41,17 @@ #define UART_DEV LPC_USART3 -static inline void board_lpc18_pinmux(void) -{ - const PINMUX_GRP_T pinmuxing[] = - { +static inline void board_lpc18_pinmux(void) { + const PINMUX_GRP_T pinmuxing[] = { + // ETM Trace + #ifdef TRACE_ETM + { 0xF, 4, SCU_MODE_FUNC2 | SCU_MODE_HIGHSPEEDSLEW_EN }, + { 0xF, 5, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN }, + { 0xF, 6, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN }, + { 0xF, 7, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN }, + { 0xF, 8, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN }, + #endif + // LEDs { 0xD, 10, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4) }, { 0xD, 11, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4 | SCU_MODE_PULLDOWN) }, @@ -72,8 +79,7 @@ static inline void board_lpc18_pinmux(void) Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T)); /* Pin clock mux values, re-used structure, value in first index is meaningless */ - const PINMUX_GRP_T pinclockmuxing[] = - { + const PINMUX_GRP_T pinclockmuxing[] = { { 0, 0, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)}, { 0, 1, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)}, { 0, 2, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)}, @@ -81,8 +87,7 @@ static inline void board_lpc18_pinmux(void) }; /* Clock pins only, group field not used */ - for (uint32_t i = 0; i < (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++) - { + for (uint32_t i = 0; i < (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++) { Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc); } } diff --git a/hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug b/hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug new file mode 100644 index 000000000..6e298c62d --- /dev/null +++ b/hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug @@ -0,0 +1,36 @@ + +/********************************************************************* +* +* OnProjectLoad +* +* Function description +* Project load routine. Required. +* +********************************************************************** +*/ +void OnProjectLoad (void) { + Project.AddSvdFile ("Cortex-M3.svd"); + Project.AddSvdFile ("./LPC18xx.svd"); + + Project.SetDevice ("LPC1857"); + Project.SetHostIF ("USB", ""); + Project.SetTargetIF ("SWD"); + Project.SetTIFSpeed ("50 MHz"); + + Project.SetTraceSource ("Trace Pins"); + Project.SetTracePortWidth (4); + + File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-mcb1800/cdc_msc.elf"); +} +/********************************************************************* +* +* BeforeTargetConnect +* +********************************************************************** +*/ +void BeforeTargetConnect (void) { + // + // Trace pin init is done by J-Link script file as J-Link script files are IDE independent + // + // Project.SetJLinkScript("./NXP_LPC1857JET256_TraceExample.pex"); +} diff --git a/hw/bsp/lpc18/family.c b/hw/bsp/lpc18/family.c index 57f9d55da..2fd69c84b 100644 --- a/hw/bsp/lpc18/family.c +++ b/hw/bsp/lpc18/family.c @@ -69,7 +69,6 @@ void USB1_IRQHandler(void) // MACRO TYPEDEF CONSTANT ENUM DECLARATION //--------------------------------------------------------------------+ - /* System configuration variables used by chip driver */ const uint32_t OscRateIn = 12000000; const uint32_t ExtRateIn = 0; @@ -84,7 +83,15 @@ void SystemInit(void) #endif board_lpc18_pinmux(); - Chip_SetupXtalClocking(); + + #ifdef TRACE_ETM + // Trace clock is limited to 60MHz, limit CPU clock to 120MHz + Chip_SetupCoreClock(CLKIN_CRYSTAL, 120000000UL, true); + #else + // CPU clock max to 180 Mhz + Chip_SetupCoreClock(CLKIN_CRYSTAL, MAX_CLOCK_FREQ, true); + #endif + } void board_init(void) diff --git a/hw/bsp/nrf/boards/pca10056/board.h b/hw/bsp/nrf/boards/pca10056/board.h index 50d3067b3..f4368f830 100644 --- a/hw/bsp/nrf/boards/pca10056/board.h +++ b/hw/bsp/nrf/boards/pca10056/board.h @@ -36,7 +36,7 @@ #define LED_STATE_ON 0 // Button -#define BUTTON_PIN 11 +#define BUTTON_PIN 25 // button 4 #define BUTTON_STATE_ACTIVE 0 // UART diff --git a/hw/bsp/nrf/boards/pca10056/ozone/nrf52840.jdebug b/hw/bsp/nrf/boards/pca10056/ozone/nrf52840.jdebug new file mode 100644 index 000000000..fa7ab9e23 --- /dev/null +++ b/hw/bsp/nrf/boards/pca10056/ozone/nrf52840.jdebug @@ -0,0 +1,238 @@ + +/********************************************************************* +* +* OnProjectLoad +* +* Function description +* Project load routine. Required. +* +********************************************************************** +*/ +void OnProjectLoad (void) { + // Dialog-generated settings + Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M4F.svd"); + Project.AddSvdFile ("$(InstallDir)/Config/Peripherals/ARMv7M.svd"); + + Project.SetDevice ("nRF52840_xxAA"); + Project.SetHostIF ("USB", ""); + Project.SetTargetIF ("SWD"); + Project.SetTIFSpeed ("8 MHz"); + Project.SetTraceSource ("Trace Pins"); + Project.SetTracePortWidth (4); + + // User settings + File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-pca10056/cdc_msc.elf"); +} + +/********************************************************************* +* +* TargetReset +* +* Function description +* Replaces the default target device reset routine. Optional. +* +* Notes +* This example demonstrates the usage when +* debugging a RAM program on a Cortex-M target device +* +********************************************************************** +*/ +//void TargetReset (void) { +// +// unsigned int SP; +// unsigned int PC; +// unsigned int VectorTableAddr; +// +// Exec.Reset(); +// +// VectorTableAddr = Elf.GetBaseAddr(); +// +// if (VectorTableAddr != 0xFFFFFFFF) { +// +// Util.Log("Resetting Program."); +// +// SP = Target.ReadU32(VectorTableAddr); +// Target.SetReg("SP", SP); +// +// PC = Target.ReadU32(VectorTableAddr + 4); +// Target.SetReg("PC", PC); +// } +//} + +/********************************************************************* +* +* BeforeTargetReset +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void BeforeTargetReset (void) { +//} + +/********************************************************************* +* +* AfterTargetReset +* +* Function description +* Event handler routine. +* - Sets the PC register to program reset value. +* - Sets the SP register to program reset value on Cortex-M. +* +********************************************************************** +*/ +void AfterTargetReset (void) { + unsigned int SP; + unsigned int PC; + unsigned int VectorTableAddr; + + VectorTableAddr = Elf.GetBaseAddr(); + + if (VectorTableAddr == 0xFFFFFFFF) { + Util.Log("Project file error: failed to get program base"); + } else { + SP = Target.ReadU32(VectorTableAddr); + Target.SetReg("SP", SP); + + PC = Target.ReadU32(VectorTableAddr + 4); + Target.SetReg("PC", PC); + } +} + +/********************************************************************* +* +* DebugStart +* +* Function description +* Replaces the default debug session startup routine. Optional. +* +********************************************************************** +*/ +//void DebugStart (void) { +//} + +/********************************************************************* +* +* TargetConnect +* +* Function description +* Replaces the default target IF connection routine. Optional. +* +********************************************************************** +*/ +//void TargetConnect (void) { +//} + +/********************************************************************* +* +* BeforeTargetConnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +void BeforeTargetConnect (void) { +} + +/********************************************************************* +* +* AfterTargetConnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void AfterTargetConnect (void) { +//} + +/********************************************************************* +* +* TargetDownload +* +* Function description +* Replaces the default program download routine. Optional. +* +********************************************************************** +*/ +//void TargetDownload (void) { +//} + +/********************************************************************* +* +* BeforeTargetDownload +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void BeforeTargetDownload (void) { +//} + +/********************************************************************* +* +* AfterTargetDownload +* +* Function description +* Event handler routine. +* - Sets the PC register to program reset value. +* - Sets the SP register to program reset value on Cortex-M. +* +********************************************************************** +*/ +void AfterTargetDownload (void) { + unsigned int SP; + unsigned int PC; + unsigned int VectorTableAddr; + + VectorTableAddr = Elf.GetBaseAddr(); + + if (VectorTableAddr == 0xFFFFFFFF) { + Util.Log("Project file error: failed to get program base"); + } else { + SP = Target.ReadU32(VectorTableAddr); + Target.SetReg("SP", SP); + + PC = Target.ReadU32(VectorTableAddr + 4); + Target.SetReg("PC", PC); + } +} + +/********************************************************************* +* +* BeforeTargetDisconnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void BeforeTargetDisconnect (void) { +//} + +/********************************************************************* +* +* AfterTargetDisconnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void AfterTargetDisconnect (void) { +//} + +/********************************************************************* +* +* AfterTargetHalt +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void AfterTargetHalt (void) { +//} diff --git a/hw/bsp/nrf/boards/pca10095/ozone/nrf5340.jdebug b/hw/bsp/nrf/boards/pca10095/ozone/nrf5340.jdebug new file mode 100644 index 000000000..4ad0376a4 --- /dev/null +++ b/hw/bsp/nrf/boards/pca10095/ozone/nrf5340.jdebug @@ -0,0 +1,335 @@ +/********************************************************************* +* (c) SEGGER Microcontroller GmbH * +* The Embedded Experts * +* www.segger.com * +********************************************************************** + +File : +Created : 30 Jun 2021 13:37 +Ozone Version : V3.24a +*/ + +/********************************************************************* +* +* OnProjectLoad +* +* Function description +* Project load routine. Required. +* +********************************************************************** +*/ +void OnProjectLoad (void) { + // Dialog-generated settings + Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M33F.svd"); + Project.AddSvdFile ("./nrf5340_application.svd"); + Project.SetDevice ("nRF5340_xxAA_APP"); + Project.SetHostIF ("USB", ""); + Project.SetTargetIF ("SWD"); + Project.SetTIFSpeed ("16 MHz"); + + Project.SetTraceSource ("Trace Pins"); + Project.SetTracePortWidth (4); + + // User settings + File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-pca10095/cdc_msc.elf"); +} + +/********************************************************************* +* +* OnStartupComplete +* +* Function description +* Called when program execution has reached/passed +* the startup completion point. Optional. +* +********************************************************************** +*/ +//void OnStartupComplete (void) { +//} + +/********************************************************************* +* +* TargetReset +* +* Function description +* Replaces the default target device reset routine. Optional. +* +* Notes +* This example demonstrates the usage when +* debugging an application in RAM on a Cortex-M target device. +* +********************************************************************** +*/ +//void TargetReset (void) { +// +// unsigned int SP; +// unsigned int PC; +// unsigned int VectorTableAddr; +// +// VectorTableAddr = Elf.GetBaseAddr(); +// // +// // Set up initial stack pointer +// // +// if (VectorTableAddr != 0xFFFFFFFF) { +// SP = Target.ReadU32(VectorTableAddr); +// Target.SetReg("SP", SP); +// } +// // +// // Set up entry point PC +// // +// PC = Elf.GetEntryPointPC(); +// +// if (PC != 0xFFFFFFFF) { +// Target.SetReg("PC", PC); +// } else if (VectorTableAddr != 0xFFFFFFFF) { +// PC = Target.ReadU32(VectorTableAddr + 4); +// Target.SetReg("PC", PC); +// } else { +// Util.Error("Project file error: failed to set entry point PC", 1); +// } +//} + +/********************************************************************* +* +* BeforeTargetReset +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void BeforeTargetReset (void) { +//} + +/********************************************************************* +* +* AfterTargetReset +* +* Function description +* Event handler routine. Optional. +* The default implementation initializes SP and PC to reset values. +** +********************************************************************** +*/ +void AfterTargetReset (void) { + _SetupTarget(); +} + +/********************************************************************* +* +* DebugStart +* +* Function description +* Replaces the default debug session startup routine. Optional. +* +********************************************************************** +*/ +//void DebugStart (void) { +//} + +/********************************************************************* +* +* TargetConnect +* +* Function description +* Replaces the default target IF connection routine. Optional. +* +********************************************************************** +*/ +//void TargetConnect (void) { +//} + +/********************************************************************* +* +* BeforeTargetConnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +void BeforeTargetConnect (void) { +} + +/********************************************************************* +* +* AfterTargetConnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void AfterTargetConnect (void) { +//} + +/********************************************************************* +* +* TargetDownload +* +* Function description +* Replaces the default program download routine. Optional. +* +********************************************************************** +*/ +//void TargetDownload (void) { +//} + +/********************************************************************* +* +* BeforeTargetDownload +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void BeforeTargetDownload (void) { +//} + +/********************************************************************* +* +* AfterTargetDownload +* +* Function description +* Event handler routine. Optional. +* The default implementation initializes SP and PC to reset values. +* +********************************************************************** +*/ +void AfterTargetDownload (void) { + _SetupTarget(); +} + +/********************************************************************* +* +* BeforeTargetDisconnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void BeforeTargetDisconnect (void) { +//} + +/********************************************************************* +* +* AfterTargetDisconnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void AfterTargetDisconnect (void) { +//} + +/********************************************************************* +* +* AfterTargetHalt +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void AfterTargetHalt (void) { +//} + +/********************************************************************* +* +* BeforeTargetResume +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void BeforeTargetResume (void) { +//} + +/********************************************************************* +* +* OnSnapshotLoad +* +* Function description +* Called upon loading a snapshot. Optional. +* +* Additional information +* This function is used to restore the target state in cases +* where values cannot simply be written to the target. +* Typical use: GPIO clock needs to be enabled, before +* GPIO is configured. +* +********************************************************************** +*/ +//void OnSnapshotLoad (void) { +//} + +/********************************************************************* +* +* OnSnapshotSave +* +* Function description +* Called upon saving a snapshot. Optional. +* +* Additional information +* This function is usually used to save values of the target +* state which can either not be trivially read, +* or need to be restored in a specific way or order. +* Typically use: Memory Mapped Registers, +* such as PLL and GPIO configuration. +* +********************************************************************** +*/ +//void OnSnapshotSave (void) { +//} + +/********************************************************************* +* +* OnError +* +* Function description +* Called when an error occurred. Optional. +* +********************************************************************** +*/ +//void OnError (void) { +//} + +/********************************************************************* +* +* _SetupTarget +* +* Function description +* Setup the target. +* Called by AfterTargetReset() and AfterTargetDownload(). +* +* Auto-generated function. May be overridden by Ozone. +* +********************************************************************** +*/ +void _SetupTarget(void) { + unsigned int SP; + unsigned int PC; + unsigned int VectorTableAddr; + + VectorTableAddr = Elf.GetBaseAddr(); + // + // Set up initial stack pointer + // + SP = Target.ReadU32(VectorTableAddr); + if (SP != 0xFFFFFFFF) { + Target.SetReg("SP", SP); + } + // + // Set up entry point PC + // + PC = Elf.GetEntryPointPC(); + if (PC != 0xFFFFFFFF) { + Target.SetReg("PC", PC); + } else { + Util.Error("Project script error: failed to set up entry point PC", 1); + } +} diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake index 88670b50b..825380d0b 100644 --- a/hw/bsp/nrf/family.cmake +++ b/hw/bsp/nrf/family.cmake @@ -46,6 +46,12 @@ function(add_board_target BOARD_TARGET) target_compile_definitions(${BOARD_TARGET} PUBLIC CONFIG_GPIO_AS_PINRESET ) + + if (TRACE_ETM STREQUAL "1") + # ENABLE_TRACE will cause system_nrf5x.c to set up ETM trace + target_compile_definitions(${BOARD_TARGET} PUBLIC ENABLE_TRACE) + endif () + target_include_directories(${BOARD_TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} ${NRFX_DIR} diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/board.ioc b/hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/b_g474e_dpow1.ioc similarity index 98% rename from hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/board.ioc rename to hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/b_g474e_dpow1.ioc index 6ce126f84..c15011896 100644 --- a/hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/board.ioc +++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/b_g474e_dpow1.ioc @@ -111,13 +111,13 @@ ProjectManager.MainLocation=Src ProjectManager.NoMain=false ProjectManager.PreviousToolchain= ProjectManager.ProjectBuild=false -ProjectManager.ProjectFileName=board.ioc -ProjectManager.ProjectName=board +ProjectManager.ProjectFileName=b_g474e_dpow1.ioc +ProjectManager.ProjectName=b_g474e_dpow1 ProjectManager.ProjectStructure= ProjectManager.RegisterCallBack= ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=Makefile -ProjectManager.ToolChainLocation= +ProjectManager.ToolChainLocation=Src ProjectManager.UnderRoot=false ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_USART3_UART_Init-USART3-false-HAL-true,5-MX_UCPD1_Init-UCPD1-false-LL-true RCC.ADC12Freq_Value=150000000 diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.h b/hw/bsp/stm32h7/boards/stm32h743eval/board.h index 666bec9a1..7e3c015c8 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/board.h +++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.h @@ -85,41 +85,60 @@ static inline void board_stm32h7_clock_init(void) RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - /* PLL1 for System Clock */ + // PLL1 for System Clock +#ifdef TRACE_ETM + // From H743 eval board manual + // - ETM can only work at 50 MHz clock by default because ETM signals are shared with other peripherals. If better + // performance of ETM is required (84 MHz/98 MHz), R217, R230, R231, R234, R236, SB2, SB5, SB8, SB11, + // SB42, SB57 must be removed to reduce the stub on ETM signals. In this configuration SAI and PDM are not + // functional and NOR Flash and the address of SRAM are limited on A18. + // - ETM trace function would be abnormal as SAI_SDB share the same pins with TRACE_D0, and TRACE_D0 + // would be forced high by SAI_SDB. When using ETM trace it is necessary to set ADCDAT1 pin (SAI_SDB signal + // of the STM32) of audio codec WM8994ECS/R (U22) by software to be tri-state. + + // Since Trace CLK = PLL1 / 3 --> max PLL1 clock is 150Mhz + RCC_OscInitStruct.PLL.PLLM = 2; + RCC_OscInitStruct.PLL.PLLN = 24; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 4; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLFRACN = 0; +#else + // Set PLL1 to 400Mhz RCC_OscInitStruct.PLL.PLLM = 5; RCC_OscInitStruct.PLL.PLLN = 160; - RCC_OscInitStruct.PLL.PLLFRACN = 0; RCC_OscInitStruct.PLL.PLLP = 2; RCC_OscInitStruct.PLL.PLLR = 2; RCC_OscInitStruct.PLL.PLLQ = 4; - +#endif RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM; RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; HAL_RCC_OscConfig(&RCC_OscInitStruct); - /* PLL3 for USB Clock */ - PeriphClkInitStruct.PLL3.PLL3M = 25; - PeriphClkInitStruct.PLL3.PLL3N = 336; - PeriphClkInitStruct.PLL3.PLL3FRACN = 0; - PeriphClkInitStruct.PLL3.PLL3P = 2; - PeriphClkInitStruct.PLL3.PLL3R = 2; - PeriphClkInitStruct.PLL3.PLL3Q = 7; - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3; - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - - /* Select PLL as system clock source and configure bus clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \ - RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1); + /* Select PLL as system clock source and configure bus clocks dividers */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | + RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_D3PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; - RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4); + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2); + + /* PLL3 for USB Clock */ + PeriphClkInitStruct.PLL3.PLL3M = 25; + PeriphClkInitStruct.PLL3.PLL3N = 336; + PeriphClkInitStruct.PLL3.PLL3FRACN = 0; + PeriphClkInitStruct.PLL3.PLL3P = 2; + PeriphClkInitStruct.PLL3.PLL3Q = 7; + PeriphClkInitStruct.PLL3.PLL3R = 2; + + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); /*activate CSI clock mondatory for I/O Compensation Cell*/ __HAL_RCC_CSI_ENABLE() ; diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc b/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc new file mode 100644 index 000000000..331080c17 --- /dev/null +++ b/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc @@ -0,0 +1,1125 @@ +#MicroXplorer Configuration settings - do not modify +CAD.formats=[] +CAD.pinconfig=Project naming +CAD.provider= +File.Version=6 +GPIO.groupedBy=Group By Peripherals +KeepUserPlacement=false +Mcu.CPN=STM32H743XIH6 +Mcu.Family=STM32H7 +Mcu.IP0=CORTEX_M7 +Mcu.IP1=DEBUG +Mcu.IP2=NVIC +Mcu.IP3=RCC +Mcu.IP4=SYS +Mcu.IP5=USB_OTG_FS +Mcu.IP6=USB_OTG_HS +Mcu.IPNb=7 +Mcu.Name=STM32H743XIHx +Mcu.Package=TFBGA240 +Mcu.Pin0=PI6 +Mcu.Pin1=PI5 +Mcu.Pin10=PA15 (JTDI) +Mcu.Pin100=PC1 +Mcu.Pin101=PC2 +Mcu.Pin102=PC3 +Mcu.Pin103=PJ9 +Mcu.Pin104=PH2 +Mcu.Pin105=PA2 +Mcu.Pin106=PA1 +Mcu.Pin107=PJ0 +Mcu.Pin108=PE10 +Mcu.Pin109=PJ8 +Mcu.Pin11=PI1 +Mcu.Pin110=PJ7 +Mcu.Pin111=PJ6 +Mcu.Pin112=PH3 +Mcu.Pin113=PH4 +Mcu.Pin114=PH5 +Mcu.Pin115=PI15 +Mcu.Pin116=PJ1 +Mcu.Pin117=PF13 +Mcu.Pin118=PF14 +Mcu.Pin119=PE9 +Mcu.Pin12=PI0 +Mcu.Pin120=PE11 +Mcu.Pin121=PB10 +Mcu.Pin122=PB11 +Mcu.Pin123=PH10 +Mcu.Pin124=PH11 +Mcu.Pin125=PD15 +Mcu.Pin126=PD14 +Mcu.Pin127=PA6 +Mcu.Pin128=PA7 +Mcu.Pin129=PB2 +Mcu.Pin13=PI7 +Mcu.Pin130=PF12 +Mcu.Pin131=PF15 +Mcu.Pin132=PE12 +Mcu.Pin133=PE15 +Mcu.Pin134=PJ5 +Mcu.Pin135=PH9 +Mcu.Pin136=PH12 +Mcu.Pin137=PD11 +Mcu.Pin138=PD12 +Mcu.Pin139=PD13 +Mcu.Pin14=PE1 +Mcu.Pin140=PA0_C +Mcu.Pin141=PA5 +Mcu.Pin142=PC4 +Mcu.Pin143=PB1 +Mcu.Pin144=PJ2 +Mcu.Pin145=PF11 +Mcu.Pin146=PG0 +Mcu.Pin147=PE8 +Mcu.Pin148=PE13 +Mcu.Pin149=PH6 +Mcu.Pin15=PB6 +Mcu.Pin150=PH8 +Mcu.Pin151=PB12 +Mcu.Pin152=PB15 +Mcu.Pin153=PD10 +Mcu.Pin154=PD9 +Mcu.Pin155=PA3 +Mcu.Pin156=PA4 +Mcu.Pin157=PC5 +Mcu.Pin158=PB0 +Mcu.Pin159=PJ3 +Mcu.Pin16=PB4 (NJTRST) +Mcu.Pin160=PJ4 +Mcu.Pin161=PG1 +Mcu.Pin162=PE7 +Mcu.Pin163=PE14 +Mcu.Pin164=PH7 +Mcu.Pin165=PB13 +Mcu.Pin166=PB14 +Mcu.Pin167=PD8 +Mcu.Pin168=VP_SYS_VS_Systick +Mcu.Pin17=PK4 +Mcu.Pin18=PG11 +Mcu.Pin19=PJ15 +Mcu.Pin2=PI4 +Mcu.Pin20=PD6 +Mcu.Pin21=PD3 +Mcu.Pin22=PC11 +Mcu.Pin23=PA14 (JTCK/SWCLK) +Mcu.Pin24=PI2 +Mcu.Pin25=PH15 +Mcu.Pin26=PH14 +Mcu.Pin27=PC15-OSC32_OUT (OSC32_OUT) +Mcu.Pin28=PC14-OSC32_IN (OSC32_IN) +Mcu.Pin29=PE2 +Mcu.Pin3=PB5 +Mcu.Pin30=PE0 +Mcu.Pin31=PB7 +Mcu.Pin32=PB3 (JTDO/TRACESWO) +Mcu.Pin33=PK6 +Mcu.Pin34=PK3 +Mcu.Pin35=PG12 +Mcu.Pin36=PD7 +Mcu.Pin37=PC12 +Mcu.Pin38=PI3 +Mcu.Pin39=PA13 (JTMS/SWDIO) +Mcu.Pin4=PK5 +Mcu.Pin40=PE5 +Mcu.Pin41=PE4 +Mcu.Pin42=PE3 +Mcu.Pin43=PB9 +Mcu.Pin44=PB8 +Mcu.Pin45=PG15 +Mcu.Pin46=PK7 +Mcu.Pin47=PG14 +Mcu.Pin48=PG13 +Mcu.Pin49=PJ14 +Mcu.Pin5=PG10 +Mcu.Pin50=PJ12 +Mcu.Pin51=PD2 +Mcu.Pin52=PD0 +Mcu.Pin53=PA10 +Mcu.Pin54=PA9 +Mcu.Pin55=PH13 +Mcu.Pin56=PI9 +Mcu.Pin57=PC13 +Mcu.Pin58=PI8 +Mcu.Pin59=PE6 +Mcu.Pin6=PG9 +Mcu.Pin60=PJ13 +Mcu.Pin61=PD1 +Mcu.Pin62=PC8 +Mcu.Pin63=PC9 +Mcu.Pin64=PA8 +Mcu.Pin65=PA12 +Mcu.Pin66=PA11 +Mcu.Pin67=PI10 +Mcu.Pin68=PI11 +Mcu.Pin69=PC7 +Mcu.Pin7=PD5 +Mcu.Pin70=PC6 +Mcu.Pin71=PG8 +Mcu.Pin72=PG7 +Mcu.Pin73=PF2 +Mcu.Pin74=PF1 +Mcu.Pin75=PF0 +Mcu.Pin76=PG5 +Mcu.Pin77=PG6 +Mcu.Pin78=PI12 +Mcu.Pin79=PI13 +Mcu.Pin8=PD4 +Mcu.Pin80=PI14 +Mcu.Pin81=PF3 +Mcu.Pin82=PG4 +Mcu.Pin83=PG3 +Mcu.Pin84=PG2 +Mcu.Pin85=PK2 +Mcu.Pin86=PH1-OSC_OUT (PH1) +Mcu.Pin87=PH0-OSC_IN (PH0) +Mcu.Pin88=PF5 +Mcu.Pin89=PF4 +Mcu.Pin9=PC10 +Mcu.Pin90=PK0 +Mcu.Pin91=PK1 +Mcu.Pin92=PF6 +Mcu.Pin93=PF7 +Mcu.Pin94=PF8 +Mcu.Pin95=PJ11 +Mcu.Pin96=PC0 +Mcu.Pin97=PF10 +Mcu.Pin98=PF9 +Mcu.Pin99=PJ10 +Mcu.PinsNb=169 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32H743XIHx +MxCube.Version=6.8.1 +MxDb.Version=DB.6.0.81 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:false +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false +PA0_C.GPIOParameters=GPIO_Label +PA0_C.GPIO_Label=Potentiometer +PA0_C.Locked=true +PA0_C.Signal=ADCx_INN1 +PA1.GPIOParameters=GPIO_Label +PA1.GPIO_Label=RMII_REF_CLK [LAN8742A_REFCLK0] +PA1.Locked=true +PA1.Signal=ETH_REF_CLK +PA10.GPIOParameters=GPIO_Label +PA10.GPIO_Label=USB_FS1_ID +PA10.Locked=true +PA10.Signal=USB_OTG_FS_ID +PA11.GPIOParameters=GPIO_Label +PA11.GPIO_Label=USB_FS1_DM +PA11.Locked=true +PA11.Mode=Device_Only +PA11.Signal=USB_OTG_FS_DM +PA12.GPIOParameters=GPIO_Label +PA12.GPIO_Label=USB_FS1_DP +PA12.Locked=true +PA12.Mode=Device_Only +PA12.Signal=USB_OTG_FS_DP +PA13\ (JTMS/SWDIO).Locked=true +PA13\ (JTMS/SWDIO).Mode=Trace_Synchro_4bits_SW +PA13\ (JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO +PA14\ (JTCK/SWCLK).Locked=true +PA14\ (JTCK/SWCLK).Mode=Trace_Synchro_4bits_SW +PA14\ (JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK +PA15\ (JTDI).GPIOParameters=GPIO_Label +PA15\ (JTDI).GPIO_Label=TDI +PA15\ (JTDI).Locked=true +PA15\ (JTDI).Signal=DEBUG_JTDI +PA2.GPIOParameters=GPIO_Label +PA2.GPIO_Label=ETH_MDIO [LAN8742A_MDIO] +PA2.Locked=true +PA2.Signal=ETH_MDIO +PA3.GPIOParameters=GPIO_Label +PA3.GPIO_Label=ULPI_D0 [USB3320C_D0] +PA3.Locked=true +PA3.Mode=Device_HS +PA3.Signal=USB_OTG_HS_ULPI_D0 +PA4.GPIOParameters=GPIO_Label +PA4.GPIO_Label=LED3_RGB [LD3_Red] +PA4.Locked=true +PA4.Signal=GPIO_Output +PA5.GPIOParameters=GPIO_Label +PA5.GPIO_Label=ULPI_CK [USB3320C_CLKOUT] +PA5.Locked=true +PA5.Mode=Device_HS +PA5.Signal=USB_OTG_HS_ULPI_CK +PA6.GPIOParameters=GPIO_Label +PA6.GPIO_Label=LCD_BL_CTRL +PA6.Locked=true +PA6.Signal=GPIO_Output +PA7.GPIOParameters=GPIO_Label +PA7.GPIO_Label=RMII_CRS_DV [LAN8742A_CRS_DV] +PA7.Locked=true +PA7.Signal=ETH_CRS_DV +PA8.GPIOParameters=GPIO_Label +PA8.GPIO_Label=MCO +PA8.Locked=true +PA8.Signal=RCC_MCO_1 +PA9.GPIOParameters=GPIO_Label +PA9.GPIO_Label=VBUS_FS1 +PA9.Locked=true +PA9.Signal=USB_OTG_FS_VBUS +PB0.GPIOParameters=GPIO_Label +PB0.GPIO_Label=ULPI_D1 [USB3320C_D1] +PB0.Locked=true +PB0.Mode=Device_HS +PB0.Signal=USB_OTG_HS_ULPI_D1 +PB1.GPIOParameters=GPIO_Label +PB1.GPIO_Label=ULPI_D2 [USB3320C_D2] +PB1.Locked=true +PB1.Mode=Device_HS +PB1.Signal=USB_OTG_HS_ULPI_D2 +PB10.GPIOParameters=GPIO_Label +PB10.GPIO_Label=ULPI_D3 [USB3320C_D3] +PB10.Locked=true +PB10.Mode=Device_HS +PB10.Signal=USB_OTG_HS_ULPI_D3 +PB11.GPIOParameters=GPIO_Label +PB11.GPIO_Label=ULPI_D4 [USB3320C_D4] +PB11.Locked=true +PB11.Mode=Device_HS +PB11.Signal=USB_OTG_HS_ULPI_D4 +PB12.GPIOParameters=GPIO_Label +PB12.GPIO_Label=ULPI_D5 [USB3320C_D5] +PB12.Locked=true +PB12.Mode=Device_HS +PB12.Signal=USB_OTG_HS_ULPI_D5 +PB13.GPIOParameters=GPIO_Label +PB13.GPIO_Label=ULPI_D6 [USB3320C_D6] +PB13.Locked=true +PB13.Mode=Device_HS +PB13.Signal=USB_OTG_HS_ULPI_D6 +PB14.GPIOParameters=GPIO_Label +PB14.GPIO_Label=RS232_TX [ST3241EBPR_T2IN] +PB14.Locked=true +PB14.Signal=USART1_TX +PB15.GPIOParameters=GPIO_Label +PB15.GPIO_Label=RS_232RX [ST3241EBPR_R3OUT] +PB15.Locked=true +PB15.Signal=USART1_RX +PB2.GPIOParameters=GPIO_Label +PB2.GPIO_Label=QSPI_CLK [MT25TL01GHBA8ESF_CLK_1] +PB2.Locked=true +PB2.Signal=QUADSPI_CLK +PB3\ (JTDO/TRACESWO).Locked=true +PB3\ (JTDO/TRACESWO).Signal=DEBUG_JTDO-SWO +PB4\ (NJTRST).GPIOParameters=GPIO_Label +PB4\ (NJTRST).GPIO_Label=TRST +PB4\ (NJTRST).Locked=true +PB4\ (NJTRST).Signal=DEBUG_JTRST +PB5.GPIOParameters=GPIO_Label +PB5.GPIO_Label=ULPI_D7 [USB3320C_D7] +PB5.Locked=true +PB5.Mode=Device_HS +PB5.Signal=USB_OTG_HS_ULPI_D7 +PB6.GPIOParameters=GPIO_Label +PB6.GPIO_Label=I2C1_SCL [STM32L152CCT6_I2C_SCL] +PB6.Locked=true +PB6.Signal=I2C1_SCL +PB7.GPIOParameters=GPIO_Label +PB7.GPIO_Label=I2C1_SDA [STM32L152CCT6_I2C_SDA] +PB7.Locked=true +PB7.Signal=I2C1_SDA +PB8.GPIOParameters=GPIO_Label +PB8.GPIO_Label=SDIO1_CKIN +PB8.Locked=true +PB8.Signal=SDMMC1_CKIN +PB9.GPIOParameters=GPIO_Label +PB9.GPIO_Label=SDIO1_CDIR +PB9.Locked=true +PB9.Signal=SDMMC1_CDIR +PC0.GPIOParameters=GPIO_Label +PC0.GPIO_Label=ULPI_STP [USB3320C_STP] +PC0.Locked=true +PC0.Mode=Device_HS +PC0.Signal=USB_OTG_HS_ULPI_STP +PC1.GPIOParameters=GPIO_Label +PC1.GPIO_Label=RMII_MDC [LAN8742A_MDC] +PC1.Locked=true +PC1.Signal=ETH_MDC +PC10.GPIOParameters=GPIO_Label +PC10.GPIO_Label=SDIO1_D2 +PC10.Locked=true +PC10.Signal=SDMMC1_D2 +PC11.GPIOParameters=GPIO_Label +PC11.GPIO_Label=SDIO1_D3 +PC11.Locked=true +PC11.Signal=SDMMC1_D3 +PC12.GPIOParameters=GPIO_Label +PC12.GPIO_Label=SDIO1_CLK +PC12.Locked=true +PC12.Signal=SDMMC1_CK +PC13.GPIOParameters=GPIO_Label +PC13.GPIO_Label=TAMPER_KEY [B1] +PC13.Locked=true +PC13.Signal=RTC_TAMP1 +PC14-OSC32_IN\ (OSC32_IN).Locked=true +PC14-OSC32_IN\ (OSC32_IN).Signal=RCC_OSC32_IN +PC15-OSC32_OUT\ (OSC32_OUT).Locked=true +PC15-OSC32_OUT\ (OSC32_OUT).Signal=RCC_OSC32_OUT +PC2.GPIOParameters=GPIO_Label +PC2.GPIO_Label=DFSDM_CLK +PC2.Locked=true +PC2.Signal=S_CKOUTDFSDM1 +PC3.GPIOParameters=GPIO_Label +PC3.GPIO_Label=DFSM_DAT1 +PC3.Locked=true +PC3.Signal=S_DATAIN1DFSDM1 +PC4.GPIOParameters=GPIO_Label +PC4.GPIO_Label=RMII_RXD0 [LAN8742A_RXD0] +PC4.Locked=true +PC4.Signal=ETH_RXD0 +PC5.GPIOParameters=GPIO_Label +PC5.GPIO_Label=RMII_RXD1 [LAN8742A_RXD1] +PC5.Locked=true +PC5.Signal=ETH_RXD1 +PC6.GPIOParameters=GPIO_Label +PC6.GPIO_Label=SDIO1_D0DIR +PC6.Locked=true +PC6.Signal=SDMMC1_D0DIR +PC7.Locked=true +PC7.Signal=DEBUG_TRGIO +PC8.GPIOParameters=GPIO_Label +PC8.GPIO_Label=SDIO1_D0 +PC8.Locked=true +PC8.Signal=SDMMC1_D0 +PC9.GPIOParameters=GPIO_Label +PC9.GPIO_Label=SDIO1_D1 +PC9.Locked=true +PC9.Signal=SDMMC1_D1 +PD0.GPIOParameters=GPIO_Label +PD0.GPIO_Label=D2 [IS42S32800G_DQ2] +PD0.Locked=true +PD0.Signal=FMC_D2_DA2 +PD1.GPIOParameters=GPIO_Label +PD1.GPIO_Label=D3 [IS42S32800G_DQ3] +PD1.Locked=true +PD1.Signal=FMC_D3_DA3 +PD10.GPIOParameters=GPIO_Label +PD10.GPIO_Label=D15 [IS42S32800G_DQ15] +PD10.Locked=true +PD10.Signal=FMC_D15_DA15 +PD11.GPIOParameters=GPIO_Label +PD11.GPIO_Label=A16 [PC28F128M29EWLA_A16] +PD11.Locked=true +PD11.Signal=FMC_A16_CLE +PD12.GPIOParameters=GPIO_Label +PD12.GPIO_Label=A17 [PC28F128M29EWLA_A17] +PD12.Locked=true +PD12.Signal=FMC_A17_ALE +PD13.GPIOParameters=GPIO_Label +PD13.GPIO_Label=A18 [PC28F128M29EWLA_A18] +PD13.Locked=true +PD13.Signal=FMC_A18 +PD14.GPIOParameters=GPIO_Label +PD14.GPIO_Label=D0 [IS42S32800G_DQ0] +PD14.Locked=true +PD14.Signal=FMC_D0_DA0 +PD15.GPIOParameters=GPIO_Label +PD15.GPIO_Label=D1 [IS42S32800G_DQ1] +PD15.Locked=true +PD15.Signal=FMC_D1_DA1 +PD2.GPIOParameters=GPIO_Label +PD2.GPIO_Label=SDIO1_CMD +PD2.Locked=true +PD2.Signal=SDMMC1_CMD +PD3.GPIOParameters=GPIO_Label +PD3.GPIO_Label=FDCAN1_STBY [MCP2562FD_STBY] +PD3.Locked=true +PD3.Signal=GPIO_Output +PD4.GPIOParameters=GPIO_Label +PD4.GPIO_Label=FMC_NOE [IS61WV102416BLL_OE] +PD4.Locked=true +PD4.Signal=FMC_NOE +PD5.GPIOParameters=GPIO_Label +PD5.GPIO_Label=FMC_NWE [IS61WV102416BLL_WE] +PD5.Locked=true +PD5.Signal=FMC_NWE +PD6.GPIOParameters=GPIO_Label +PD6.GPIO_Label=FMC_NWAIT [PC28F128M29EWLA_RB] +PD6.Locked=true +PD6.Signal=FMC_NWAIT +PD7.GPIOParameters=GPIO_Label +PD7.GPIO_Label=FMC_NE1 [PC28F128M29EWLA_E] +PD7.Locked=true +PD7.Signal=FMC_NE1 +PD8.GPIOParameters=GPIO_Label +PD8.GPIO_Label=D13 [IS42S32800G_DQ13] +PD8.Locked=true +PD8.Signal=FMC_D13_DA13 +PD9.GPIOParameters=GPIO_Label +PD9.GPIO_Label=D14 [IS42S32800G_DQ14] +PD9.Locked=true +PD9.Signal=FMC_D14_DA14 +PE0.GPIOParameters=GPIO_Label +PE0.GPIO_Label=FMC_NBL0 [IS42S32800G_DQM0] +PE0.Locked=true +PE0.Signal=FMC_NBL0 +PE1.GPIOParameters=GPIO_Label +PE1.GPIO_Label=FMC_NBL1 [IS42S32800G_DQM1] +PE1.Locked=true +PE1.Signal=FMC_NBL1 +PE10.GPIOParameters=GPIO_Label +PE10.GPIO_Label=D7 [IS42S32800G_DQ7] +PE10.Locked=true +PE10.Signal=FMC_D7_DA7 +PE11.GPIOParameters=GPIO_Label +PE11.GPIO_Label=D8 [IS42S32800G_DQ8] +PE11.Locked=true +PE11.Signal=FMC_D8_DA8 +PE12.GPIOParameters=GPIO_Label +PE12.GPIO_Label=D9 [IS42S32800G_DQ9] +PE12.Locked=true +PE12.Signal=FMC_D9_DA9 +PE13.GPIOParameters=GPIO_Label +PE13.GPIO_Label=D10 [IS42S32800G_DQ10] +PE13.Locked=true +PE13.Signal=FMC_D10_DA10 +PE14.GPIOParameters=GPIO_Label +PE14.GPIO_Label=D11 [IS42S32800G_DQ11] +PE14.Locked=true +PE14.Signal=FMC_D11_DA11 +PE15.GPIOParameters=GPIO_Label +PE15.GPIO_Label=D12 [IS42S32800G_DQ12] +PE15.Locked=true +PE15.Signal=FMC_D12_DA12 +PE2.Locked=true +PE2.Mode=Trace_Synchro_4bits_SW +PE2.Signal=DEBUG_TRACECLK +PE3.Locked=true +PE3.Mode=Trace_Synchro_4bits_SW +PE3.Signal=DEBUG_TRACED0 +PE4.Locked=true +PE4.Mode=Trace_Synchro_4bits_SW +PE4.Signal=DEBUG_TRACED1 +PE5.Locked=true +PE5.Mode=Trace_Synchro_4bits_SW +PE5.Signal=DEBUG_TRACED2 +PE6.Locked=true +PE6.Mode=Trace_Synchro_4bits_SW +PE6.Signal=DEBUG_TRACED3 +PE7.GPIOParameters=GPIO_Label +PE7.GPIO_Label=D4 [IS42S32800G_DQ4] +PE7.Locked=true +PE7.Signal=FMC_D4_DA4 +PE8.GPIOParameters=GPIO_Label +PE8.GPIO_Label=D5 [IS42S32800G_DQ5] +PE8.Locked=true +PE8.Signal=FMC_D5_DA5 +PE9.GPIOParameters=GPIO_Label +PE9.GPIO_Label=D6 [IS42S32800G_DQ6] +PE9.Locked=true +PE9.Signal=FMC_D6_DA6 +PF0.GPIOParameters=GPIO_Label +PF0.GPIO_Label=A0 [PC28F128M29EWLA_A0] +PF0.Locked=true +PF0.Signal=FMC_A0 +PF1.GPIOParameters=GPIO_Label +PF1.GPIO_Label=A1 [PC28F128M29EWLA_A1] +PF1.Locked=true +PF1.Signal=FMC_A1 +PF10.GPIOParameters=GPIO_Label +PF10.GPIO_Label=LED1_RGB [LD1_Green] +PF10.Locked=true +PF10.Signal=GPIO_Output +PF11.GPIOParameters=GPIO_Label +PF11.GPIO_Label=SNDRAS [IS42S32800G_RAS] +PF11.Locked=true +PF11.Signal=FMC_SDNRAS +PF12.GPIOParameters=GPIO_Label +PF12.GPIO_Label=A6 [PC28F128M29EWLA_A6] +PF12.Locked=true +PF12.Signal=FMC_A6 +PF13.GPIOParameters=GPIO_Label +PF13.GPIO_Label=A7 [PC28F128M29EWLA_A7] +PF13.Locked=true +PF13.Signal=FMC_A7 +PF14.GPIOParameters=GPIO_Label +PF14.GPIO_Label=A8 [PC28F128M29EWLA_A8] +PF14.Locked=true +PF14.Signal=FMC_A8 +PF15.GPIOParameters=GPIO_Label +PF15.GPIO_Label=A9 [PC28F128M29EWLA_A9] +PF15.Locked=true +PF15.Signal=FMC_A9 +PF2.GPIOParameters=GPIO_Label +PF2.GPIO_Label=A2 [PC28F128M29EWLA_A2] +PF2.Locked=true +PF2.Signal=FMC_A2 +PF3.GPIOParameters=GPIO_Label +PF3.GPIO_Label=A3 [PC28F128M29EWLA_A3] +PF3.Locked=true +PF3.Signal=FMC_A3 +PF4.GPIOParameters=GPIO_Label +PF4.GPIO_Label=A4 [PC28F128M29EWLA_A4] +PF4.Locked=true +PF4.Signal=FMC_A4 +PF5.GPIOParameters=GPIO_Label +PF5.GPIO_Label=A5 [PC28F128M29EWLA_A5] +PF5.Locked=true +PF5.Signal=FMC_A5 +PF6.GPIOParameters=GPIO_Label +PF6.GPIO_Label=QSPI_BK1_IO3 [MT25TL01GHBA8ESF_DQ3] +PF6.Locked=true +PF6.Signal=QUADSPI_BK1_IO3 +PF7.GPIOParameters=GPIO_Label +PF7.GPIO_Label=QSPI_BK1_IO2 [MT25TL01GHBA8ESF_DQ2] +PF7.Locked=true +PF7.Signal=QUADSPI_BK1_IO2 +PF8.GPIOParameters=GPIO_Label +PF8.GPIO_Label=QSPI_BK1_IO0 [MT25TL01GHBA8ESF_DQ0] +PF8.Locked=true +PF8.Signal=QUADSPI_BK1_IO0 +PF9.GPIOParameters=GPIO_Label +PF9.GPIO_Label=QSPI_BK1_IO1 [MT25TL01GHBA8ESF_DQ1] +PF9.Locked=true +PF9.Signal=QUADSPI_BK1_IO1 +PG0.GPIOParameters=GPIO_Label +PG0.GPIO_Label=A10 [PC28F128M29EWLA_A10] +PG0.Locked=true +PG0.Signal=FMC_A10 +PG1.GPIOParameters=GPIO_Label +PG1.GPIO_Label=A11 [PC28F128M29EWLA_A11] +PG1.Locked=true +PG1.Signal=FMC_A11 +PG10.GPIOParameters=GPIO_Label +PG10.GPIO_Label=FMC_NE3 [IS61WV102416BLL_CE] +PG10.Locked=true +PG10.Signal=FMC_NE3 +PG11.GPIOParameters=GPIO_Label +PG11.GPIO_Label=RMII_TX_EN [LAN8742A_TXEN] +PG11.Locked=true +PG11.Signal=ETH_TX_EN +PG12.GPIOParameters=GPIO_Label +PG12.GPIO_Label=RMII_TXD1 [LAN8742A_TXD1] +PG12.Locked=true +PG12.Signal=ETH_TXD1 +PG13.GPIOParameters=GPIO_Label +PG13.GPIO_Label=RMII_TXD0 [LAN8742A_TXD0] +PG13.Locked=true +PG13.Signal=ETH_TXD0 +PG14.GPIOParameters=GPIO_Label +PG14.GPIO_Label=QSPI_BK2_IO3 [MT25TL01GHBA8ESF_DQ7] +PG14.Locked=true +PG14.Signal=QUADSPI_BK2_IO3 +PG15.GPIOParameters=GPIO_Label +PG15.GPIO_Label=SDNCAS [IS42S32800G_CAS] +PG15.Locked=true +PG15.Signal=FMC_SDNCAS +PG2.GPIOParameters=GPIO_Label +PG2.GPIO_Label=A12 [PC28F128M29EWLA_A12] +PG2.Locked=true +PG2.Signal=FMC_A12 +PG3.GPIOParameters=GPIO_Label +PG3.GPIO_Label=A13 [PC28F128M29EWLA_A13] +PG3.Locked=true +PG3.Signal=FMC_A13 +PG4.Locked=true +PG4.Signal=FMC_A14_BA0 +PG5.Locked=true +PG5.Signal=FMC_A15_BA1 +PG6.GPIOParameters=GPIO_Label +PG6.GPIO_Label=QSPI_BK1_NCS [MT25TL01GHBA8ESF_CS] +PG6.Locked=true +PG6.Signal=QUADSPI_BK1_NCS +PG7.GPIOParameters=GPIO_Label +PG7.GPIO_Label=SAI1_MCLKA [WM8994ECS_MCLK1] +PG7.Locked=true +PG7.Signal=SAI1_MCLK_A +PG8.GPIOParameters=GPIO_Label +PG8.GPIO_Label=SDCLK [IS42S32800G_CLK] +PG8.Locked=true +PG8.Signal=FMC_SDCLK +PG9.GPIOParameters=GPIO_Label +PG9.GPIO_Label=QSPI_BK2_IO2 [MT25TL01GHBA8ESF_DQ6] +PG9.Locked=true +PG9.Signal=QUADSPI_BK2_IO2 +PH0-OSC_IN\ (PH0).Locked=true +PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator +PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN +PH1-OSC_OUT\ (PH1).Locked=true +PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator +PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT +PH10.GPIOParameters=GPIO_Label +PH10.GPIO_Label=D18 [IS42S32800G_DQ18] +PH10.Locked=true +PH10.Signal=FMC_D18 +PH11.GPIOParameters=GPIO_Label +PH11.GPIO_Label=D19 [IS42S32800G_DQ19] +PH11.Locked=true +PH11.Signal=FMC_D19 +PH12.GPIOParameters=GPIO_Label +PH12.GPIO_Label=D20 [IS42S32800G_DQ20] +PH12.Locked=true +PH12.Signal=FMC_D20 +PH13.GPIOParameters=GPIO_Label +PH13.GPIO_Label=D21 [IS42S32800G_DQ21] +PH13.Locked=true +PH13.Signal=FMC_D21 +PH14.GPIOParameters=GPIO_Label +PH14.GPIO_Label=D22 [IS42S32800G_DQ22] +PH14.Locked=true +PH14.Signal=FMC_D22 +PH15.GPIOParameters=GPIO_Label +PH15.GPIO_Label=D23 [IS42S32800G_DQ23] +PH15.Locked=true +PH15.Signal=FMC_D23 +PH2.GPIOParameters=GPIO_Label +PH2.GPIO_Label=QSPI_BK2_IO0 [MT25TL01GHBA8ESF_DQ4] +PH2.Locked=true +PH2.Signal=QUADSPI_BK2_IO0 +PH3.GPIOParameters=GPIO_Label +PH3.GPIO_Label=QSPI_BK2_IO1 [MT25TL01GHBA8ESF_DQ5] +PH3.Locked=true +PH3.Signal=QUADSPI_BK2_IO1 +PH4.GPIOParameters=GPIO_Label +PH4.GPIO_Label=ULPI_NXT [USB3320C_NXT] +PH4.Locked=true +PH4.Mode=Device_HS +PH4.Signal=USB_OTG_HS_ULPI_NXT +PH5.GPIOParameters=GPIO_Label +PH5.GPIO_Label=SDNWE [IS42S32800G_WE] +PH5.Locked=true +PH5.Signal=FMC_SDNWE +PH6.GPIOParameters=GPIO_Label +PH6.GPIO_Label=SDNE1 [IS42S32800G_CS] +PH6.Locked=true +PH6.Signal=FMC_SDNE1 +PH7.GPIOParameters=GPIO_Label +PH7.GPIO_Label=SDCKE1 [IS42S32800G_CKE] +PH7.Locked=true +PH7.Signal=FMC_SDCKE1 +PH8.GPIOParameters=GPIO_Label +PH8.GPIO_Label=D16 [IS42S32800G_DQ16] +PH8.Locked=true +PH8.Signal=FMC_D16 +PH9.GPIOParameters=GPIO_Label +PH9.GPIO_Label=D17 [IS42S32800G_DQ17] +PH9.Locked=true +PH9.Signal=FMC_D17 +PI0.GPIOParameters=GPIO_Label +PI0.GPIO_Label=D24 [IS42S32800G_DQ24] +PI0.Locked=true +PI0.Signal=FMC_D24 +PI1.GPIOParameters=GPIO_Label +PI1.GPIO_Label=D25 [IS42S32800G_DQ25] +PI1.Locked=true +PI1.Signal=FMC_D25 +PI10.GPIOParameters=GPIO_Label +PI10.GPIO_Label=D31 [IS42S32800G_DQ31] +PI10.Locked=true +PI10.Signal=FMC_D31 +PI11.GPIOParameters=GPIO_Label +PI11.GPIO_Label=ULPI_DIR [USB3320C_DIR] +PI11.Locked=true +PI11.Mode=Device_HS +PI11.Signal=USB_OTG_HS_ULPI_DIR +PI12.GPIOParameters=GPIO_Label +PI12.GPIO_Label=LCD_HSYNC +PI12.Locked=true +PI12.Signal=LTDC_HSYNC +PI13.GPIOParameters=GPIO_Label +PI13.GPIO_Label=LCD_VSYNC +PI13.Locked=true +PI13.Signal=LTDC_VSYNC +PI14.GPIOParameters=GPIO_Label +PI14.GPIO_Label=LCD_CLK +PI14.Locked=true +PI14.Signal=LTDC_CLK +PI15.GPIOParameters=GPIO_Label +PI15.GPIO_Label=LCD_R0 +PI15.Locked=true +PI15.Signal=LTDC_R0 +PI2.GPIOParameters=GPIO_Label +PI2.GPIO_Label=D26 [IS42S32800G_DQ26] +PI2.Locked=true +PI2.Signal=FMC_D26 +PI3.GPIOParameters=GPIO_Label +PI3.GPIO_Label=D27 [IS42S32800G_DQ27 +PI3.Locked=true +PI3.Signal=FMC_D27 +PI4.GPIOParameters=GPIO_Label +PI4.GPIO_Label=FMC_NBL2 [IS42S32800G_DQM2] +PI4.Locked=true +PI4.Signal=FMC_NBL2 +PI5.GPIOParameters=GPIO_Label +PI5.GPIO_Label=FMC_NBL3 [IS42S32800G_DQM3] +PI5.Locked=true +PI5.Signal=FMC_NBL3 +PI6.GPIOParameters=GPIO_Label +PI6.GPIO_Label=D28 [IS42S32800G_DQ28] +PI6.Locked=true +PI6.Signal=FMC_D28 +PI7.GPIOParameters=GPIO_Label +PI7.GPIO_Label=D29 [IS42S32800G_DQ29] +PI7.Locked=true +PI7.Signal=FMC_D29 +PI8.GPIOParameters=GPIO_Label +PI8.GPIO_Label=MFX_IRQOUT [MFX_V3_IRQOUT] +PI8.Locked=true +PI8.Signal=GPXTI8 +PI9.GPIOParameters=GPIO_Label +PI9.GPIO_Label=D30 [IS42S32800G_DQ30] +PI9.Locked=true +PI9.Signal=FMC_D30 +PJ0.GPIOParameters=GPIO_Label +PJ0.GPIO_Label=LCD_R1 +PJ0.Locked=true +PJ0.Signal=LTDC_R1 +PJ1.GPIOParameters=GPIO_Label +PJ1.GPIO_Label=LCD_R2 +PJ1.Locked=true +PJ1.Signal=LTDC_R2 +PJ10.GPIOParameters=GPIO_Label +PJ10.GPIO_Label=LCd_G3 +PJ10.Locked=true +PJ10.Signal=LTDC_G3 +PJ11.GPIOParameters=GPIO_Label +PJ11.GPIO_Label=LCD_G4 +PJ11.Locked=true +PJ11.Signal=LTDC_G4 +PJ12.Locked=true +PJ12.Signal=DEBUG_TRGOUT +PJ13.GPIOParameters=GPIO_Label +PJ13.GPIO_Label=LCD_B1 +PJ13.Locked=true +PJ13.Signal=LTDC_B1 +PJ14.GPIOParameters=GPIO_Label +PJ14.GPIO_Label=LCD_B2 +PJ14.Locked=true +PJ14.Signal=LTDC_B2 +PJ15.GPIOParameters=GPIO_Label +PJ15.GPIO_Label=LCD_B3 +PJ15.Locked=true +PJ15.Signal=LTDC_B3 +PJ2.GPIOParameters=GPIO_Label +PJ2.GPIO_Label=LCD_R3 +PJ2.Locked=true +PJ2.Signal=LTDC_R3 +PJ3.GPIOParameters=GPIO_Label +PJ3.GPIO_Label=LCD_R4 +PJ3.Locked=true +PJ3.Signal=LTDC_R4 +PJ4.GPIOParameters=GPIO_Label +PJ4.GPIO_Label=LCD_R5 +PJ4.Locked=true +PJ4.Signal=LTDC_R5 +PJ5.GPIOParameters=GPIO_Label +PJ5.GPIO_Label=LCD_R6 +PJ5.Locked=true +PJ5.Signal=LTDC_R6 +PJ6.GPIOParameters=GPIO_Label +PJ6.GPIO_Label=LCD_R7 +PJ6.Locked=true +PJ6.Signal=LTDC_R7 +PJ7.Locked=true +PJ7.Signal=DEBUG_TRGIN +PJ8.GPIOParameters=GPIO_Label +PJ8.GPIO_Label=LCD_G1 +PJ8.Locked=true +PJ8.Signal=LTDC_G1 +PJ9.GPIOParameters=GPIO_Label +PJ9.GPIO_Label=LCD_G2 +PJ9.Locked=true +PJ9.Signal=LTDC_G2 +PK0.GPIOParameters=GPIO_Label +PK0.GPIO_Label=LCD_G5 +PK0.Locked=true +PK0.Signal=LTDC_G5 +PK1.GPIOParameters=GPIO_Label +PK1.GPIO_Label=LCD_G6 +PK1.Locked=true +PK1.Signal=LTDC_G6 +PK2.GPIOParameters=GPIO_Label +PK2.GPIO_Label=LCD_G7 +PK2.Locked=true +PK2.Signal=LTDC_G7 +PK3.GPIOParameters=GPIO_Label +PK3.GPIO_Label=LCD_B4 +PK3.Locked=true +PK3.Signal=LTDC_B4 +PK4.GPIOParameters=GPIO_Label +PK4.GPIO_Label=LCD_B5 +PK4.Locked=true +PK4.Signal=LTDC_B5 +PK5.GPIOParameters=GPIO_Label +PK5.GPIO_Label=LCD_B6 +PK5.Locked=true +PK5.Signal=LTDC_B6 +PK6.GPIOParameters=GPIO_Label +PK6.GPIO_Label=LCD_B7 +PK6.Locked=true +PK6.Signal=LTDC_B7 +PK7.GPIOParameters=GPIO_Label +PK7.GPIO_Label=LCD_DE +PK7.Locked=true +PK7.Signal=LTDC_DE +PinOutPanel.CurrentBGAView=Top +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32H743XIHx +ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.11.0 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=2 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=stm32h743eval.ioc +ProjectManager.ProjectName=stm32h743eval +ProjectManager.ProjectStructure= +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=Makefile +ProjectManager.ToolChainLocation=Src +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,4-MX_USB_OTG_HS_PCD_Init-USB_OTG_HS-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true +RCC.ADCFreq_Value=50390625 +RCC.AHB12Freq_Value=150000000 +RCC.AHB4Freq_Value=150000000 +RCC.APB1Freq_Value=75000000 +RCC.APB2Freq_Value=75000000 +RCC.APB3Freq_Value=75000000 +RCC.APB4Freq_Value=75000000 +RCC.AXIClockFreq_Value=150000000 +RCC.CECFreq_Value=32000 +RCC.CKPERFreq_Value=64000000 +RCC.CortexFreq_Value=150000000 +RCC.CpuClockFreq_Value=150000000 +RCC.D1CPREFreq_Value=150000000 +RCC.D1PPRE=RCC_APB3_DIV2 +RCC.D2PPRE1=RCC_APB1_DIV2 +RCC.D2PPRE2=RCC_APB2_DIV2 +RCC.D3PPRE=RCC_APB4_DIV2 +RCC.DFSDMACLkFreq_Value=75000000 +RCC.DFSDMFreq_Value=75000000 +RCC.DIVM1=2 +RCC.DIVM3=25 +RCC.DIVN1=24 +RCC.DIVN3=336 +RCC.DIVP1Freq_Value=150000000 +RCC.DIVP2Freq_Value=50390625 +RCC.DIVP3Freq_Value=168000000 +RCC.DIVQ1=4 +RCC.DIVQ1Freq_Value=75000000 +RCC.DIVQ2Freq_Value=50390625 +RCC.DIVQ3=7 +RCC.DIVQ3Freq_Value=48000000 +RCC.DIVR1Freq_Value=150000000 +RCC.DIVR2Freq_Value=50390625 +RCC.DIVR3Freq_Value=168000000 +RCC.EnbaleCSS=true +RCC.FDCANFreq_Value=75000000 +RCC.FMCFreq_Value=150000000 +RCC.FamilyName=M +RCC.HCLK3ClockFreq_Value=150000000 +RCC.HCLKFreq_Value=150000000 +RCC.HPREFreq_Value=64000000 +RCC.HRTIMFreq_Value=150000000 +RCC.HSICalibrationValue=32 +RCC.I2C123Freq_Value=75000000 +RCC.I2C4Freq_Value=75000000 +RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM3,DIVN1,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,EnbaleCSS,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPREFreq_Value,HRTIMFreq_Value,HSICalibrationValue,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLL3FRACN,PLLFRACN,PLLSourceVirtual,PWR_Regulator_Voltage_Scale,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBCLockSelection,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value +RCC.LPTIM1Freq_Value=75000000 +RCC.LPTIM2Freq_Value=75000000 +RCC.LPTIM345Freq_Value=75000000 +RCC.LPUART1Freq_Value=75000000 +RCC.LTDCFreq_Value=168000000 +RCC.MCO1PinFreq_Value=64000000 +RCC.MCO2PinFreq_Value=150000000 +RCC.PLL2FRACN=0 +RCC.PLL3FRACN=0 +RCC.PLLFRACN=0 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +RCC.PWR_Regulator_Voltage_Scale=PWR_REGULATOR_VOLTAGE_SCALE1 +RCC.QSPIFreq_Value=150000000 +RCC.RNGFreq_Value=48000000 +RCC.RTCFreq_Value=32000 +RCC.SAI1Freq_Value=75000000 +RCC.SAI23Freq_Value=75000000 +RCC.SAI4AFreq_Value=75000000 +RCC.SAI4BFreq_Value=75000000 +RCC.SDMMCFreq_Value=75000000 +RCC.SPDIFRXFreq_Value=75000000 +RCC.SPI123Freq_Value=75000000 +RCC.SPI45Freq_Value=75000000 +RCC.SPI6Freq_Value=75000000 +RCC.SWPMI1Freq_Value=75000000 +RCC.SYSCLKFreq_VALUE=150000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.Tim1OutputFreq_Value=150000000 +RCC.Tim2OutputFreq_Value=150000000 +RCC.TraceFreq_Value=150000000 +RCC.USART16Freq_Value=75000000 +RCC.USART234578Freq_Value=75000000 +RCC.USBCLockSelection=RCC_USBCLKSOURCE_PLL3 +RCC.USBFreq_Value=48000000 +RCC.VCO1OutputFreq_Value=300000000 +RCC.VCO2OutputFreq_Value=100781250 +RCC.VCO3OutputFreq_Value=336000000 +RCC.VCOInput1Freq_Value=12500000 +RCC.VCOInput2Freq_Value=781250 +RCC.VCOInput3Freq_Value=1000000 +SH.ADCx_INN1.0=ADC1_INN1 +SH.ADCx_INN1.ConfNb=1 +SH.FMC_A0.0=FMC_A0 +SH.FMC_A0.ConfNb=1 +SH.FMC_A1.0=FMC_A1 +SH.FMC_A1.ConfNb=1 +SH.FMC_A10.0=FMC_A10 +SH.FMC_A10.ConfNb=1 +SH.FMC_A11.0=FMC_A11 +SH.FMC_A11.ConfNb=1 +SH.FMC_A12.0=FMC_A12 +SH.FMC_A12.ConfNb=1 +SH.FMC_A13.0=FMC_A13 +SH.FMC_A13.ConfNb=1 +SH.FMC_A14_BA0.0=FMC_BA0 +SH.FMC_A14_BA0.1=FMC_A14 +SH.FMC_A14_BA0.ConfNb=2 +SH.FMC_A15_BA1.0=FMC_BA1 +SH.FMC_A15_BA1.1=FMC_A15 +SH.FMC_A15_BA1.ConfNb=2 +SH.FMC_A16_CLE.0=FMC_A16 +SH.FMC_A16_CLE.ConfNb=1 +SH.FMC_A17_ALE.0=FMC_A17 +SH.FMC_A17_ALE.ConfNb=1 +SH.FMC_A18.0=FMC_A18 +SH.FMC_A18.ConfNb=1 +SH.FMC_A2.0=FMC_A2 +SH.FMC_A2.ConfNb=1 +SH.FMC_A3.0=FMC_A3 +SH.FMC_A3.ConfNb=1 +SH.FMC_A4.0=FMC_A4 +SH.FMC_A4.ConfNb=1 +SH.FMC_A5.0=FMC_A5 +SH.FMC_A5.ConfNb=1 +SH.FMC_A6.0=FMC_A6 +SH.FMC_A6.ConfNb=1 +SH.FMC_A7.0=FMC_A7 +SH.FMC_A7.ConfNb=1 +SH.FMC_A8.0=FMC_A8 +SH.FMC_A8.ConfNb=1 +SH.FMC_A9.0=FMC_A9 +SH.FMC_A9.ConfNb=1 +SH.FMC_D0_DA0.0=FMC_D0 +SH.FMC_D0_DA0.ConfNb=1 +SH.FMC_D10_DA10.0=FMC_D10 +SH.FMC_D10_DA10.ConfNb=1 +SH.FMC_D11_DA11.0=FMC_D11 +SH.FMC_D11_DA11.ConfNb=1 +SH.FMC_D12_DA12.0=FMC_D12 +SH.FMC_D12_DA12.ConfNb=1 +SH.FMC_D13_DA13.0=FMC_D13 +SH.FMC_D13_DA13.ConfNb=1 +SH.FMC_D14_DA14.0=FMC_D14 +SH.FMC_D14_DA14.ConfNb=1 +SH.FMC_D15_DA15.0=FMC_D15 +SH.FMC_D15_DA15.ConfNb=1 +SH.FMC_D16.0=FMC_D16 +SH.FMC_D16.ConfNb=1 +SH.FMC_D17.0=FMC_D17 +SH.FMC_D17.ConfNb=1 +SH.FMC_D18.0=FMC_D18 +SH.FMC_D18.ConfNb=1 +SH.FMC_D19.0=FMC_D19 +SH.FMC_D19.ConfNb=1 +SH.FMC_D1_DA1.0=FMC_D1 +SH.FMC_D1_DA1.ConfNb=1 +SH.FMC_D20.0=FMC_D20 +SH.FMC_D20.ConfNb=1 +SH.FMC_D21.0=FMC_D21 +SH.FMC_D21.ConfNb=1 +SH.FMC_D22.0=FMC_D22 +SH.FMC_D22.ConfNb=1 +SH.FMC_D23.0=FMC_D23 +SH.FMC_D23.ConfNb=1 +SH.FMC_D24.0=FMC_D24 +SH.FMC_D24.ConfNb=1 +SH.FMC_D25.0=FMC_D25 +SH.FMC_D25.ConfNb=1 +SH.FMC_D26.0=FMC_D26 +SH.FMC_D26.ConfNb=1 +SH.FMC_D27.0=FMC_D27 +SH.FMC_D27.ConfNb=1 +SH.FMC_D28.0=FMC_D28 +SH.FMC_D28.ConfNb=1 +SH.FMC_D29.0=FMC_D29 +SH.FMC_D29.ConfNb=1 +SH.FMC_D2_DA2.0=FMC_D2 +SH.FMC_D2_DA2.ConfNb=1 +SH.FMC_D30.0=FMC_D30 +SH.FMC_D30.ConfNb=1 +SH.FMC_D31.0=FMC_D31 +SH.FMC_D31.ConfNb=1 +SH.FMC_D3_DA3.0=FMC_D3 +SH.FMC_D3_DA3.ConfNb=1 +SH.FMC_D4_DA4.0=FMC_D4 +SH.FMC_D4_DA4.ConfNb=1 +SH.FMC_D5_DA5.0=FMC_D5 +SH.FMC_D5_DA5.ConfNb=1 +SH.FMC_D6_DA6.0=FMC_D6 +SH.FMC_D6_DA6.ConfNb=1 +SH.FMC_D7_DA7.0=FMC_D7 +SH.FMC_D7_DA7.ConfNb=1 +SH.FMC_D8_DA8.0=FMC_D8 +SH.FMC_D8_DA8.ConfNb=1 +SH.FMC_D9_DA9.0=FMC_D9 +SH.FMC_D9_DA9.ConfNb=1 +SH.FMC_NBL0.0=FMC_NBL0 +SH.FMC_NBL0.ConfNb=1 +SH.FMC_NBL1.0=FMC_NBL1 +SH.FMC_NBL1.ConfNb=1 +SH.FMC_NBL2.0=FMC_NBL2 +SH.FMC_NBL2.ConfNb=1 +SH.FMC_NBL3.0=FMC_NBL3 +SH.FMC_NBL3.ConfNb=1 +SH.FMC_NOE.0=FMC_NOE +SH.FMC_NOE.ConfNb=1 +SH.FMC_NWAIT.0=FMC_NWAIT +SH.FMC_NWAIT.ConfNb=1 +SH.FMC_NWE.0=FMC_NWE +SH.FMC_NWE.ConfNb=1 +SH.FMC_SDCLK.0=FMC_SDCLK +SH.FMC_SDCLK.ConfNb=1 +SH.FMC_SDNCAS.0=FMC_SDNCAS +SH.FMC_SDNCAS.ConfNb=1 +SH.FMC_SDNRAS.0=FMC_SDNRAS +SH.FMC_SDNRAS.ConfNb=1 +SH.FMC_SDNWE.0=FMC_SDNWE +SH.FMC_SDNWE.ConfNb=1 +SH.GPXTI8.0=GPIO_EXTI8 +SH.GPXTI8.ConfNb=1 +SH.S_CKOUTDFSDM1.0=DFSDM1_CKOUT +SH.S_CKOUTDFSDM1.ConfNb=1 +SH.S_DATAIN1DFSDM1.0=DFSDM1_DATIN1 +SH.S_DATAIN1DFSDM1.ConfNb=1 +USB_OTG_FS.IPParameters=VirtualMode +USB_OTG_FS.VirtualMode=Device_Only +USB_OTG_HS.IPParameters=VirtualMode-Device_HS +USB_OTG_HS.VirtualMode-Device_HS=Device_HS +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +board=STM32H743I-EVAL2 +boardIOC=true diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/ozone/stm32h743.jdebug b/hw/bsp/stm32h7/boards/stm32h743eval/ozone/stm32h743.jdebug new file mode 100644 index 000000000..0ab078319 --- /dev/null +++ b/hw/bsp/stm32h7/boards/stm32h743eval/ozone/stm32h743.jdebug @@ -0,0 +1,245 @@ + +/********************************************************************* +* +* OnProjectLoad +* +* Function description +* Project load routine. Required. +* +********************************************************************** +*/ +void OnProjectLoad (void) { + Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M7F.svd"); + Project.AddSvdFile ("$(InstallDir)/Config/Peripherals/ARMv7M.svd"); + Project.AddSvdFile ("./STM32H743.svd"); + + Project.SetDevice ("STM32H743XI"); + Project.SetHostIF ("USB", ""); + Project.SetTargetIF ("SWD"); + Project.SetTIFSpeed ("50 MHz"); + + Project.SetTraceSource ("Trace Pins"); + Project.SetTracePortWidth (4); + // timing delay for trace pins in pico seconds, default is 2 nano seconds + Project.SetTraceTiming (100, 100, 100, 100); + + File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-stm32h743eval/cdc_msc.elf"); +} + +/********************************************************************* +*0 +* TargetReset +* +* Function description +* Replaces the default target device reset routine. Optional. +* +* Notes +* This example demonstrates the usage when +* debugging a RAM program on a Cortex-M target device +* +********************************************************************** +*/ +//void TargetReset (void) { +// +// unsigned int SP; +// unsigned int PC; +// unsigned int VectorTableAddr; +// +// Exec.Reset(); +// +// VectorTableAddr = Elf.GetBaseAddr(); +// +// if (VectorTableAddr != 0xFFFFFFFF) { +// +// Util.Log("Resetting Program."); +// +// SP = Target.ReadU32(VectorTableAddr); +// Target.SetReg("SP", SP); +// +// PC = Target.ReadU32(VectorTableAddr + 4); +// Target.SetReg("PC", PC); +// } +//} + +/********************************************************************* +* +* BeforeTargetReset +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void BeforeTargetReset (void) { +//} + +/********************************************************************* +* +* AfterTargetReset +* +* Function description +* Event handler routine. +* - Sets the PC register to program reset value. +* - Sets the SP register to program reset value on Cortex-M. +* +********************************************************************** +*/ +void AfterTargetReset (void) { + unsigned int SP; + unsigned int PC; + unsigned int VectorTableAddr; + + VectorTableAddr = Elf.GetBaseAddr(); + + if (VectorTableAddr == 0xFFFFFFFF) { + Util.Log("Project file error: failed to get program base"); + } else { + SP = Target.ReadU32(VectorTableAddr); + Target.SetReg("SP", SP); + + PC = Target.ReadU32(VectorTableAddr + 4); + Target.SetReg("PC", PC); + } +} + +/********************************************************************* +* +* DebugStart +* +* Function description +* Replaces the default debug session startup routine. Optional. +* +********************************************************************** +*/ +//void DebugStart (void) { +//} + +/********************************************************************* +* +* TargetConnect +* +* Function description +* Replaces the default target IF connection routine. Optional. +* +********************************************************************** +*/ +//void TargetConnect (void) { +//} + +/********************************************************************* +* +* BeforeTargetConnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ + +void BeforeTargetConnect (void) { + // + // Trace pin init is done by J-Link script file as J-Link script files are IDE independent + // + //Project.SetJLinkScript("./ST_STM32H743_Traceconfig.pex"); +} + +/********************************************************************* +* +* AfterTargetConnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void AfterTargetConnect (void) { +//} + +/********************************************************************* +* +* TargetDownload +* +* Function description +* Replaces the default program download routine. Optional. +* +********************************************************************** +*/ +//void TargetDownload (void) { +//} + +/********************************************************************* +* +* BeforeTargetDownload +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void BeforeTargetDownload (void) { +//} + +/********************************************************************* +* +* AfterTargetDownload +* +* Function description +* Event handler routine. +* - Sets the PC register to program reset value. +* - Sets the SP register to program reset value on Cortex-M. +* +********************************************************************** +*/ +void AfterTargetDownload (void) { + unsigned int SP; + unsigned int PC; + unsigned int VectorTableAddr; + + VectorTableAddr = Elf.GetBaseAddr(); + Util.Log("___"); + if (VectorTableAddr == 0xFFFFFFFF) { + Util.Log("Project file error: failed to get program base"); + } else { + SP = Target.ReadU32(VectorTableAddr); + Target.SetReg("SP", SP); + + PC = Target.ReadU32(VectorTableAddr + 4); + Target.SetReg("PC", PC); + } +} + +/********************************************************************* +* +* BeforeTargetDisconnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void BeforeTargetDisconnect (void) { +//} + +/********************************************************************* +* +* AfterTargetDisconnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void AfterTargetDisconnect (void) { +//} + +/********************************************************************* +* +* AfterTargetHalt +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void AfterTargetHalt (void) { +//} diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c index 35b2cd55b..eb4ac841e 100644 --- a/hw/bsp/stm32h7/family.c +++ b/hw/bsp/stm32h7/family.c @@ -56,6 +56,30 @@ void OTG_HS_IRQHandler(void) UART_HandleTypeDef UartHandle; +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +#ifdef TRACE_ETM +void trace_etm_init(void) { + // H7 trace pin is PE2 to PE6 + // __HAL_RCC_GPIOE_CLK_ENABLE(); + + GPIO_InitTypeDef gpio_init; + gpio_init.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6; + gpio_init.Mode = GPIO_MODE_AF_PP; + gpio_init.Pull = GPIO_PULLUP; + gpio_init.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + gpio_init.Alternate = GPIO_AF0_TRACE; + HAL_GPIO_Init(GPIOE, &gpio_init); + + // Enable trace clk, also in D1 and D3 domain + DBGMCU->CR |= DBGMCU_CR_DBG_TRACECKEN | DBGMCU_CR_DBG_CKD1EN | DBGMCU_CR_DBG_CKD3EN; +} +#else + #define trace_etm_init() +#endif + void board_init(void) { board_stm32h7_clock_init(); @@ -74,6 +98,8 @@ void board_init(void) #endif __HAL_RCC_GPIOJ_CLK_ENABLE(); + trace_etm_init(); + // Enable UART Clock UART_CLK_EN();