lpc55 correct bus_reset with highspeed on support controller
correct hsphy init for family
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@@ -164,43 +164,71 @@ void board_init(void)
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/* PORT0 PIN22 configured as USB0_VBUS */
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IOCON_PinMuxSet(IOCON, 0U, 22U, IOCON_PIO_DIG_FUNC7_EN);
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// USB Controller
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POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); /*Turn on USB0 Phy */
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POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /*< Turn on USB1 Phy */
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#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
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// Port0 is Full Speed
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/* Turn on USB0 Phy */
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POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY);
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/* reset the IP to make sure it's in reset state. */
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RESET_PeripheralReset(kUSB0D_RST_SHIFT_RSTn);
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RESET_PeripheralReset(kUSB0HSL_RST_SHIFT_RSTn);
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RESET_PeripheralReset(kUSB0HMR_RST_SHIFT_RSTn);
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// Enable USB Clock Adjustments to trim the FRO for the full speed controller
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ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK;
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CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false);
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CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
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/*According to reference mannual, device mode setting has to be set by access usb host register */
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CLOCK_EnableClock(kCLOCK_Usbhsl0); // enable usb0 host clock
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USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
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CLOCK_DisableClock(kCLOCK_Usbhsl0); // disable usb0 host clock
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/* enable USB Device clock */
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CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf));
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#endif
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#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE
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// Port1 is High Speed
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/* Turn on USB1 Phy */
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POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY);
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/* reset the IP to make sure it's in reset state. */
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RESET_PeripheralReset(kUSB1H_RST_SHIFT_RSTn);
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RESET_PeripheralReset(kUSB1D_RST_SHIFT_RSTn);
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RESET_PeripheralReset(kUSB1_RST_SHIFT_RSTn);
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RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn);
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#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE
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CLOCK_EnableClock(kCLOCK_Usbh1);
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/* Put PHY powerdown under software control */
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USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK;
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/* According to reference mannual, device mode setting has to be set by access usb host register */
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CLOCK_EnableClock(kCLOCK_Usbh1); // enable usb0 host clock
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USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK; // Put PHY powerdown under software control
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USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
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/* enable usb1 host clock */
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CLOCK_DisableClock(kCLOCK_Usbh1);
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#endif
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#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
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// Enable USB Clock Adjustments to trim the FRO for the full speed controller
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ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK;
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CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false);
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CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
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/* enable usb0 host clock */
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CLOCK_EnableClock(kCLOCK_Usbhsl0);
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/*According to reference mannual, device mode setting has to be set by access usb host register */
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USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
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/* disable usb0 host clock */
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CLOCK_DisableClock(kCLOCK_Usbhsl0);
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CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf)); /* enable USB Device clock */
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#endif
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CLOCK_DisableClock(kCLOCK_Usbh1); // disable usb0 host clock
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/* enable USB Device clock */
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CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_UsbPhySrcExt, XTAL0_CLK_HZ);
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CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUnused, 0U);
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//USB_EhciPhyInit(CONTROLLER_ID, BOARD_XTAL0_CLK_HZ, NULL);
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// Enable PHY support for Low speed device + LS via FS Hub
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USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
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// Enable all power for normal operation
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USBPHY->PWD = 0;
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USBPHY->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK;
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USBPHY->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK;
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// TX Timing
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// uint32_t phytx = USBPHY->TX;
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// phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
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// phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
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// USBPHY->TX = phytx;
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#endif
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}
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//--------------------------------------------------------------------+
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