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@@ -90,6 +90,7 @@ static inline uint32_t sie_command_read (uint8_t cmd_code, uint8_t data_len) ATT
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static inline uint32_t sie_command_read (uint8_t cmd_code, uint8_t data_len)
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{
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// TODO multiple read
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sie_commamd_code(SIE_CMDPHASE_COMMAND, cmd_code);
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sie_commamd_code(SIE_CMDPHASE_READ, cmd_code);
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return LPC_USB->USBCmdData;
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}
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@@ -97,6 +98,7 @@ static inline uint32_t sie_command_read (uint8_t cmd_code, uint8_t data_len)
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//--------------------------------------------------------------------+
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// IMPLEMENTATION
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//--------------------------------------------------------------------+
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void endpoint_control_isr(uint8_t coreid)
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{
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(void) coreid; // suppress compiler warning
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@@ -126,14 +128,14 @@ void endpoint_control_isr(uint8_t coreid)
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{
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//ASSERT(false, (void) 0); // not current supported
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}
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sie_command_write(SIE_CMDCODE_ENDPOINT_SELECT+0, 0, 0);
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sie_command_write(SIE_CMDCODE_BUFFER_CLEAR, 0, 0);
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}
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// control IN
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if (endpoint_int_status & BIT_(1))
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{
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(void) endpoint_int_status;
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}
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LPC_USB->USBEpIntClr = endpoint_int_status; // acknowledge interrupt
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@@ -141,13 +143,13 @@ void endpoint_control_isr(uint8_t coreid)
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void dcd_isr(uint8_t coreid)
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{
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uint32_t device_int_status = LPC_USB->USBDevIntSt & LPC_USB->USBDevIntEn & DEV_INT_ALL_MASK;
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uint32_t const device_int_status = LPC_USB->USBDevIntSt & LPC_USB->USBDevIntEn & DEV_INT_ALL_MASK;
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LPC_USB->USBDevIntClr = device_int_status;// Acknowledge handled interrupt
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//------------- usb bus event -------------//
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if (device_int_status & DEV_INT_DEVICE_STATUS_MASK)
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{
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uint32_t dev_status_reg = sie_command_read(SIE_CMDCODE_DEVICE_STATUS, 1);
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uint32_t const dev_status_reg = sie_command_read(SIE_CMDCODE_DEVICE_STATUS, 1);
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if (dev_status_reg & SIE_DEV_STATUS_RESET_MASK)
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{
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usbd_isr(coreid, TUSB_EVENT_BUS_RESET);
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@@ -173,7 +175,8 @@ void dcd_isr(uint8_t coreid)
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if (device_int_status & DEV_INT_ERROR_MASK)
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{
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ASSERT(false, (void) 0);
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uint32_t error_status = sie_command_read(SIE_CMDCODE_READ_ERROR_STATUS, 1);
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// ASSERT(false, (void) 0);
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}
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}
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@@ -213,8 +216,8 @@ tusb_error_t dcd_init(void)
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LPC_USB->USBDMAIntEn = (DMA_INT_END_OF_XFER_MASK | DMA_INT_NEW_DD_REQUEST_MASK | DMA_INT_ERROR_MASK );
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// clear all stall on control endpoint IN & OUT if any
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sie_command_write(SIE_CMDCODE_ENDPOINT_SET_STATUS , 0, 0);
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sie_command_write(SIE_CMDCODE_ENDPOINT_SET_STATUS + 1, 0, 0);
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sie_command_write(SIE_CMDCODE_ENDPOINT_SET_STATUS , 1, 0);
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sie_command_write(SIE_CMDCODE_ENDPOINT_SET_STATUS + 1, 1, 0);
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return TUSB_ERROR_NONE;
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}
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@@ -234,6 +237,30 @@ void dcd_device_set_address(uint8_t coreid, uint8_t dev_addr)
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sie_command_write(SIE_CMDCODE_SET_ADDRESS, 1, 0x80 | dev_addr); // 7th bit is : device_enable
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}
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tusb_error_t dcd_pipe_control_write(uint8_t coreid, void const * buffer, uint16_t length)
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{
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LPC_USB->USBCtrl = SLAVE_CONTROL_WRITE_ENABLE_MASK; // logical endpoint = 0
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LPC_USB->USBTxPLen = length;
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for (uint16_t count = 0; count < (length + 3) / 4; count++)
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{
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LPC_USB->USBTxData = *((uint32_t *)buffer); // NOTE: cortex M3 have no problem with alignment
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buffer += 4;
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}
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LPC_USB->USBCtrl = 0;
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sie_command_write(SIE_CMDCODE_ENDPOINT_SELECT+1, 0, 0); // select control IN endpoint
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sie_command_write(SIE_CMDCODE_BUFFER_VALIDATE, 0, 0);
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return TUSB_ERROR_NONE;
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}
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tusb_error_t dcd_pipe_control_read(uint8_t coreid)
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{
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return TUSB_ERROR_NONE;
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}
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void dcd_pipe_control_write_zero_length(uint8_t coreid)
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{
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LPC_USB->USBCtrl = SLAVE_CONTROL_WRITE_ENABLE_MASK; // logical endpoint = 0
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