support at32 mcu
This commit is contained in:
zhiqiang
@@ -550,6 +550,44 @@
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#define TUP_RHPORT_HIGHSPEED 1
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#define TUD_ENDPOINT_ONE_DIRECTION_ONLY
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//--------------------------------------------------------------------+
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// ArteryTek
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//--------------------------------------------------------------------+
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#elif TU_CHECK_MCU(OPT_MCU_AT32F403A_407)
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#define TUP_USBIP_FSDEV
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#define TUP_USBIP_FSDEV_AT32
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#define TUP_DCD_ENDPOINT_MAX 8
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#elif TU_CHECK_MCU(OPT_MCU_AT32F413)
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#define TUP_USBIP_FSDEV
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#define TUP_USBIP_FSDEV_AT32
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#define TUP_DCD_ENDPOINT_MAX 8
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#elif TU_CHECK_MCU(OPT_MCU_AT32F415)
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#define TUP_USBIP_DWC2
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#define TUP_USBIP_DWC2_AT32
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#define TUP_DCD_ENDPOINT_MAX 4
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#elif TU_CHECK_MCU(OPT_MCU_AT32F435_437)
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#define TUP_USBIP_DWC2
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#define TUP_USBIP_DWC2_AT32
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#define TUP_DCD_ENDPOINT_MAX 8
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#elif TU_CHECK_MCU(OPT_MCU_AT32F423)
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#define TUP_USBIP_DWC2
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#define TUP_USBIP_DWC2_AT32
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#define TUP_DCD_ENDPOINT_MAX 8
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#elif TU_CHECK_MCU(OPT_MCU_AT32F402_405)
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#define TUP_USBIP_DWC2
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#define TUP_USBIP_DWC2_AT32
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#define TUP_DCD_ENDPOINT_MAX 8
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#elif TU_CHECK_MCU(OPT_MCU_AT32F425)
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#define TUP_USBIP_DWC2
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#define TUP_USBIP_DWC2_AT32
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#define TUP_DCD_ENDPOINT_MAX 8
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#endif
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//--------------------------------------------------------------------+
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@@ -117,6 +117,8 @@
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#include "fsdev_stm32.h"
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#elif defined(TUP_USBIP_FSDEV_CH32)
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#include "fsdev_ch32.h"
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#elif defined(TUP_USBIP_FSDEV_AT32)
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#include "fsdev_at32.h"
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#else
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#error "Unknown USB IP"
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#endif
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224
src/portable/st/stm32_fsdev/fsdev_at32.h
Normal file
224
src/portable/st/stm32_fsdev/fsdev_at32.h
Normal file
@@ -0,0 +1,224 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2024, hathach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*/
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#ifndef TUSB_FSDEV_AT32_H
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#define TUSB_FSDEV_AT32_H
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#include "common/tusb_compiler.h"
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#if CFG_TUSB_MCU == OPT_MCU_AT32F403A_407
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#include "at32f403a_407.h"
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#elif CFG_TUSB_MCU == OPT_MCU_AT32F413
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#include "at32f413.h"
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#endif
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//#include "fsdev_common.h"
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//--------------------------------------------------------------------+
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//
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//--------------------------------------------------------------------+
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#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413)
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static const IRQn_Type fsdev_irq[] = {
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USBFS_H_CAN1_TX_IRQn,
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USBFS_L_CAN1_RX0_IRQn,
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USBFSWakeUp_IRQn
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};
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enum { FSDEV_IRQ_NUM = TU_ARRAY_SIZE(fsdev_irq) };
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#else
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#error "Unsupported MCU"
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#endif
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void dcd_int_enable(uint8_t rhport) {
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(void)rhport;
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#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413)
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// AT32F403A/407 devices allow to remap the USB interrupt vectors from
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// shared USB/CAN IRQs to separate CAN and USB IRQs.
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// This dynamically checks if this remap is active to enable the right IRQs.
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if (CRM->intmap_bit.usbintmap) {
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NVIC_DisableIRQ(USBFS_MAPH_IRQn);
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NVIC_DisableIRQ(USBFS_MAPL_IRQn);
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NVIC_DisableIRQ(USBFSWakeUp_IRQn);
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} else
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#endif
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{
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for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) {
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NVIC_EnableIRQ(fsdev_irq[i]);
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}
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}
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}
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void dcd_int_disable(uint8_t rhport) {
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(void)rhport;
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#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413)
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// AT32F403A/407 devices allow to remap the USB interrupt vectors from
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// shared USB/CAN IRQs to separate CAN and USB IRQs.
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// This dynamically checks if this remap is active to enable the right IRQs.
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if (CRM->intmap_bit.usbintmap) {
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NVIC_DisableIRQ(USBFS_MAPH_IRQn);
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NVIC_DisableIRQ(USBFS_MAPL_IRQn);
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NVIC_DisableIRQ(USBFSWakeUp_IRQn);
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} else
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#endif
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{
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for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) {
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NVIC_DisableIRQ(fsdev_irq[i]);
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}
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}
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}
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void dcd_disconnect(uint8_t rhport) {
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(void) rhport;
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/* disable usb phy */
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//USB->ctrl_bit.disusb = TRUE;
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*(int *)(0x40000000+0x5C00+0x40) |= (1<<1);
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*(int *)(0x40000000+0x5C00+0x60) |= (1<<1);
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/* D+ 1.5k pull-up disable */
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//USB->cfg_bit.puo = TRUE;
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}
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void dcd_connect(uint8_t rhport) {
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(void) rhport;
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/* enable usb phy */
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//USB->ctrl_bit.disusb = 0;
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*(int *)(0x40000000+0x5C00+0x40) &= ~(1<<1);
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*(int *)(0x40000000+0x5C00+0x60) &= ~(1<<1);
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/* Dp 1.5k pull-up enable */
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//USB->cfg_bit.puo = 0;
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}
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#define FSDEV_PMA_SIZE (512u)
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#define FSDEV_REG_BASE (APB1PERIPH_BASE + 0x00005C00UL)
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#define FSDEV_PMA_BASE (APB1PERIPH_BASE + 0x00006000UL)
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/**************************** ISTR interrupt events *************************/
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#define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
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#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
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#define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
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#define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
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#define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
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#define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
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#define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
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#define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
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#define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
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#define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
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/* Legacy defines */
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#define USB_ISTR_PMAOVRM USB_ISTR_PMAOVR
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#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
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#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
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#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
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#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
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#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
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#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
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#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
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#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
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/* Legacy defines */
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#define USB_CLR_PMAOVRM USB_CLR_PMAOVR
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/************************* CNTR control register bits definitions ***********/
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#define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
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#define USB_CNTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
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#define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
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#define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
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#define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
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#define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
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#define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
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#define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
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#define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
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#define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
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#define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
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#define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
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#define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
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/* Legacy defines */
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#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVR
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#define USB_CNTR_LP_MODE USB_CNTR_LPMODE
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/******************** FNR Frame Number Register bit definitions ************/
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#define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
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#define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
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#define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
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#define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
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#define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
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/******************** DADDR Device ADDRess bit definitions ****************/
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#define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */
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#define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */
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/****************************** Endpoint register *************************/
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#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
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#define USB_EP1R (USB_BASE + 0x04U) /*!< endpoint 1 register address */
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#define USB_EP2R (USB_BASE + 0x08U) /*!< endpoint 2 register address */
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#define USB_EP3R (USB_BASE + 0x0CU) /*!< endpoint 3 register address */
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#define USB_EP4R (USB_BASE + 0x10U) /*!< endpoint 4 register address */
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#define USB_EP5R (USB_BASE + 0x14U) /*!< endpoint 5 register address */
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#define USB_EP6R (USB_BASE + 0x18U) /*!< endpoint 6 register address */
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#define USB_EP7R (USB_BASE + 0x1CU) /*!< endpoint 7 register address */
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/* bit positions */
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#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
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#define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
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#define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
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#define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
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#define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
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#define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
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#define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
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#define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
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#define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
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#define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
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/* EndPoint REGister MASK (no toggle fields) */
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#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
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/*!< EP_TYPE[1:0] EndPoint TYPE */
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#define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
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#define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
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#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
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#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
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#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
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#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
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#define USB_EPKIND_MASK ((uint16_t) ~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
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/*!< STAT_TX[1:0] STATus for TX transfer */
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#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
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#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
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#define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
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#define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
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#define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
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#define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
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#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
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/*!< STAT_RX[1:0] STATus for RX transfer */
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#define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
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#define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
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#define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
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#define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
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#define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
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#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
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#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
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#endif
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135
src/portable/synopsys/dwc2/dwc2_at32.h
Normal file
135
src/portable/synopsys/dwc2/dwc2_at32.h
Normal file
@@ -0,0 +1,135 @@
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/*
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* The MIT License (MIT)
|
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*
|
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* Copyright (c) 2021, Ha Thach (tinyusb.org)
|
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*
|
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* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
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#ifndef DWC2_AT32_H_
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#define DWC2_AT32_H_
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#define DWC2_EP_MAX TUP_DCD_ENDPOINT_MAX
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#if CFG_TUSB_MCU == OPT_MCU_AT32F415
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#include <at32f415.h>
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#define OTG1_FIFO_SIZE 1280
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#define OTG1_IRQn OTGFS1_IRQn
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#define DWC2_OTG1_REG_BASE 0x50000000UL
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#elif CFG_TUSB_MCU == OPT_MCU_AT32F435_437
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#include <at32f435_437.h>
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#define OTG1_FIFO_SIZE 1280
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#define OTG2_FIFO_SIZE 1280
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#define OTG1_IRQn OTGFS1_IRQn
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#define OTG2_IRQn OTGFS2_IRQn
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#define DWC2_OTG1_REG_BASE 0x50000000UL
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#define DWC2_OTG2_REG_BASE 0x40040000UL
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#elif CFG_TUSB_MCU == OPT_MCU_AT32F423
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#include <at32f423.h>
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#define OTG1_FIFO_SIZE 1280
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#define OTG1_IRQn OTGFS1_IRQn
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#define DWC2_OTG1_REG_BASE 0x50000000UL
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#elif CFG_TUSB_MCU == OPT_MCU_AT32F402_405
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#include <at32f402_405.h>
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#define OTG1_FIFO_SIZE 1280
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#define OTG2_FIFO_SIZE 4096
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#define OTG1_IRQn OTGFS1_IRQn
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#define OTG2_IRQn OTGHS_IRQn
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#define DWC2_OTG1_REG_BASE 0x50000000UL
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#define DWC2_OTG2_REG_BASE 0x40040000UL //OTGHS
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#elif CFG_TUSB_MCU == OPT_MCU_AT32F425
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#include <at32f425.h>
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#define OTG1_FIFO_SIZE 1280
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#define OTG1_IRQn OTGFS1_IRQn
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#define DWC2_OTG1_REG_BASE 0x50000000UL
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#endif
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#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
static const dwc2_controller_t _dwc2_controller[] =
|
||||
{
|
||||
{ .reg_base = DWC2_OTG1_REG_BASE, .irqnum = OTG1_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG1_FIFO_SIZE },
|
||||
#if defined DWC2_OTG2_REG_BASE
|
||||
{ .reg_base = DWC2_OTG2_REG_BASE, .irqnum = OTG2_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG2_FIFO_SIZE }
|
||||
#endif
|
||||
};
|
||||
|
||||
TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) {
|
||||
(void) role;
|
||||
const IRQn_Type irqn = (IRQn_Type) _dwc2_controller[rhport].irqnum;
|
||||
if (enabled) {
|
||||
NVIC_EnableIRQ(irqn);
|
||||
} else {
|
||||
NVIC_DisableIRQ(irqn);
|
||||
}
|
||||
}
|
||||
|
||||
TU_ATTR_ALWAYS_INLINE
|
||||
static inline void dwc2_dcd_int_enable(uint8_t rhport)
|
||||
{
|
||||
NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum);
|
||||
}
|
||||
|
||||
TU_ATTR_ALWAYS_INLINE
|
||||
static inline void dwc2_dcd_int_disable (uint8_t rhport)
|
||||
{
|
||||
NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum);
|
||||
}
|
||||
|
||||
static inline void dwc2_remote_wakeup_delay(void)
|
||||
{
|
||||
// try to delay for 1 ms
|
||||
uint32_t count = system_core_clock / 1000;
|
||||
while ( count-- ) __asm volatile ("nop");
|
||||
}
|
||||
|
||||
// MCU specific PHY init, called BEFORE core reset
|
||||
static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
|
||||
{
|
||||
(void) dwc2;
|
||||
// Enable on-chip HS PHY
|
||||
if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI)
|
||||
{
|
||||
|
||||
}
|
||||
else if(hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED)
|
||||
{
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
// MCU specific PHY update, it is called AFTER init() and core reset
|
||||
static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
|
||||
{
|
||||
(void) dwc2;
|
||||
(void) hs_phy_type;
|
||||
|
||||
dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN | STM32_GCCFG_DCDEN | STM32_GCCFG_PDEN;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DWC2_GD32_H_ */
|
||||
@@ -121,6 +121,12 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
|
||||
// Set 16-bit interface if supported
|
||||
if (ghwcfg4.phy_data_width) {
|
||||
gusbcfg |= GUSBCFG_PHYIF16; // 16 bit
|
||||
|
||||
/* at32f402_405 does not actually support 16-bit */
|
||||
#if CFG_TUSB_MCU == OPT_MCU_AT32F402_405
|
||||
gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit
|
||||
#endif
|
||||
|
||||
} else {
|
||||
gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit
|
||||
}
|
||||
@@ -139,7 +145,13 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
|
||||
// - 9 if using 8-bit PHY interface
|
||||
// - 5 if using 16-bit PHY interface
|
||||
gusbcfg &= ~GUSBCFG_TRDT_Msk;
|
||||
gusbcfg |= (ghwcfg4.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
|
||||
gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
|
||||
|
||||
/* at32f402_405 does not actually support 16-bit */
|
||||
#if CFG_TUSB_MCU == OPT_MCU_AT32F402_405
|
||||
gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 9u : 9u) << GUSBCFG_TRDT_Pos;
|
||||
#endif
|
||||
|
||||
dwc2->gusbcfg = gusbcfg;
|
||||
|
||||
// MCU specific PHY update post reset
|
||||
|
||||
@@ -49,6 +49,8 @@
|
||||
#include "dwc2_efm32.h"
|
||||
#elif TU_CHECK_MCU(OPT_MCU_XMC4000)
|
||||
#include "dwc2_xmc.h"
|
||||
#elif defined(TUP_USBIP_DWC2_AT32)
|
||||
#include "dwc2_at32.h"
|
||||
#else
|
||||
#error "Unsupported MCUs"
|
||||
#endif
|
||||
|
||||
@@ -201,6 +201,15 @@
|
||||
#define OPT_MCU_MAX32650 2402 ///< ADI MAX32650/1/2
|
||||
#define OPT_MCU_MAX78002 2403 ///< ADI MAX78002
|
||||
|
||||
// ArteryTek
|
||||
#define OPT_MCU_AT32F403A_407 2500 ///< ArteryTek AT32F403A_AT32F407
|
||||
#define OPT_MCU_AT32F415 2501 ///< ArteryTek AT32F415
|
||||
#define OPT_MCU_AT32F435_437 2502 ///< ArteryTek AT32F435_AT32F437
|
||||
#define OPT_MCU_AT32F423 2503 ///< ArteryTek AT32F423
|
||||
#define OPT_MCU_AT32F402_405 2504 ///< ArteryTek AT32F402_405
|
||||
#define OPT_MCU_AT32F425 2505 ///< ArteryTek AT32F425
|
||||
#define OPT_MCU_AT32F413 2506 ///< ArteryTek AT32F413
|
||||
|
||||
// Check if configured MCU is one of listed
|
||||
// Apply _TU_CHECK_MCU with || as separator to list of input
|
||||
#define _TU_CHECK_MCU(_m) (CFG_TUSB_MCU == _m)
|
||||
|
||||
Reference in New Issue
Block a user