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ground works for hcd max3421e

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This commit is contained in:
hathach
2023-08-18 14:06:57 +07:00
parent 9257a0f562
commit 824e585e2b
6 changed files with 369 additions and 31 deletions
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4
hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
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@@ -1,6 +1,6 @@
set(MCU_VARIANT nrf52840)
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
# set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
#set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
function(update_board TARGET)
endfunction()

7
hw/bsp/nrf/boards/feather_nrf52840_express/board.h
View File

@@ -45,6 +45,13 @@
#define UART_RX_PIN 24
#define UART_TX_PIN 25
// SPI for USB host shield
#define SPI_SCK_PIN 14
#define SPI_MOSI_PIN 13
#define SPI_MISO_PIN 15
#define SPI_CS_PIN 27
#define MAX3241E_INT_PIN 26
#ifdef __cplusplus
}
#endif

80
hw/bsp/nrf/family.c
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@@ -40,6 +40,7 @@
#include "hal/nrf_gpio.h"
#include "drivers/include/nrfx_power.h"
#include "drivers/include/nrfx_uarte.h"
#include "drivers/include/nrfx_spim.h"
#ifdef SOFTDEVICE_PRESENT
#include "nrf_sdm.h"
@@ -54,8 +55,7 @@
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
//--------------------------------------------------------------------+
void USBD_IRQHandler(void)
{
void USBD_IRQHandler(void) {
tud_int_handler(0);
}
@@ -81,6 +81,7 @@ enum {
#endif
static nrfx_uarte_t _uart_id = NRFX_UARTE_INSTANCE(0);
static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(0);
// tinyusb function that handles power event (detected, ready, removed)
// We must call it within SD's SOC event handler, or set it as power event handler if SD is not enabled.
@@ -88,13 +89,11 @@ extern void tusb_hal_nrf_power_event(uint32_t event);
// nrf power callback, could be unused if SD is enabled or usb is disabled (board_test example)
TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event)
{
TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
tusb_hal_nrf_power_event((uint32_t) event);
}
void board_init(void)
{
void board_init(void) {
// stop LF clock just in case we jump from application without reset
NRF_CLOCK->TASKS_LFCLKSTOP = 1UL;
@@ -113,8 +112,7 @@ void board_init(void)
SysTick_Config(SystemCoreClock/1000);
// UART
nrfx_uarte_config_t uart_cfg =
{
nrfx_uarte_config_t uart_cfg = {
.pseltxd = UART_TX_PIN,
.pselrxd = UART_RX_PIN,
.pselcts = NRF_UARTE_PSEL_DISCONNECTED,
@@ -175,45 +173,78 @@ void board_init(void)
if ( usb_reg & VBUSDETECT_Msk ) tusb_hal_nrf_power_event(USB_EVT_DETECTED);
if ( usb_reg & OUTPUTRDY_Msk ) tusb_hal_nrf_power_event(USB_EVT_READY);
#endif
(void) _spi;
#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
// USB host using max3421e usb controller via SPI
nrfx_spim_config_t cfg = {
.sck_pin = SPI_SCK_PIN,
.mosi_pin = SPI_MOSI_PIN,
.miso_pin = SPI_MISO_PIN,
.ss_pin = SPI_CS_PIN,
.ss_active_high = false,
.irq_priority = 3,
.orc = 0xFF,
// default setting 4 Mhz, Mode 0, MSB first
.frequency = NRF_SPIM_FREQ_4M,
.mode = NRF_SPIM_MODE_0,
.bit_order = NRF_SPIM_BIT_ORDER_MSB_FIRST,
};
// no handler --> blocking
nrfx_spim_init(&_spi, &cfg, NULL, NULL);
#endif
}
//--------------------------------------------------------------------+
// Board porting API
//--------------------------------------------------------------------+
void board_led_write(bool state)
{
nrf_gpio_pin_write(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
void board_led_write(bool state) {
nrf_gpio_pin_write(LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
}
uint32_t board_button_read(void)
{
uint32_t board_button_read(void) {
return BUTTON_STATE_ACTIVE == nrf_gpio_pin_read(BUTTON_PIN);
}
int board_uart_read(uint8_t* buf, int len)
{
(void) buf; (void) len;
int board_uart_read(uint8_t *buf, int len) {
(void) buf;
(void) len;
return 0;
// return NRFX_SUCCESS == nrfx_uart_rx(&_uart_id, buf, (size_t) len) ? len : 0;
}
int board_uart_write(void const * buf, int len)
{
return (NRFX_SUCCESS == nrfx_uarte_tx(&_uart_id, (uint8_t const*) buf, (size_t) len)) ? len : 0;
int board_uart_write(void const *buf, int len) {
return (NRFX_SUCCESS == nrfx_uarte_tx(&_uart_id, (uint8_t const *) buf, (size_t) len)) ? len : 0;
}
#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
void SysTick_Handler (void)
{
void SysTick_Handler(void) {
system_ticks++;
}
uint32_t board_millis(void)
{
uint32_t board_millis(void) {
return system_ticks;
}
#endif
#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
// API: SPI transfer with MAX3421E, must be implemented by application
bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len) {
(void) rhport;
nrfx_spim_xfer_desc_t xfer = {
.p_tx_buffer = tx_buf,
.tx_length = tx_len,
.p_rx_buffer = rx_buf,
.rx_length = rx_len,
};
return nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS;
}
#endif
#ifdef SOFTDEVICE_PRESENT
@@ -251,8 +282,7 @@ void SD_EVT_IRQHandler(void)
}
}
void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info)
{
void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info) {
(void) id;
(void) pc;
(void) info;

2
hw/bsp/nrf/family.cmake
View File

@@ -122,7 +122,7 @@ function(family_configure_example TARGET RTOS)
family_add_tinyusb(${TARGET} OPT_MCU_NRF5X ${RTOS})
target_sources(${TARGET}-tinyusb PUBLIC
${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c
#${TOP}/src/portable/analog/max3421e/hcd_max3421e.c
${TOP}/src/portable/analog/max3421e/hcd_max3421e.c
)
target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})

5
hw/bsp/nrf/nrfx_config.h
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@@ -9,9 +9,8 @@
#define NRFX_UARTE_ENABLED 1
#define NRFX_UARTE0_ENABLED 1
#define NRFX_UARTE1_ENABLED 0
#define NRFX_UARTE2_ENABLED 0
#define NRFX_UARTE3_ENABLED 0
#define NRFX_SPIM_ENABLED 1
#define NRFX_SPIM0_ENABLED 1
#define NRFX_PRS_ENABLED 0
#define NRFX_USBREG_ENABLED 1

302
src/portable/analog/max3421e/hcd_max3421e.c Normal file
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@@ -0,0 +1,302 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2023 Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#include "tusb_option.h"
#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
#include "host/hcd.h"
//--------------------------------------------------------------------+
//
//--------------------------------------------------------------------+
// Command format is
// Reg [7:3] | 0 [2] | Dir [1] | Ack [0]
enum {
CMDBYTE_WRITE = 0x02,
};
enum {
RCVVFIFO_ADDR = 1u << 3, // 0x08
SNDFIFO_ADDR = 2u << 3, // 0x10
SUDFIFO_ADDR = 4u << 3, // 0x20
RCVBC_ADDR = 6u << 3, // 0x30
SNDBC_ADDR = 7u << 3, // 0x38
USBIRQ_ADDR = 13u << 3, // 0x68
USBIEN_ADDR = 14u << 3, // 0x70
USBCTL_ADDR = 15u << 3, // 0x78
CPUCTL_ADDR = 16u << 3, // 0x80
PINCTL_ADDR = 17u << 3, // 0x88
REVISION_ADDR = 18u << 3, // 0x90
HIRQ_ADDR = 25u << 3, // 0xC8
HIEN_ADDR = 26u << 3, // 0xD0
MODE_ADDR = 27u << 3, // 0xD8
PERADDR_ADDR = 28u << 3, // 0xE0
HCTL_ADDR = 29u << 3, // 0xE8
HXFR_ADDR = 30u << 3, // 0xF0
HRSL_ADDR = 31u << 3, // 0xF8
};
enum {
USBIRQ_OSCOK_IRQ = 1u << 0,
USBIRQ_NOVBUS_IRQ = 1u << 5,
USBIRQ_VBUS_IRQ = 1u << 6,
};
enum {
USBCTL_PWRDOWN = 1u << 4,
USBCTL_CHIPRES = 1u << 5,
};
enum {
CPUCTL_IE = 1u << 0,
CPUCTL_PULSEWID0 = 1u << 6,
CPUCTL_PULSEWID1 = 1u << 7,
};
enum {
PINCTL_GPXA = 1u << 0,
PINCTL_GPXB = 1u << 1,
PINCTL_POSINT = 1u << 2,
PINCTL_INTLEVEL = 1u << 3,
PINCTL_FDUPSPI = 1u << 4,
};
enum {
HIRQ_BUSEVENT_IRQ = 1u << 0,
HIRQ_RWU_IRQ = 1u << 1,
HIRQ_RCVDAV_IRQ = 1u << 2,
HIRQ_SNDBAV_IRQ = 1u << 3,
HIRQ_SUSDN_IRQ = 1u << 4,
HIRQ_CONDET_IRQ = 1u << 5,
HIRQ_FRAME_IRQ = 1u << 6,
HIRQ_HXFRDN_IRQ = 1u << 7,
};
enum {
MODE_HOST = 1u << 0,
MODE_LOWSPEED = 1u << 1,
MODE_HUBPRE = 1u << 2,
MODE_SOFKAENAB = 1u << 3,
MODE_SEPIRQ = 1u << 4,
MODE_DELAYISO = 1u << 5,
MODE_DMPULLDN = 1u << 6,
MODE_DPPULLDN = 1u << 7,
};
enum {
HCTL_BUSRST = 1u << 1,
HCTL_FRMRST = 1u << 2,
HCTL_SAMPLEBUS = 1u << 3,
HCTL_SIGRSM = 1u << 4,
HCTL_RCVTOG0 = 1u << 5,
HCTL_RCVTOG1 = 1u << 6,
HCTL_SNDTOG0 = 1u << 7,
HCTL_SNDTOG1 = 1u << 8,
};
enum {
HXFR_EPNUM_MASK = 0x0f,
HXFR_SETUP = 1u << 4,
HXFR_OUT_NIN = 1u << 5,
HXFR_ISO = 1u << 6,
HXFR_HS = 1u << 7,
};
enum {
HRSL_RESULT_MASK = 0x0f,
HRSL_RCVTOGRD = 1u << 4,
HRSL_SNDTOGRD = 1u << 5,
HRSL_KSTATUS = 1u << 6,
HRSL_JSTATUS = 1u << 7,
};
// API: SPI transfer with MAX3421E, must be implemented by application
bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len);
// return HIRQ register since we are in full-duplex mode
static uint8_t reg_write(uint8_t reg, uint8_t data) {
uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data};
uint8_t rx_buf[2] = {0, 0};
tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2);
return rx_buf[0];
}
static uint8_t reg_read(uint8_t reg) {
uint8_t tx_buf[2] = {reg, 0};
uint8_t rx_buf[2] = {0, 0};
return tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2) ? rx_buf[1] : 0;
}
//--------------------------------------------------------------------+
// Controller API
//--------------------------------------------------------------------+
// optional hcd configuration, called by tuh_configure()
bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
(void) rhport;
(void) cfg_id;
(void) cfg_param;
return false;
}
// Initialize controller to host mode
bool hcd_init(uint8_t rhport) {
(void) rhport;
// full duplex, interrupt level (should be configurable)
reg_write(PINCTL_ADDR, PINCTL_FDUPSPI | PINCTL_INTLEVEL);
// reset
reg_write(USBCTL_ADDR, USBCTL_CHIPRES);
reg_write(USBCTL_ADDR, 0);
while( !(reg_read(USBIRQ_ADDR) & USBIRQ_OSCOK_IRQ) ) {
// wait for oscillator to stabilize
}
// Mode: Host and DP/DM pull down
reg_write(MODE_ADDR, MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST);
// Connection detection
reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ /*| HIRQ_FRAME_IRQ */);
return false;
}
// Interrupt Handler
void hcd_int_handler(uint8_t rhport) {
(void) rhport;
}
// Enable USB interrupt
void hcd_int_enable (uint8_t rhport) {
(void) rhport;
}
// Disable USB interrupt
void hcd_int_disable(uint8_t rhport) {
(void) rhport;
}
// Get frame number (1ms)
uint32_t hcd_frame_number(uint8_t rhport) {
(void) rhport;
return 0;
}
//--------------------------------------------------------------------+
// Port API
//--------------------------------------------------------------------+
// Get the current connect status of roothub port
bool hcd_port_connect_status(uint8_t rhport) {
(void) rhport;
return false;
}
// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
void hcd_port_reset(uint8_t rhport) {
(void) rhport;
}
// Complete bus reset sequence, may be required by some controllers
void hcd_port_reset_end(uint8_t rhport) {
(void) rhport;
}
// Get port link speed
tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
(void) rhport;
return TUSB_SPEED_FULL;
}
// HCD closes all opened endpoints belong to this device
void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
(void) rhport;
(void) dev_addr;
}
//--------------------------------------------------------------------+
// Endpoints API
//--------------------------------------------------------------------+
// Open an endpoint
bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) {
(void) rhport;
(void) dev_addr;
(void) ep_desc;
return false;
}
// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
(void) rhport;
(void) dev_addr;
(void) ep_addr;
(void) buffer;
(void) buflen;
return false;
}
// Abort a queued transfer. Note: it can only abort transfer that has not been started
// Return true if a queued transfer is aborted, false if there is no transfer to abort
bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
(void) rhport;
(void) dev_addr;
(void) ep_addr;
return false;
}
// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) {
(void) rhport;
(void) dev_addr;
(void) setup_packet;
return false;
}
// clear stall, data toggle is also reset to DATA0
bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
(void) rhport;
(void) dev_addr;
(void) ep_addr;
return false;
}
#endif