splitted cdch_internal_control_complete() into driver's _internal_control_complete() and moved them into driver's sections. no functional change
This commit is contained in:
@@ -286,7 +286,6 @@ static cdch_interface_t* make_new_itf(uint8_t daddr, tusb_desc_interface_t const
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static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t const *desc_ep);
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static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t const *desc_ep);
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static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num);
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static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num);
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static void cdch_internal_control_complete(tuh_xfer_t* xfer);
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// APPLICATION API
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// APPLICATION API
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@@ -422,127 +421,6 @@ bool tuh_cdc_read_clear (uint8_t idx) {
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// Control Endpoint API
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// Control Endpoint API
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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static void process_internal_control_complete(tuh_xfer_t* xfer, uint8_t itf_num) {
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uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
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cdch_interface_t* p_cdc = get_itf(idx);
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TU_ASSERT(p_cdc, );
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uint16_t const value = tu_le16toh(xfer->setup->wValue);
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bool const success = (xfer->result == XFER_RESULT_SUCCESS);
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TU_LOG_P_CDC("control complete success = %u", success);
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if (success) {
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switch (p_cdc->serial_drid) {
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case SERIAL_DRIVER_ACM:
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switch (xfer->setup->bRequest) {
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case CDC_REQUEST_SET_CONTROL_LINE_STATE:
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p_cdc->line_state = (uint8_t) value;
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break;
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case CDC_REQUEST_SET_LINE_CODING: {
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uint16_t const len = tu_min16(sizeof(cdc_line_coding_t), tu_le16toh(xfer->setup->wLength));
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memcpy(&p_cdc->line_coding, xfer->buffer, len);
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break;
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}
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default: break;
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}
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break;
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#if CFG_TUH_CDC_FTDI
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case SERIAL_DRIVER_FTDI:
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switch (xfer->setup->bRequest) {
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case FTDI_SIO_MODEM_CTRL:
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p_cdc->line_state = (uint8_t) value;
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break;
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case FTDI_SIO_SET_BAUD_RATE:
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p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate;
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break;
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default: break;
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}
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break;
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#endif
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#if CFG_TUH_CDC_CP210X
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case SERIAL_DRIVER_CP210X:
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switch(xfer->setup->bRequest) {
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case CP210X_SET_MHS:
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p_cdc->line_state = (uint8_t) value;
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break;
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case CP210X_SET_BAUDRATE: {
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uint32_t baudrate;
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memcpy(&baudrate, xfer->buffer, sizeof(uint32_t));
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p_cdc->line_coding.bit_rate = tu_le32toh(baudrate);
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break;
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}
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default: break;
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}
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break;
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#endif
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#if CFG_TUH_CDC_CH34X
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case SERIAL_DRIVER_CH34X:
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switch (xfer->setup->bRequest) {
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case CH34X_REQ_WRITE_REG:
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// register write request
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switch (value) {
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case CH34X_REG16_DIVISOR_PRESCALER:
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// baudrate
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p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate;
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break;
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case CH32X_REG16_LCR2_LCR:
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// data format
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p_cdc->line_coding.stop_bits = p_cdc->requested_line_coding.stop_bits;
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p_cdc->line_coding.parity = p_cdc->requested_line_coding.parity;
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p_cdc->line_coding.data_bits = p_cdc->requested_line_coding.data_bits;
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break;
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default: break;
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}
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break;
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case CH34X_REQ_MODEM_CTRL: {
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// set modem controls RTS/DTR request. Note: signals are inverted
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uint16_t const modem_signal = ~value;
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if (modem_signal & CH34X_BIT_RTS) {
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p_cdc->line_state |= CDC_CONTROL_LINE_STATE_RTS;
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} else {
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p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_RTS;
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}
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if (modem_signal & CH34X_BIT_DTR) {
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p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR;
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} else {
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p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_DTR;
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}
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break;
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}
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default: break;
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}
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break;
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#endif
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default: break;
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}
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}
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xfer->complete_cb = p_cdc->user_control_cb;
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if (xfer->complete_cb) {
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xfer->complete_cb(xfer);
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}
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}
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// internal control complete to update state such as line state, encoding
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static void cdch_internal_control_complete(tuh_xfer_t* xfer) {
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uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
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process_internal_control_complete(xfer, itf_num);
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}
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bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
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bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
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cdch_interface_t* p_cdc = get_itf(idx);
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cdch_interface_t* p_cdc = get_itf(idx);
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TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
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TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
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@@ -820,6 +698,36 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num) {
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//------------- Driver API -------------//
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//------------- Driver API -------------//
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// internal control complete to update state such as line state, encoding
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static void acm_internal_control_complete(tuh_xfer_t * xfer) {
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uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
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uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
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cdch_interface_t * p_cdc = get_itf(idx);
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TU_ASSERT(p_cdc,);
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bool const success = (xfer->result == XFER_RESULT_SUCCESS);
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TU_LOG_P_CDC("control complete success = %u", success);
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if (success) {
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switch (xfer->setup->bRequest) {
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case CDC_REQUEST_SET_CONTROL_LINE_STATE:
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p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue);
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break;
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case CDC_REQUEST_SET_LINE_CODING:
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uint16_t const len = tu_min16(sizeof(cdc_line_coding_t), tu_le16toh(xfer->setup->wLength));
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memcpy(&p_cdc->line_coding, xfer->buffer, len);
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break;
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default: break;
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}
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}
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xfer->complete_cb = p_cdc->user_control_cb;
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if (xfer->complete_cb) {
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xfer->complete_cb(xfer);
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}
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}
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static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
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static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
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TU_VERIFY(p_cdc->acm_capability.support_line_request);
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TU_VERIFY(p_cdc->acm_capability.support_line_request);
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@@ -842,7 +750,7 @@ static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_st
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.ep_addr = 0,
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.ep_addr = 0,
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.setup = &request,
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.setup = &request,
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.buffer = NULL,
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.buffer = NULL,
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.complete_cb = complete_cb ? cdch_internal_control_complete : NULL, // complete_cb is NULL for sync call
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.complete_cb = complete_cb ? acm_internal_control_complete : NULL, // complete_cb is NULL for sync call
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.user_data = user_data
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.user_data = user_data
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};
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};
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@@ -873,7 +781,7 @@ static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const
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.ep_addr = 0,
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.ep_addr = 0,
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.setup = &request,
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.setup = &request,
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.buffer = enum_buf,
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.buffer = enum_buf,
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.complete_cb = complete_cb ? cdch_internal_control_complete : NULL, // complete_cb is NULL for sync call
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.complete_cb = complete_cb ? acm_internal_control_complete : NULL, // complete_cb is NULL for sync call
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.user_data = user_data
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.user_data = user_data
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};
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};
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@@ -1030,13 +938,42 @@ static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, u
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//------------- Driver API -------------//
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//------------- Driver API -------------//
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// internal control complete to update state such as line state, line_coding
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static void ftdi_internal_control_complete(tuh_xfer_t * xfer) {
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uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
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uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
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cdch_interface_t * p_cdc = get_itf(idx);
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TU_ASSERT(p_cdc,);
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bool const success = (xfer->result == XFER_RESULT_SUCCESS);
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TU_LOG_P_CDC("control complete success = %u", success);
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if (success) {
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switch (xfer->setup->bRequest) {
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case FTDI_SIO_MODEM_CTRL:
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p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue);
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break;
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case FTDI_SIO_SET_BAUD_RATE:
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p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate;
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break;
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default: break;
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}
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}
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xfer->complete_cb = p_cdc->user_control_cb;
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if (xfer->complete_cb) {
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xfer->complete_cb(xfer);
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}
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}
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static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
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static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
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uint16_t const divisor = (uint16_t) ftdi_232bm_baud_to_divisor(baudrate);
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uint16_t const divisor = (uint16_t) ftdi_232bm_baud_to_divisor(baudrate);
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p_cdc->user_control_cb = complete_cb;
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p_cdc->user_control_cb = complete_cb;
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p_cdc->requested_line_coding.bit_rate = baudrate;
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p_cdc->requested_line_coding.bit_rate = baudrate;
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TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor,
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TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor,
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complete_cb ? cdch_internal_control_complete : NULL, user_data));
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complete_cb ? ftdi_internal_control_complete : NULL, user_data));
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return true;
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return true;
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}
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}
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@@ -1065,7 +1002,7 @@ static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t cons
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static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
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static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
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p_cdc->user_control_cb = complete_cb;
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p_cdc->user_control_cb = complete_cb;
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TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state,
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TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state,
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complete_cb ? cdch_internal_control_complete : NULL, user_data));
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complete_cb ? ftdi_internal_control_complete : NULL, user_data));
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return true;
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return true;
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}
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}
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@@ -1222,11 +1159,42 @@ static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfe
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//------------- Driver API -------------//
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//------------- Driver API -------------//
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// internal control complete to update state such as line state, encoding
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static void cp210x_internal_control_complete(tuh_xfer_t * xfer) {
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uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
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uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
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cdch_interface_t * p_cdc = get_itf(idx);
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TU_ASSERT(p_cdc,);
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bool const success = (xfer->result == XFER_RESULT_SUCCESS);
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TU_LOG_P_CDC("control complete success = %u", success);
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if (success) {
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switch(xfer->setup->bRequest) {
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case CP210X_SET_MHS:
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p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue);
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break;
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case CP210X_SET_BAUDRATE:
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uint32_t baudrate;
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memcpy(&baudrate, xfer->buffer, sizeof(uint32_t));
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p_cdc->line_coding.bit_rate = tu_le32toh(baudrate);
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break;
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default: break;
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}
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}
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xfer->complete_cb = p_cdc->user_control_cb;
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if (xfer->complete_cb) {
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xfer->complete_cb(xfer);
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}
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}
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static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
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static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
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uint32_t baud_le = tu_htole32(baudrate);
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uint32_t baud_le = tu_htole32(baudrate);
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p_cdc->user_control_cb = complete_cb;
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p_cdc->user_control_cb = complete_cb;
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return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4,
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return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4,
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complete_cb ? cdch_internal_control_complete : NULL, user_data);
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complete_cb ? cp210x_internal_control_complete : NULL, user_data);
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}
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}
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static bool cp210x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
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static bool cp210x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
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@@ -1253,7 +1221,7 @@ static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t co
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static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
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static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
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p_cdc->user_control_cb = complete_cb;
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p_cdc->user_control_cb = complete_cb;
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return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0,
|
return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0,
|
||||||
complete_cb ? cdch_internal_control_complete : NULL, user_data);
|
complete_cb ? cp210x_internal_control_complete : NULL, user_data);
|
||||||
}
|
}
|
||||||
|
|
||||||
//------------- Enumeration -------------//
|
//------------- Enumeration -------------//
|
||||||
@@ -1412,9 +1380,60 @@ static bool ch34x_write_reg_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
|
|||||||
//------------- Driver API -------------//
|
//------------- Driver API -------------//
|
||||||
|
|
||||||
// internal control complete to update state such as line state, encoding
|
// internal control complete to update state such as line state, encoding
|
||||||
static void ch34x_control_complete(tuh_xfer_t* xfer) {
|
static void ch34x_internal_control_complete(tuh_xfer_t * xfer) {
|
||||||
// CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber
|
// CH34x has only interface 0, because wIndex is used as payload and not for bInterfaceNumber
|
||||||
process_internal_control_complete(xfer, 0);
|
uint8_t const itf_num = 0;
|
||||||
|
uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
|
||||||
|
cdch_interface_t * p_cdc = get_itf(idx);
|
||||||
|
TU_ASSERT(p_cdc,);
|
||||||
|
bool const success = (xfer->result == XFER_RESULT_SUCCESS);
|
||||||
|
TU_LOG_P_CDC("control complete success = %u", success);
|
||||||
|
|
||||||
|
if (success) {
|
||||||
|
switch (xfer->setup->bRequest) {
|
||||||
|
case CH34X_REQ_WRITE_REG:
|
||||||
|
// register write request
|
||||||
|
switch (tu_le16toh(xfer->setup->wValue)) {
|
||||||
|
case CH34X_REG16_DIVISOR_PRESCALER:
|
||||||
|
// baudrate
|
||||||
|
p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case CH32X_REG16_LCR2_LCR:
|
||||||
|
// data format
|
||||||
|
p_cdc->line_coding.stop_bits = p_cdc->requested_line_coding.stop_bits;
|
||||||
|
p_cdc->line_coding.parity = p_cdc->requested_line_coding.parity;
|
||||||
|
p_cdc->line_coding.data_bits = p_cdc->requested_line_coding.data_bits;
|
||||||
|
break;
|
||||||
|
|
||||||
|
default: break;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case CH34X_REQ_MODEM_CTRL:
|
||||||
|
// set modem controls RTS/DTR request. Note: signals are inverted
|
||||||
|
uint16_t const modem_signal = ~tu_le16toh(xfer->setup->wValue);
|
||||||
|
if (modem_signal & CH34X_BIT_RTS) {
|
||||||
|
p_cdc->line_state |= CDC_CONTROL_LINE_STATE_RTS;
|
||||||
|
} else {
|
||||||
|
p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_RTS;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (modem_signal & CH34X_BIT_DTR) {
|
||||||
|
p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR;
|
||||||
|
} else {
|
||||||
|
p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_DTR;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
default: break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
xfer->complete_cb = p_cdc->user_control_cb;
|
||||||
|
if (xfer->complete_cb) {
|
||||||
|
xfer->complete_cb(xfer);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
|
static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
|
||||||
@@ -1426,7 +1445,7 @@ static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, ui
|
|||||||
uint8_t const lcr = ch34x_get_lcr(stop_bits, parity, data_bits);
|
uint8_t const lcr = ch34x_get_lcr(stop_bits, parity, data_bits);
|
||||||
TU_VERIFY(lcr);
|
TU_VERIFY(lcr);
|
||||||
TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, CH32X_REG16_LCR2_LCR, lcr,
|
TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, CH32X_REG16_LCR2_LCR, lcr,
|
||||||
complete_cb ? ch34x_control_complete : NULL, user_data));
|
complete_cb ? ch34x_internal_control_complete : NULL, user_data));
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -1435,7 +1454,7 @@ static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
|
|||||||
p_cdc->requested_line_coding.bit_rate = baudrate;
|
p_cdc->requested_line_coding.bit_rate = baudrate;
|
||||||
p_cdc->user_control_cb = complete_cb;
|
p_cdc->user_control_cb = complete_cb;
|
||||||
TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, baudrate,
|
TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, baudrate,
|
||||||
complete_cb ? ch34x_control_complete : NULL, user_data));
|
complete_cb ? ch34x_internal_control_complete : NULL, user_data));
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -1450,7 +1469,7 @@ static void ch34x_set_line_coding_stage1_complete(tuh_xfer_t* xfer) {
|
|||||||
// stage 1 success, continue to stage 2
|
// stage 1 success, continue to stage 2
|
||||||
p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate;
|
p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate;
|
||||||
TU_ASSERT(ch34x_set_data_format(p_cdc, p_cdc->requested_line_coding.stop_bits, p_cdc->requested_line_coding.parity,
|
TU_ASSERT(ch34x_set_data_format(p_cdc, p_cdc->requested_line_coding.stop_bits, p_cdc->requested_line_coding.parity,
|
||||||
p_cdc->requested_line_coding.data_bits, ch34x_control_complete, xfer->user_data), );
|
p_cdc->requested_line_coding.data_bits, ch34x_internal_control_complete, xfer->user_data), );
|
||||||
} else {
|
} else {
|
||||||
// stage 1 failed, notify user
|
// stage 1 failed, notify user
|
||||||
xfer->complete_cb = p_cdc->user_control_cb;
|
xfer->complete_cb = p_cdc->user_control_cb;
|
||||||
@@ -1511,7 +1530,7 @@ static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state,
|
|||||||
|
|
||||||
p_cdc->user_control_cb = complete_cb;
|
p_cdc->user_control_cb = complete_cb;
|
||||||
TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_MODEM_CTRL, control, 0,
|
TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_MODEM_CTRL, control, 0,
|
||||||
complete_cb ? ch34x_control_complete : NULL, user_data));
|
complete_cb ? ch34x_internal_control_complete : NULL, user_data));
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
Reference in New Issue
Block a user