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change dcd_dcache_*() API return type from void to bool

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hathach
2024-11-25 19:11:19 +07:00
parent 66741e35c2
commit 833eb7d22d
8 changed files with 67 additions and 65 deletions
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6
src/device/dcd.h
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@@ -93,15 +93,15 @@ typedef struct TU_ATTR_ALIGNED(4) {
// clean/flush data cache: write cache -> memory.
// Required before an DMA TX transfer to make sure data is in memory
void dcd_dcache_clean(const void* addr, uint32_t data_size);
bool dcd_dcache_clean(const void* addr, uint32_t data_size);
// invalidate data cache: mark cache as invalid, next read will read from memory
// Required BOTH before and after an DMA RX transfer
void dcd_dcache_invalidate(const void* addr, uint32_t data_size);
bool dcd_dcache_invalidate(const void* addr, uint32_t data_size);
// clean and invalidate data cache
// Required before an DMA transfer where memory is both read/write by DMA
void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size);
bool dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size);
//--------------------------------------------------------------------+
// Controller API

9
src/device/usbd.c
View File

@@ -97,16 +97,19 @@ TU_ATTR_WEAK void dcd_disconnect(uint8_t rhport) {
(void) rhport;
}
TU_ATTR_WEAK void dcd_dcache_clean(const void* addr, uint32_t data_size) {
TU_ATTR_WEAK bool dcd_dcache_clean(const void* addr, uint32_t data_size) {
(void) addr; (void) data_size;
return true;
}
TU_ATTR_WEAK void dcd_dcache_invalidate(const void* addr, uint32_t data_size) {
TU_ATTR_WEAK bool dcd_dcache_invalidate(const void* addr, uint32_t data_size) {
(void) addr; (void) data_size;
return true;
}
TU_ATTR_WEAK void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
TU_ATTR_WEAK bool dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
(void) addr; (void) data_size;
return true;
}
//--------------------------------------------------------------------+