add new example device_virtual_com
This commit is contained in:
@@ -1,32 +1,34 @@
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//*****************************************************************************
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// +--+
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// | ++----+
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// +-++ |
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// | |
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// +-+--+ |
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// | +--+--+
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// +----+ Copyright (c) 2011-12 Code Red Technologies Ltd.
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//
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// LPC43xx Microcontroller Startup code for use with Red Suite
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//
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// Version : 120430
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//
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// Software License Agreement
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//
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// The software is owned by Code Red Technologies and/or its suppliers, and is
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// protected under applicable copyright laws. All rights are reserved. Any
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// use in violation of the foregoing restrictions may subject the user to criminal
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// sanctions under applicable laws, as well as to civil liability for the breach
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// of the terms and conditions of this license.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
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// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
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// CODE RED TECHNOLOGIES LTD.
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// LPC43xx (Cortex-M4) Microcontroller Startup code for use with LPCXpresso IDE
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//
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// Version : 150706
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//*****************************************************************************
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//
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// Copyright(C) NXP Semiconductors, 2013-2015
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// All rights reserved.
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//
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// Software that is described herein is for illustrative purposes only
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// which provides customers with programming information regarding the
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// LPC products. This software is supplied "AS IS" without any warranties of
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// any kind, and NXP Semiconductors and its licensor disclaim any and
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// all warranties, express or implied, including all implied warranties of
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// merchantability, fitness for a particular purpose and non-infringement of
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// intellectual property rights. NXP Semiconductors assumes no responsibility
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// or liability for the use of the software, conveys no license or rights under any
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// patent, copyright, mask work right, or any other intellectual property rights in
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// or to any products. NXP Semiconductors reserves the right to make changes
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// in the software without notification. NXP Semiconductors also makes no
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// representation or warranty that such application will be suitable for the
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// specified use without further testing or modification.
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//
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// Permission to use, copy, modify, and distribute this software and its
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// documentation is hereby granted, under NXP Semiconductors' and its
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// licensor's relevant copyrights in the software, without fee, provided that it
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// is used in conjunction with NXP Semiconductors microcontrollers. This
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// copyright, permission, and disclaimer notice must appear in all copies of
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// this code.
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//*****************************************************************************
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#if defined (__cplusplus)
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#ifdef __REDLIB__
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#error Redlib does not support C++
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@@ -37,7 +39,7 @@
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//
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//*****************************************************************************
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extern "C" {
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extern void __libc_init_array(void);
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extern void __libc_init_array(void);
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}
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#endif
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#endif
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@@ -45,17 +47,17 @@ extern "C" {
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#define WEAK __attribute__ ((weak))
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#define ALIAS(f) __attribute__ ((weak, alias (#f)))
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// Code Red - if CMSIS is being used, then SystemInit() routine
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// will be called by startup code rather than in application's main()
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#if defined (__USE_CMSIS)
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#include "LPC43xx.h"
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#endif
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//*****************************************************************************
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#if defined (__cplusplus)
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extern "C" {
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#endif
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//*****************************************************************************
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#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
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// Declaration of external SystemInit function
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extern void SystemInit(void);
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#endif
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//*****************************************************************************
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//
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// Forward declaration of the default handlers. These are aliased.
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@@ -63,7 +65,7 @@ extern "C" {
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// automatically take precedence over these weak definitions
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//
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//*****************************************************************************
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void ResetISR(void);
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void ResetISR(void);
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WEAK void NMI_Handler(void);
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WEAK void HardFault_Handler(void);
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WEAK void MemManage_Handler(void);
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@@ -84,9 +86,12 @@ WEAK void IntDefaultHandler(void);
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//
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//*****************************************************************************
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void DAC_IRQHandler(void) ALIAS(IntDefaultHandler);
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#if defined (__USE_LPCOPEN)
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void M0APP_IRQHandler(void) ALIAS(IntDefaultHandler);
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#else
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void M0CORE_IRQHandler(void) ALIAS(IntDefaultHandler);
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#endif
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void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
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void EZH_IRQHandler(void) ALIAS(IntDefaultHandler);
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void FLASH_EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
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void ETH_IRQHandler(void) ALIAS(IntDefaultHandler);
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void SDIO_IRQHandler(void) ALIAS(IntDefaultHandler);
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@@ -102,7 +107,7 @@ void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
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void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
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void ADC0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void SPI_IRQHandler (void) ALIAS(IntDefaultHandler);
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void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
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void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void ADC1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
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@@ -127,15 +132,18 @@ void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void EVRT_IRQHandler(void) ALIAS(IntDefaultHandler);
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void CAN1_IRQHandler(void) ALIAS(IntDefaultHandler);
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#if defined (__USE_LPCOPEN)
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void ADCHS_IRQHandler(void) ALIAS(IntDefaultHandler);
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#else
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void VADC_IRQHandler(void) ALIAS(IntDefaultHandler);
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#endif
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void ATIMER_IRQHandler(void) ALIAS(IntDefaultHandler);
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void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
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void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
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void M0s_IRQHandler(void) ALIAS(IntDefaultHandler);
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void M0SUB_IRQHandler(void) ALIAS(IntDefaultHandler);
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void CAN0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
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//*****************************************************************************
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//
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// The entry point for the application.
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@@ -154,6 +162,13 @@ extern int main(void);
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//*****************************************************************************
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extern void _vStackTop(void);
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//*****************************************************************************
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//
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// External declaration for LPC MCU vector table checksum from Linker Script
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//
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//*****************************************************************************
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WEAK extern void __valid_user_code_checksum();
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//*****************************************************************************
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#if defined (__cplusplus)
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} // extern "C"
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@@ -165,81 +180,90 @@ extern void _vStackTop(void);
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//
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//*****************************************************************************
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extern void (* const g_pfnVectors[])(void);
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__attribute__ ((section(".isr_vector")))
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__attribute__ ((used,section(".isr_vector")))
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void (* const g_pfnVectors[])(void) = {
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// Core Level - CM4
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&_vStackTop, // The initial stack pointer
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ResetISR, // The reset handler
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NMI_Handler, // The NMI handler
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HardFault_Handler, // The hard fault handler
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MemManage_Handler, // The MPU fault handler
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BusFault_Handler, // The bus fault handler
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UsageFault_Handler, // The usage fault handler
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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SVC_Handler, // SVCall handler
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DebugMon_Handler, // Debug monitor handler
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0, // Reserved
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PendSV_Handler, // The PendSV handler
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SysTick_Handler, // The SysTick handler
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// Core Level - CM4
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&_vStackTop, // The initial stack pointer
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ResetISR, // The reset handler
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NMI_Handler, // The NMI handler
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HardFault_Handler, // The hard fault handler
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MemManage_Handler, // The MPU fault handler
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BusFault_Handler, // The bus fault handler
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UsageFault_Handler, // The usage fault handler
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__valid_user_code_checksum, // LPC MCU Checksum
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0, // Reserved
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0, // Reserved
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0, // Reserved
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SVC_Handler, // SVCall handler
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DebugMon_Handler, // Debug monitor handler
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0, // Reserved
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PendSV_Handler, // The PendSV handler
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SysTick_Handler, // The SysTick handler
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// Chip Level - LPC43 (M4)
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DAC_IRQHandler, // 16
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#if defined (__USE_LPCOPEN)
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M0APP_IRQHandler, // 17 CortexM4/M0 (LPC43XX ONLY)
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#else
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M0CORE_IRQHandler, // 17
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#endif
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DMA_IRQHandler, // 18
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0, // 19
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FLASH_EEPROM_IRQHandler, // 20 ORed flash Bank A, flash Bank B, EEPROM interrupts
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ETH_IRQHandler, // 21
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SDIO_IRQHandler, // 22
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LCD_IRQHandler, // 23
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USB0_IRQHandler, // 24
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USB1_IRQHandler, // 25
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SCT_IRQHandler, // 26
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RIT_IRQHandler, // 27
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TIMER0_IRQHandler, // 28
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TIMER1_IRQHandler, // 29
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TIMER2_IRQHandler, // 30
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TIMER3_IRQHandler, // 31
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MCPWM_IRQHandler, // 32
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ADC0_IRQHandler, // 33
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I2C0_IRQHandler, // 34
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I2C1_IRQHandler, // 35
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SPI_IRQHandler, // 36
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ADC1_IRQHandler, // 37
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SSP0_IRQHandler, // 38
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SSP1_IRQHandler, // 39
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UART0_IRQHandler, // 40
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UART1_IRQHandler, // 41
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UART2_IRQHandler, // 42
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UART3_IRQHandler, // 43
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I2S0_IRQHandler, // 44
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I2S1_IRQHandler, // 45
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SPIFI_IRQHandler, // 46
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SGPIO_IRQHandler, // 47
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GPIO0_IRQHandler, // 48
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GPIO1_IRQHandler, // 49
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GPIO2_IRQHandler, // 50
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GPIO3_IRQHandler, // 51
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GPIO4_IRQHandler, // 52
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GPIO5_IRQHandler, // 53
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GPIO6_IRQHandler, // 54
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GPIO7_IRQHandler, // 55
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GINT0_IRQHandler, // 56
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GINT1_IRQHandler, // 57
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EVRT_IRQHandler, // 58
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CAN1_IRQHandler, // 59
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0, // 60
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#if defined (__USE_LPCOPEN)
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ADCHS_IRQHandler, // 61 ADCHS combined interrupt
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#else
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VADC_IRQHandler, // 61
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#endif
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ATIMER_IRQHandler, // 62
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RTC_IRQHandler, // 63
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0, // 64
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WDT_IRQHandler, // 65
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M0SUB_IRQHandler, // 66
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CAN0_IRQHandler, // 67
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QEI_IRQHandler, // 68
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};
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// Chip Level - LPC43
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DAC_IRQHandler, // 16
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M0CORE_IRQHandler, // 17
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DMA_IRQHandler, // 18
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EZH_IRQHandler, // 19
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FLASH_EEPROM_IRQHandler, // 20
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ETH_IRQHandler, // 21
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SDIO_IRQHandler, // 22
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LCD_IRQHandler, // 23
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USB0_IRQHandler, // 24
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USB1_IRQHandler, // 25
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SCT_IRQHandler, // 26
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RIT_IRQHandler, // 27
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TIMER0_IRQHandler, // 28
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TIMER1_IRQHandler, // 29
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TIMER2_IRQHandler, // 30
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TIMER3_IRQHandler, // 31
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MCPWM_IRQHandler, // 32
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ADC0_IRQHandler, // 33
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I2C0_IRQHandler, // 34
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I2C1_IRQHandler, // 35
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SPI_IRQHandler, // 36
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ADC1_IRQHandler, // 37
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SSP0_IRQHandler, // 38
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SSP1_IRQHandler, // 39
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UART0_IRQHandler, // 40
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UART1_IRQHandler, // 41
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UART2_IRQHandler, // 42
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UART3_IRQHandler, // 43
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I2S0_IRQHandler, // 44
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I2S1_IRQHandler, // 45
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SPIFI_IRQHandler, // 46
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SGPIO_IRQHandler, // 47
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GPIO0_IRQHandler, // 48
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GPIO1_IRQHandler, // 49
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GPIO2_IRQHandler, // 50
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GPIO3_IRQHandler, // 51
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GPIO4_IRQHandler, // 52
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GPIO5_IRQHandler, // 53
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GPIO6_IRQHandler, // 54
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GPIO7_IRQHandler, // 55
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GINT0_IRQHandler, // 56
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GINT1_IRQHandler, // 57
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EVRT_IRQHandler, // 58
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CAN1_IRQHandler, // 59
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0, // 60
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VADC_IRQHandler, // 61
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ATIMER_IRQHandler, // 62
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RTC_IRQHandler, // 63
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0, // 64
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WDT_IRQHandler, // 65
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M0s_IRQHandler, // 66
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CAN0_IRQHandler, // 67
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QEI_IRQHandler, // 68
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};
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//*****************************************************************************
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// Functions to carry out the initialization of RW and BSS data sections. These
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@@ -247,21 +271,22 @@ void (* const g_pfnVectors[])(void) = {
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// ResetISR() function in order to cope with MCUs with multiple banks of
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// memory.
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//*****************************************************************************
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__attribute__ ((section(".after_vectors")))
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__attribute__((section(".after_vectors"
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)))
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void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
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unsigned int *pulDest = (unsigned int*) start;
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unsigned int *pulSrc = (unsigned int*) romstart;
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unsigned int loop;
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for (loop = 0; loop < len; loop = loop + 4)
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*pulDest++ = *pulSrc++;
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unsigned int *pulDest = (unsigned int*) start;
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unsigned int *pulSrc = (unsigned int*) romstart;
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unsigned int loop;
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for (loop = 0; loop < len; loop = loop + 4)
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*pulDest++ = *pulSrc++;
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}
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__attribute__ ((section(".after_vectors")))
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void bss_init(unsigned int start, unsigned int len) {
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unsigned int *pulDest = (unsigned int*) start;
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unsigned int loop;
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for (loop = 0; loop < len; loop = loop + 4)
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*pulDest++ = 0;
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unsigned int *pulDest = (unsigned int*) start;
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unsigned int loop;
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for (loop = 0; loop < len; loop = loop + 4)
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*pulDest++ = 0;
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}
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//*****************************************************************************
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@@ -282,8 +307,7 @@ extern unsigned int __bss_section_table_end;
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// library.
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//
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//*****************************************************************************
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void
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ResetISR(void) {
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void ResetISR(void) {
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// *************************************************************
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// The following conditional block of code manually resets as
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@@ -298,123 +322,128 @@ ResetISR(void) {
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//
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#ifndef DONT_RESET_ON_RESTART
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// Disable interrupts
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__asm volatile ("cpsid i");
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// equivalent to CMSIS '__disable_irq()' function
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// Disable interrupts
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__asm volatile ("cpsid i");
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// equivalent to CMSIS '__disable_irq()' function
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unsigned int *RESET_CONTROL = (unsigned int *) 0x40053100;
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// LPC_RGU->RESET_CTRL0 @ 0x40053100
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// LPC_RGU->RESET_CTRL1 @ 0x40053104
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// Note that we do not use the CMSIS register access mechanism,
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// as there is no guarantee that the project has been configured
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// to use CMSIS.
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unsigned int *RESET_CONTROL = (unsigned int *) 0x40053100;
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// LPC_RGU->RESET_CTRL0 @ 0x40053100
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// LPC_RGU->RESET_CTRL1 @ 0x40053104
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// Note that we do not use the CMSIS register access mechanism,
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// as there is no guarantee that the project has been configured
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// to use CMSIS.
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// Write to LPC_RGU->RESET_CTRL0
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*(RESET_CONTROL+0) = 0x10DF0000;
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// GPIO_RST|AES_RST|ETHERNET_RST|SDIO_RST|DMA_RST|
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// USB1_RST|USB0_RST|LCD_RST
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// Write to LPC_RGU->RESET_CTRL0
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*(RESET_CONTROL + 0) = 0x10DF1000;
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// GPIO_RST|AES_RST|ETHERNET_RST|SDIO_RST|DMA_RST|
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// USB1_RST|USB0_RST|LCD_RST|M0_SUB_RST
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// Write to LPC_RGU->RESET_CTRL1
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*(RESET_CONTROL+1) = 0x01DFF7FF;
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// M0APP_RST|CAN0_RST|CAN1_RST|I2S_RST|SSP1_RST|SSP0_RST|
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// I2C1_RST|I2C0_RST|UART3_RST|UART1_RST|UART1_RST|UART0_RST|
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// DAC_RST|ADC1_RST|ADC0_RST|QEI_RST|MOTOCONPWM_RST|SCT_RST|
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// RITIMER_RST|TIMER3_RST|TIMER2_RST|TIMER1_RST|TIMER0_RST
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// Write to LPC_RGU->RESET_CTRL1
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*(RESET_CONTROL + 1) = 0x01DFF7FF;
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// M0APP_RST|CAN0_RST|CAN1_RST|I2S_RST|SSP1_RST|SSP0_RST|
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// I2C1_RST|I2C0_RST|UART3_RST|UART1_RST|UART1_RST|UART0_RST|
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// DAC_RST|ADC1_RST|ADC0_RST|QEI_RST|MOTOCONPWM_RST|SCT_RST|
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// RITIMER_RST|TIMER3_RST|TIMER2_RST|TIMER1_RST|TIMER0_RST
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||||
// Clear all pending interrupts in the NVIC
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||||
volatile unsigned int *NVIC_ICPR = (unsigned int *) 0xE000E280;
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||||
unsigned int irqpendloop;
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||||
for (irqpendloop = 0; irqpendloop < 8; irqpendloop++) {
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||||
*(NVIC_ICPR+irqpendloop)= 0xFFFFFFFF;
|
||||
}
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||||
// Clear all pending interrupts in the NVIC
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||||
volatile unsigned int *NVIC_ICPR = (unsigned int *) 0xE000E280;
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||||
unsigned int irqpendloop;
|
||||
for (irqpendloop = 0; irqpendloop < 8; irqpendloop++) {
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||||
*(NVIC_ICPR + irqpendloop) = 0xFFFFFFFF;
|
||||
}
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||||
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||||
// Reenable interrupts
|
||||
__asm volatile ("cpsie i");
|
||||
// equivalent to CMSIS '__enable_irq()' function
|
||||
// Reenable interrupts
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||||
__asm volatile ("cpsie i");
|
||||
// equivalent to CMSIS '__enable_irq()' function
|
||||
|
||||
#endif // ifndef DONT_RESET_ON_RESTART
|
||||
// *************************************************************
|
||||
|
||||
#if defined (__USE_LPCOPEN)
|
||||
SystemInit();
|
||||
#endif
|
||||
|
||||
//
|
||||
// Copy the data sections from flash to SRAM.
|
||||
//
|
||||
unsigned int LoadAddr, ExeAddr, SectionLen;
|
||||
unsigned int *SectionTableAddr;
|
||||
unsigned int LoadAddr, ExeAddr, SectionLen;
|
||||
unsigned int *SectionTableAddr;
|
||||
|
||||
// Load base address of Global Section Table
|
||||
SectionTableAddr = &__data_section_table;
|
||||
// Load base address of Global Section Table
|
||||
SectionTableAddr = &__data_section_table;
|
||||
|
||||
// Copy the data sections from flash to SRAM.
|
||||
while (SectionTableAddr < &__data_section_table_end) {
|
||||
LoadAddr = *SectionTableAddr++;
|
||||
ExeAddr = *SectionTableAddr++;
|
||||
SectionLen = *SectionTableAddr++;
|
||||
data_init(LoadAddr, ExeAddr, SectionLen);
|
||||
}
|
||||
// At this point, SectionTableAddr = &__bss_section_table;
|
||||
// Zero fill the bss segment
|
||||
while (SectionTableAddr < &__bss_section_table_end) {
|
||||
ExeAddr = *SectionTableAddr++;
|
||||
SectionLen = *SectionTableAddr++;
|
||||
bss_init(ExeAddr, SectionLen);
|
||||
}
|
||||
while (SectionTableAddr < &__data_section_table_end) {
|
||||
LoadAddr = *SectionTableAddr++;
|
||||
ExeAddr = *SectionTableAddr++;
|
||||
SectionLen = *SectionTableAddr++;
|
||||
data_init(LoadAddr, ExeAddr, SectionLen);
|
||||
}
|
||||
// At this point, SectionTableAddr = &__bss_section_table;
|
||||
// Zero fill the bss segment
|
||||
while (SectionTableAddr < &__bss_section_table_end) {
|
||||
ExeAddr = *SectionTableAddr++;
|
||||
SectionLen = *SectionTableAddr++;
|
||||
bss_init(ExeAddr, SectionLen);
|
||||
}
|
||||
|
||||
#if !defined (__USE_LPCOPEN)
|
||||
// LPCOpen init code deals with FP and VTOR initialisation
|
||||
#if defined (__VFP_FP__) && !defined (__SOFTFP__)
|
||||
/*
|
||||
* Code to enable the Cortex-M4 FPU only included
|
||||
* if appropriate build options have been selected.
|
||||
* Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
|
||||
*/
|
||||
// CPACR is located at address 0xE000ED88
|
||||
asm("LDR.W R0, =0xE000ED88");
|
||||
// Read CPACR
|
||||
asm("LDR R1, [R0]");
|
||||
// Set bits 20-23 to enable CP10 and CP11 coprocessors
|
||||
asm(" ORR R1, R1, #(0xF << 20)");
|
||||
// Write back the modified value to the CPACR
|
||||
asm("STR R1, [R0]");
|
||||
/*
|
||||
* Code to enable the Cortex-M4 FPU only included
|
||||
* if appropriate build options have been selected.
|
||||
* Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
|
||||
*/
|
||||
// CPACR is located at address 0xE000ED88
|
||||
asm("LDR.W R0, =0xE000ED88");
|
||||
// Read CPACR
|
||||
asm("LDR R1, [R0]");
|
||||
// Set bits 20-23 to enable CP10 and CP11 coprocessors
|
||||
asm(" ORR R1, R1, #(0xF << 20)");
|
||||
// Write back the modified value to the CPACR
|
||||
asm("STR R1, [R0]");
|
||||
#endif // (__VFP_FP__) && !(__SOFTFP__)
|
||||
|
||||
// ******************************
|
||||
// Check to see if we are running the code from a non-zero
|
||||
// ******************************
|
||||
// Check to see if we are running the code from a non-zero
|
||||
// address (eg RAM, external flash), in which case we need
|
||||
// to modify the VTOR register to tell the CPU that the
|
||||
// vector table is located at a non-0x0 address.
|
||||
|
||||
// Note that we do not use the CMSIS register access mechanism,
|
||||
// as there is no guarantee that the project has been configured
|
||||
// to use CMSIS.
|
||||
unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
|
||||
if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {
|
||||
// CMSIS : SCB->VTOR = <address of vector table>
|
||||
*pSCB_VTOR = (unsigned int)g_pfnVectors;
|
||||
}
|
||||
// Note that we do not use the CMSIS register access mechanism,
|
||||
// as there is no guarantee that the project has been configured
|
||||
// to use CMSIS.
|
||||
unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
|
||||
if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000) {
|
||||
// CMSIS : SCB->VTOR = <address of vector table>
|
||||
*pSCB_VTOR = (unsigned int) g_pfnVectors;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef __USE_CMSIS
|
||||
SystemInit();
|
||||
#if defined (__USE_CMSIS)
|
||||
SystemInit();
|
||||
#endif
|
||||
|
||||
#if defined (__cplusplus)
|
||||
//
|
||||
// Call C++ library initialisation
|
||||
//
|
||||
__libc_init_array();
|
||||
//
|
||||
// Call C++ library initialisation
|
||||
//
|
||||
__libc_init_array();
|
||||
#endif
|
||||
|
||||
#if defined (__REDLIB__)
|
||||
// Call the Redlib library, which in turn calls main()
|
||||
__main() ;
|
||||
// Call the Redlib library, which in turn calls main()
|
||||
__main();
|
||||
#else
|
||||
main();
|
||||
main();
|
||||
#endif
|
||||
|
||||
//
|
||||
// main() shouldn't return, but if it does, we'll just enter an infinite loop
|
||||
//
|
||||
while (1) {
|
||||
;
|
||||
}
|
||||
//
|
||||
// main() shouldn't return, but if it does, we'll just enter an infinite loop
|
||||
//
|
||||
while (1) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
@@ -422,66 +451,48 @@ ResetISR(void) {
|
||||
// handler routines in your application code.
|
||||
//*****************************************************************************
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
void NMI_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
void HardFault_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void MemManage_Handler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
void MemManage_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void BusFault_Handler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
void BusFault_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void UsageFault_Handler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
void UsageFault_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void SVC_Handler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
void SVC_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void DebugMon_Handler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
void DebugMon_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void PendSV_Handler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
void PendSV_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
void SysTick_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
|
||||
@@ -492,9 +503,7 @@ void SysTick_Handler(void)
|
||||
//
|
||||
//*****************************************************************************
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void IntDefaultHandler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
void IntDefaultHandler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
|
Reference in New Issue
Block a user