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Merge branch 'master' into port-ft90x

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This commit is contained in:
Ha Thach
2023-01-30 11:40:53 +07:00
committed by GitHub
parent 9f440e5c69 00c007ed68
commit 88f3279c3c
462 changed files with 14462 additions and 9057 deletions
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2
src/portable/bridgetek/ft9xx/dcd_ft9xx.c
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@@ -595,7 +595,7 @@ void dcd_remote_wakeup(uint8_t rhport)
SYS->MSC0CFG = SYS->MSC0CFG | MASK_SYS_MSC0CFG_DEV_RMWAKEUP;
// Atleast 2 ms of delay needed for RESUME Data K state.
// At least 2 ms of delay needed for RESUME Data K state.
delayms(2);
SYS->MSC0CFG &= ~MASK_SYS_MSC0CFG_DEV_RMWAKEUP;

2
src/portable/dialog/da146xx/dcd_da146xx.c
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@@ -243,7 +243,7 @@ static struct
// Converts xfer pointer to epnum (0,1,2,3) regardless of xfer direction
#define XFER_EPNUM(xfer) ((xfer - &_dcd.xfer_status[0][0]) >> 1)
// Converts xfer pinter to EPx_REGS pointer (returns same pointer for IN and OUT with same endpoint number)
// Converts xfer pointer to EPx_REGS pointer (returns same pointer for IN and OUT with same endpoint number)
#define XFER_REGS(xfer) ep_regs[XFER_EPNUM(xfer)]
// Converts epnum (0,1,2,3) to EPx_REGS pointer
#define EPNUM_REGS(epnum) ep_regs[epnum]

6
src/portable/ehci/ehci.c
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@@ -188,7 +188,7 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport)
static void list_remove_qhd_by_addr(ehci_link_t* list_head, uint8_t dev_addr)
{
for(ehci_link_t* prev = list_head;
!prev->terminate && (tu_align32(prev->address) != (uint32_t) list_head);
!prev->terminate && (tu_align32(prev->address) != (uint32_t) list_head) && prev != NULL;
prev = list_next(prev) )
{
// TODO check type for ISO iTD and siTD
@@ -199,7 +199,7 @@ static void list_remove_qhd_by_addr(ehci_link_t* list_head, uint8_t dev_addr)
#pragma GCC diagnostic pop
if ( qhd->dev_addr == dev_addr )
{
// TODO deactive all TD, wait for QHD to inactive before removal
// TODO deactivate all TD, wait for QHD to inactive before removal
prev->address = qhd->next.address;
// EHCI 4.8.2 link the removed qhd to async head (which always reachable by Host Controller)
@@ -839,7 +839,7 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c
if (TUSB_SPEED_HIGH == p_qhd->ep_speed)
{
TU_ASSERT( interval <= 16, );
if ( interval < 4) // sub milisecond interval
if ( interval < 4) // sub millisecond interval
{
p_qhd->interval_ms = 0;
p_qhd->int_smask = (interval == 1) ? TU_BIN8(11111111) :

10
src/portable/ehci/ehci.h
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@@ -114,7 +114,7 @@ typedef struct
volatile uint32_t current_page : 3 ; ///< Index into the qTD buffer pointer list
uint32_t int_on_complete : 1 ; ///< Interrupt on complete
volatile uint32_t total_bytes : 15 ; ///< Transfer bytes, decreased during transaction
volatile uint32_t data_toggle : 1 ; ///< Data Toogle bit
volatile uint32_t data_toggle : 1 ; ///< Data Toggle bit
/// Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
@@ -160,7 +160,7 @@ typedef struct TU_ATTR_ALIGNED(32)
uint8_t used;
uint8_t removing; // removed from asyn list, waiting for async advance
uint8_t pid;
uint8_t interval_ms; // polling interval in frames (or milisecond)
uint8_t interval_ms; // polling interval in frames (or millisecond)
uint16_t total_xferred_bytes; // number of bytes xferred until a qtd with ioc bit set
uint8_t reserved2[2];
@@ -225,7 +225,7 @@ typedef struct TU_ATTR_ALIGNED(32)
uint16_t reserved ; ///< reserved
// Word 3: siTD Transfer Status and Control
// Status [7:0] TODO indentical to qTD Token'status --> refractor later
// Status [7:0] TODO identical to qTD Token'status --> refactor later
volatile uint32_t : 1 ; // reserved
volatile uint32_t split_state : 1 ;
volatile uint32_t missed_uframe : 1 ;
@@ -350,8 +350,8 @@ typedef volatile struct
uint32_t periodic_status : 1 ; ///< Periodic schedule status
uint32_t async_status : 1 ; ///< Async schedule status
uint32_t : 2 ;
uint32_t nxp_int_async : 1 ; ///< NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set andthe TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected andthe packet is on the asynchronous schedule.
uint32_t nxp_int_period : 1 ; ///< NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set andthe TD was from the periodic schedule.
uint32_t nxp_int_async : 1 ; ///< NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule.
uint32_t nxp_int_period : 1 ; ///< NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule.
uint32_t : 12 ;
}status_bm;
};

2
src/portable/espressif/esp32sx/dcd_esp32sx.c
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@@ -741,7 +741,7 @@ static void handle_epin_ints(void)
// XFER Timeout
if (USB0.in_ep_reg[n].diepint & USB_D_TIMEOUT0_M) {
// Clear interrupt or enpoint will hang.
// Clear interrupt or endpoint will hang.
USB0.in_ep_reg[n].diepint = USB_D_TIMEOUT0_M;
// Maybe retry?
}

6
src/portable/microchip/pic32mz/usbhs_registers.h
View File

@@ -21,16 +21,16 @@
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*******************************************************************************/
/*******************************************************************************
USBHS Peripheral Library Register Defintions
USBHS Peripheral Library Register Definitions
File Name:
usbhs_registers.h
Summary:
USBHS PLIB Register Defintions
USBHS PLIB Register Definitions
Description:
This file contains the constants and defintions which are required by the
This file contains the constants and definitions which are required by the
the USBHS library.
*******************************************************************************/

6
src/portable/microchip/samx7x/dcd_samx7x.c
View File

@@ -42,7 +42,7 @@
# define USE_SOF 0
#endif
// Dual bank can imporve performance, but need 2 times bigger packet buffer
// Dual bank can improve performance, but need 2 times bigger packet buffer
// As SAM7x has only 4KB packet buffer, use with caution !
// Enable in FS mode as packets are smaller
#ifndef USE_DUAL_BANK
@@ -644,7 +644,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
}
__set_PRIMASK(irq_state);
// Here a ZLP has been recieved
// Here a ZLP has been received
// and the DMA transfer must be not started.
// It is the end of transfer
return false;
@@ -734,7 +734,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
}
__set_PRIMASK(irq_state);
// Here a ZLP has been recieved
// Here a ZLP has been received
// and the DMA transfer must be not started.
// It is the end of transfer
return false;

2
src/portable/nordic/nrf5x/dcd_nrf5x.c
View File

@@ -170,7 +170,7 @@ static void xact_out_dma(uint8_t epnum)
uint32_t xact_len;
// DMA can't be active during read of SIZE.EPOUT or SIZE.ISOOUT, so try to lock,
// If already running deffer call regardless if it was called from ISR or task,
// If already running defer call regardless if it was called from ISR or task,
if ( atomic_flag_test_and_set(&_dcd.dma_running) )
{
usbd_defer_func((osal_task_func_t)xact_out_dma_wrapper, (void *)(uint32_t)epnum, is_in_isr());

2
src/portable/nuvoton/nuc505/dcd_nuc505.c
View File

@@ -181,7 +181,7 @@ static void dcd_userEP_in_xfer(struct xfer_ctl_t *xfer, USBD_EP_T *ep)
ep->EPINTEN = USBD_EPINTEN_TXPKIEN_Msk;
}
/* provided buffers are thankfully 32-bit aligned, allowing most data to be transfered as 32-bit */
/* provided buffers are thankfully 32-bit aligned, allowing most data to be transferred as 32-bit */
#if 0 // TODO support dcd_edpt_xfer_fifo API
if (xfer->ff)
{

34
src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
View File

@@ -139,7 +139,7 @@ typedef union TU_ATTR_PACKED
uint32_t stall : 1 ;
uint32_t disable : 1 ;
uint32_t active : 1 ;
};
} cmd_sts;
}ep_cmd_sts_t;
TU_VERIFY_STATIC( sizeof(ep_cmd_sts_t) == 4, "size is not correct" );
@@ -329,7 +329,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
// TODO cannot able to STALL Control OUT endpoint !!!!! FIXME try some walk-around
uint8_t const ep_id = ep_addr2id(ep_addr);
_dcd.ep[ep_id][0].stall = 1;
_dcd.ep[ep_id][0].cmd_sts.stall = 1;
}
void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
@@ -338,9 +338,9 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
uint8_t const ep_id = ep_addr2id(ep_addr);
_dcd.ep[ep_id][0].stall = 0;
_dcd.ep[ep_id][0].toggle_reset = 1;
_dcd.ep[ep_id][0].toggle_mode = 0;
_dcd.ep[ep_id][0].cmd_sts.stall = 0;
_dcd.ep[ep_id][0].cmd_sts.toggle_reset = 1;
_dcd.ep[ep_id][0].cmd_sts.toggle_mode = 0;
}
bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
@@ -349,10 +349,10 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
uint8_t ep_id = ep_addr2id(p_endpoint_desc->bEndpointAddress);
// Check if endpoint is available
TU_ASSERT( _dcd.ep[ep_id][0].disable && _dcd.ep[ep_id][1].disable );
TU_ASSERT( _dcd.ep[ep_id][0].cmd_sts.disable && _dcd.ep[ep_id][1].cmd_sts.disable );
edpt_reset(rhport, ep_id);
_dcd.ep[ep_id][0].is_iso = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
_dcd.ep[ep_id][0].cmd_sts.is_iso = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
// Enable EP interrupt
dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
@@ -365,8 +365,8 @@ void dcd_edpt_close_all (uint8_t rhport)
{
for (uint8_t ep_id = 0; ep_id < 2*_dcd_controller[rhport].ep_pairs; ++ep_id)
{
_dcd.ep[ep_id][0].active = _dcd.ep[ep_id][0].active = 0; // TODO proper way is to EPSKIP then wait ep[][].active then write ep[][].disable (see table 778 in LPC55S69 Use Manual)
_dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1;
_dcd.ep[ep_id][0].cmd_sts.active = _dcd.ep[ep_id][0].cmd_sts.active = 0; // TODO proper way is to EPSKIP then wait ep[][].active then write ep[][].disable (see table 778 in LPC55S69 Use Manual)
_dcd.ep[ep_id][0].cmd_sts.disable = _dcd.ep[ep_id][1].cmd_sts.disable = 1;
}
}
@@ -375,8 +375,8 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
(void) rhport;
uint8_t ep_id = ep_addr2id(ep_addr);
_dcd.ep[ep_id][0].active = _dcd.ep[ep_id][0].active = 0; // TODO proper way is to EPSKIP then wait ep[][].active then write ep[][].disable (see table 778 in LPC55S69 Use Manual)
_dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1;
_dcd.ep[ep_id][0].cmd_sts.active = _dcd.ep[ep_id][0].cmd_sts.active = 0; // TODO proper way is to EPSKIP then wait ep[][].active then write ep[][].disable (see table 778 in LPC55S69 Use Manual)
_dcd.ep[ep_id][0].cmd_sts.disable = _dcd.ep[ep_id][1].cmd_sts.disable = 1;
}
static void prepare_ep_xfer(uint8_t rhport, uint8_t ep_id, uint16_t buf_offset, uint16_t total_bytes)
@@ -385,7 +385,7 @@ static void prepare_ep_xfer(uint8_t rhport, uint8_t ep_id, uint16_t buf_offset,
if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL )
{
nbytes = tu_min16(total_bytes, _dcd.ep[ep_id][0].is_iso ? NBYTES_ISO_FS_MAX : NBYTES_CBI_FS_MAX);
nbytes = tu_min16(total_bytes, _dcd.ep[ep_id][0].cmd_sts.is_iso ? NBYTES_ISO_FS_MAX : NBYTES_CBI_FS_MAX);
_dcd.ep[ep_id][0].buffer_fs.offset = buf_offset;
_dcd.ep[ep_id][0].buffer_fs.nbytes = nbytes;
}else
@@ -397,7 +397,7 @@ static void prepare_ep_xfer(uint8_t rhport, uint8_t ep_id, uint16_t buf_offset,
_dcd.dma[ep_id].nbytes = nbytes;
_dcd.ep[ep_id][0].active = 1;
_dcd.ep[ep_id][0].cmd_sts.active = 1;
}
bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
@@ -431,7 +431,7 @@ static void bus_reset(uint8_t rhport)
// disable all endpoints as specified by LPC55S69 UM Table 778
for(uint8_t ep_id = 0; ep_id < 2*MAX_EP_PAIRS; ep_id++)
{
_dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1;
_dcd.ep[ep_id][0].cmd_sts.disable = _dcd.ep[ep_id][1].cmd_sts.disable = 1;
}
dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
@@ -459,7 +459,7 @@ static void process_xfer_isr(uint8_t rhport, uint32_t int_status)
if ( ep_id == 0 || ep_id == 1)
{
// For control endpoint, we need to manually clear Active bit
ep_cs->active = 0;
ep_cs->cmd_sts.active = 0;
}
uint16_t buf_offset;
@@ -556,8 +556,8 @@ void dcd_int_handler(uint8_t rhport)
if ( tu_bit_test(int_status, 0) && (cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) )
{
// Follow UM flowchart to clear Active & Stall on both Control IN/OUT endpoints
_dcd.ep[0][0].active = _dcd.ep[1][0].active = 0;
_dcd.ep[0][0].stall = _dcd.ep[1][0].stall = 0;
_dcd.ep[0][0].cmd_sts.active = _dcd.ep[1][0].cmd_sts.active = 0;
_dcd.ep[0][0].cmd_sts.stall = _dcd.ep[1][0].cmd_sts.stall = 0;
dcd_reg->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK;

2
src/portable/ohci/ohci.c
View File

@@ -165,7 +165,7 @@ bool hcd_init(uint8_t rhport)
//------------- Data Structure init -------------//
tu_memclr(&ohci_data, sizeof(ohci_data_t));
for(uint8_t i=0; i<32; i++)
{ // assign all interrupt pointes to period head ed
{ // assign all interrupt pointers to period head ed
ohci_data.hcca.interrupt_table[i] = (uint32_t) &ohci_data.period_head_ed;
}

2
src/portable/ohci/ohci.h
View File

@@ -34,7 +34,7 @@
//--------------------------------------------------------------------+
// OHCI CONFIGURATION & CONSTANTS
//--------------------------------------------------------------------+
#define HOST_HCD_XFER_INTERRUPT // TODO interrupt is used widely, should always be enalbed
#define HOST_HCD_XFER_INTERRUPT // TODO interrupt is used widely, should always be enabled
#define OHCI_PERIODIC_LIST (defined HOST_HCD_XFER_INTERRUPT || defined HOST_HCD_XFER_ISOCHRONOUS)
// TODO merge OHCI with EHCI

583
src/portable/raspberrypi/rp2040/hcd_rp2040.c
View File

@@ -81,89 +81,90 @@ static struct hw_endpoint *get_dev_ep(uint8_t dev_addr, uint8_t ep_addr)
TU_ATTR_ALWAYS_INLINE static inline uint8_t dev_speed(void)
{
return (usb_hw->sie_status & USB_SIE_STATUS_SPEED_BITS) >> USB_SIE_STATUS_SPEED_LSB;
return (usb_hw->sie_status & USB_SIE_STATUS_SPEED_BITS) >> USB_SIE_STATUS_SPEED_LSB;
}
static bool need_pre(uint8_t dev_addr)
TU_ATTR_ALWAYS_INLINE static inline bool need_pre(uint8_t dev_addr)
{
// If this device is different to the speed of the root device
// (i.e. is a low speed device on a full speed hub) then need pre
return hcd_port_speed_get(0) != tuh_speed_get(dev_addr);
// If this device is different to the speed of the root device
// (i.e. is a low speed device on a full speed hub) then need pre
return hcd_port_speed_get(0) != tuh_speed_get(dev_addr);
}
static void __tusb_irq_path_func(hw_xfer_complete)(struct hw_endpoint *ep, xfer_result_t xfer_result)
{
// Mark transfer as done before we tell the tinyusb stack
uint8_t dev_addr = ep->dev_addr;
uint8_t ep_addr = ep->ep_addr;
uint xferred_len = ep->xferred_len;
hw_endpoint_reset_transfer(ep);
hcd_event_xfer_complete(dev_addr, ep_addr, xferred_len, xfer_result, true);
// Mark transfer as done before we tell the tinyusb stack
uint8_t dev_addr = ep->dev_addr;
uint8_t ep_addr = ep->ep_addr;
uint xferred_len = ep->xferred_len;
hw_endpoint_reset_transfer(ep);
hcd_event_xfer_complete(dev_addr, ep_addr, xferred_len, xfer_result, true);
}
static void __tusb_irq_path_func(_handle_buff_status_bit)(uint bit, struct hw_endpoint *ep)
{
usb_hw_clear->buf_status = bit;
// EP may have been stalled?
assert(ep->active);
bool done = hw_endpoint_xfer_continue(ep);
if (done)
{
hw_xfer_complete(ep, XFER_RESULT_SUCCESS);
}
usb_hw_clear->buf_status = bit;
// EP may have been stalled?
assert(ep->active);
bool done = hw_endpoint_xfer_continue(ep);
if ( done )
{
hw_xfer_complete(ep, XFER_RESULT_SUCCESS);
}
}
static void __tusb_irq_path_func(hw_handle_buff_status)(void)
{
uint32_t remaining_buffers = usb_hw->buf_status;
pico_trace("buf_status 0x%08x\n", remaining_buffers);
uint32_t remaining_buffers = usb_hw->buf_status;
pico_trace("buf_status 0x%08x\n", remaining_buffers);
// Check EPX first
uint bit = 0b1;
if (remaining_buffers & bit)
// Check EPX first
uint bit = 0b1;
if ( remaining_buffers & bit )
{
remaining_buffers &= ~bit;
struct hw_endpoint * ep = &epx;
uint32_t ep_ctrl = *ep->endpoint_control;
if ( ep_ctrl & EP_CTRL_DOUBLE_BUFFERED_BITS )
{
TU_LOG(3, "Double Buffered: ");
}
else
{
TU_LOG(3, "Single Buffered: ");
}
TU_LOG_HEX(3, ep_ctrl);
_handle_buff_status_bit(bit, ep);
}
// Check "interrupt" (asynchronous) endpoints for both IN and OUT
for ( uint i = 1; i <= USB_HOST_INTERRUPT_ENDPOINTS && remaining_buffers; i++ )
{
// EPX is bit 0 & 1
// IEP1 IN is bit 2
// IEP1 OUT is bit 3
// IEP2 IN is bit 4
// IEP2 OUT is bit 5
// IEP3 IN is bit 6
// IEP3 OUT is bit 7
// etc
for ( uint j = 0; j < 2; j++ )
{
bit = 1 << (i * 2 + j);
if ( remaining_buffers & bit )
{
remaining_buffers &= ~bit;
struct hw_endpoint *ep = &epx;
uint32_t ep_ctrl = *ep->endpoint_control;
if (ep_ctrl & EP_CTRL_DOUBLE_BUFFERED_BITS)
{
TU_LOG(3, "Double Buffered: ");
}else
{
TU_LOG(3, "Single Buffered: ");
}
TU_LOG_HEX(3, ep_ctrl);
_handle_buff_status_bit(bit, ep);
_handle_buff_status_bit(bit, &ep_pool[i]);
}
}
}
// Check "interrupt" (asynchronous) endpoints for both IN and OUT
for (uint i = 1; i <= USB_HOST_INTERRUPT_ENDPOINTS && remaining_buffers; i++)
{
// EPX is bit 0 & 1
// IEP1 IN is bit 2
// IEP1 OUT is bit 3
// IEP2 IN is bit 4
// IEP2 OUT is bit 5
// IEP3 IN is bit 6
// IEP3 OUT is bit 7
// etc
for(uint j = 0; j < 2; j++)
{
bit = 1 << (i*2+j);
if (remaining_buffers & bit)
{
remaining_buffers &= ~bit;
_handle_buff_status_bit(bit, &ep_pool[i]);
}
}
}
if (remaining_buffers)
{
panic("Unhandled buffer %d\n", remaining_buffers);
}
if ( remaining_buffers )
{
panic("Unhandled buffer %d\n", remaining_buffers);
}
}
static void __tusb_irq_path_func(hw_trans_complete)(void)
@@ -186,70 +187,72 @@ static void __tusb_irq_path_func(hw_trans_complete)(void)
static void __tusb_irq_path_func(hcd_rp2040_irq)(void)
{
uint32_t status = usb_hw->ints;
uint32_t handled = 0;
uint32_t status = usb_hw->ints;
uint32_t handled = 0;
if (status & USB_INTS_HOST_CONN_DIS_BITS)
if ( status & USB_INTS_HOST_CONN_DIS_BITS )
{
handled |= USB_INTS_HOST_CONN_DIS_BITS;
if ( dev_speed() )
{
handled |= USB_INTS_HOST_CONN_DIS_BITS;
if (dev_speed())
{
hcd_event_device_attach(RHPORT_NATIVE, true);
}
else
{
hcd_event_device_remove(RHPORT_NATIVE, true);
}
// Clear speed change interrupt
usb_hw_clear->sie_status = USB_SIE_STATUS_SPEED_BITS;
hcd_event_device_attach(RHPORT_NATIVE, true);
}
else
{
hcd_event_device_remove(RHPORT_NATIVE, true);
}
if (status & USB_INTS_STALL_BITS)
{
// We have rx'd a stall from the device
// NOTE THIS SHOULD HAVE PRIORITY OVER BUFF_STATUS
// AND TRANS_COMPLETE as the stall is an alternative response
// to one of those events
pico_trace("Stall REC\n");
handled |= USB_INTS_STALL_BITS;
usb_hw_clear->sie_status = USB_SIE_STATUS_STALL_REC_BITS;
hw_xfer_complete(&epx, XFER_RESULT_STALLED);
}
// Clear speed change interrupt
usb_hw_clear->sie_status = USB_SIE_STATUS_SPEED_BITS;
}
if (status & USB_INTS_BUFF_STATUS_BITS)
{
handled |= USB_INTS_BUFF_STATUS_BITS;
TU_LOG(2, "Buffer complete\n");
hw_handle_buff_status();
}
if ( status & USB_INTS_STALL_BITS )
{
// We have rx'd a stall from the device
// NOTE THIS SHOULD HAVE PRIORITY OVER BUFF_STATUS
// AND TRANS_COMPLETE as the stall is an alternative response
// to one of those events
pico_trace("Stall REC\n");
handled |= USB_INTS_STALL_BITS;
usb_hw_clear->sie_status = USB_SIE_STATUS_STALL_REC_BITS;
hw_xfer_complete(&epx, XFER_RESULT_STALLED);
}
if (status & USB_INTS_TRANS_COMPLETE_BITS)
{
handled |= USB_INTS_TRANS_COMPLETE_BITS;
usb_hw_clear->sie_status = USB_SIE_STATUS_TRANS_COMPLETE_BITS;
TU_LOG(2, "Transfer complete\n");
hw_trans_complete();
}
if ( status & USB_INTS_BUFF_STATUS_BITS )
{
handled |= USB_INTS_BUFF_STATUS_BITS;
TU_LOG(2, "Buffer complete\n");
hw_handle_buff_status();
}
if (status & USB_INTS_ERROR_RX_TIMEOUT_BITS)
{
handled |= USB_INTS_ERROR_RX_TIMEOUT_BITS;
usb_hw_clear->sie_status = USB_SIE_STATUS_RX_TIMEOUT_BITS;
}
if ( status & USB_INTS_TRANS_COMPLETE_BITS )
{
handled |= USB_INTS_TRANS_COMPLETE_BITS;
usb_hw_clear->sie_status = USB_SIE_STATUS_TRANS_COMPLETE_BITS;
TU_LOG(2, "Transfer complete\n");
hw_trans_complete();
}
if (status & USB_INTS_ERROR_DATA_SEQ_BITS)
{
usb_hw_clear->sie_status = USB_SIE_STATUS_DATA_SEQ_ERROR_BITS;
TU_LOG(3, " Seq Error: [0] = 0x%04u [1] = 0x%04x\r\n", tu_u32_low16(*epx.buffer_control), tu_u32_high16(*epx.buffer_control));
panic("Data Seq Error \n");
}
if ( status & USB_INTS_ERROR_RX_TIMEOUT_BITS )
{
handled |= USB_INTS_ERROR_RX_TIMEOUT_BITS;
usb_hw_clear->sie_status = USB_SIE_STATUS_RX_TIMEOUT_BITS;
}
if (status ^ handled)
{
panic("Unhandled IRQ 0x%x\n", (uint) (status ^ handled));
}
if ( status & USB_INTS_ERROR_DATA_SEQ_BITS )
{
usb_hw_clear->sie_status = USB_SIE_STATUS_DATA_SEQ_ERROR_BITS;
TU_LOG(3, " Seq Error: [0] = 0x%04u [1] = 0x%04x\r\n",
tu_u32_low16(*epx.buffer_control),
tu_u32_high16(*epx.buffer_control));
panic("Data Seq Error \n");
}
if ( status ^ handled )
{
panic("Unhandled IRQ 0x%x\n", (uint) (status ^ handled));
}
}
void __tusb_irq_path_func(hcd_int_handler)(uint8_t rhport)
@@ -260,116 +263,118 @@ void __tusb_irq_path_func(hcd_int_handler)(uint8_t rhport)
static struct hw_endpoint *_next_free_interrupt_ep(void)
{
struct hw_endpoint *ep = NULL;
for (uint i = 1; i < TU_ARRAY_SIZE(ep_pool); i++)
struct hw_endpoint * ep = NULL;
for ( uint i = 1; i < TU_ARRAY_SIZE(ep_pool); i++ )
{
ep = &ep_pool[i];
if ( !ep->configured )
{
ep = &ep_pool[i];
if (!ep->configured)
{
// Will be configured by _hw_endpoint_init / _hw_endpoint_allocate
ep->interrupt_num = (uint8_t) (i - 1);
return ep;
}
// Will be configured by _hw_endpoint_init / _hw_endpoint_allocate
ep->interrupt_num = (uint8_t) (i - 1);
return ep;
}
return ep;
}
return ep;
}
static struct hw_endpoint *_hw_endpoint_allocate(uint8_t transfer_type)
{
struct hw_endpoint *ep = NULL;
struct hw_endpoint * ep = NULL;
if (transfer_type != TUSB_XFER_CONTROL)
{
// Note: even though datasheet name these "Interrupt" endpoints. These are actually
// "Asynchronous" endpoints and can be used for other type such as: Bulk (ISO need confirmation)
ep = _next_free_interrupt_ep();
pico_info("Allocate %s ep %d\n", tu_edpt_type_str(transfer_type), ep->interrupt_num);
assert(ep);
ep->buffer_control = &usbh_dpram->int_ep_buffer_ctrl[ep->interrupt_num].ctrl;
ep->endpoint_control = &usbh_dpram->int_ep_ctrl[ep->interrupt_num].ctrl;
// 0 for epx (double buffered): TODO increase to 1024 for ISO
// 2x64 for intep0
// 3x64 for intep1
// etc
ep->hw_data_buf = &usbh_dpram->epx_data[64 * (ep->interrupt_num + 2)];
}
else
{
ep = &epx;
ep->buffer_control = &usbh_dpram->epx_buf_ctrl;
ep->endpoint_control = &usbh_dpram->epx_ctrl;
ep->hw_data_buf = &usbh_dpram->epx_data[0];
}
if ( transfer_type != TUSB_XFER_CONTROL )
{
// Note: even though datasheet name these "Interrupt" endpoints. These are actually
// "Asynchronous" endpoints and can be used for other type such as: Bulk (ISO need confirmation)
ep = _next_free_interrupt_ep();
pico_info("Allocate %s ep %d\n", tu_edpt_type_str(transfer_type), ep->interrupt_num);
assert(ep);
ep->buffer_control = &usbh_dpram->int_ep_buffer_ctrl[ep->interrupt_num].ctrl;
ep->endpoint_control = &usbh_dpram->int_ep_ctrl[ep->interrupt_num].ctrl;
// 0 for epx (double buffered): TODO increase to 1024 for ISO
// 2x64 for intep0
// 3x64 for intep1
// etc
ep->hw_data_buf = &usbh_dpram->epx_data[64 * (ep->interrupt_num + 2)];
}
else
{
ep = &epx;
ep->buffer_control = &usbh_dpram->epx_buf_ctrl;
ep->endpoint_control = &usbh_dpram->epx_ctrl;
ep->hw_data_buf = &usbh_dpram->epx_data[0];
}
return ep;
return ep;
}
static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type, uint8_t bmInterval)
{
// Already has data buffer, endpoint control, and buffer control allocated at this point
assert(ep->endpoint_control);
assert(ep->buffer_control);
assert(ep->hw_data_buf);
// Already has data buffer, endpoint control, and buffer control allocated at this point
assert(ep->endpoint_control);
assert(ep->buffer_control);
assert(ep->hw_data_buf);
uint8_t const num = tu_edpt_number(ep_addr);
tusb_dir_t const dir = tu_edpt_dir(ep_addr);
uint8_t const num = tu_edpt_number(ep_addr);
tusb_dir_t const dir = tu_edpt_dir(ep_addr);
ep->ep_addr = ep_addr;
ep->dev_addr = dev_addr;
ep->ep_addr = ep_addr;
ep->dev_addr = dev_addr;
// For host, IN to host == RX, anything else rx == false
ep->rx = (dir == TUSB_DIR_IN);
// For host, IN to host == RX, anything else rx == false
ep->rx = (dir == TUSB_DIR_IN);
// Response to a setup packet on EP0 starts with pid of 1
ep->next_pid = (num == 0 ? 1u : 0u);
ep->wMaxPacketSize = wMaxPacketSize;
ep->transfer_type = transfer_type;
// Response to a setup packet on EP0 starts with pid of 1
ep->next_pid = (num == 0 ? 1u : 0u);
ep->wMaxPacketSize = wMaxPacketSize;
ep->transfer_type = transfer_type;
pico_trace("hw_endpoint_init dev %d ep %d %s xfer %d\n", ep->dev_addr, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)], ep->transfer_type);
pico_trace("dev %d ep %d %s setup buffer @ 0x%p\n", ep->dev_addr, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)], ep->hw_data_buf);
uint dpram_offset = hw_data_offset(ep->hw_data_buf);
// Bits 0-5 should be 0
assert(!(dpram_offset & 0b111111));
pico_trace("hw_endpoint_init dev %d ep %d %s xfer %d\n", ep->dev_addr, tu_edpt_number(ep->ep_addr),
ep_dir_string[tu_edpt_dir(ep->ep_addr)], ep->transfer_type);
pico_trace("dev %d ep %d %s setup buffer @ 0x%p\n", ep->dev_addr, tu_edpt_number(ep->ep_addr),
ep_dir_string[tu_edpt_dir(ep->ep_addr)], ep->hw_data_buf);
uint dpram_offset = hw_data_offset(ep->hw_data_buf);
// Bits 0-5 should be 0
assert(!(dpram_offset & 0b111111));
// Fill in endpoint control register with buffer offset
uint32_t ep_reg = EP_CTRL_ENABLE_BITS
| EP_CTRL_INTERRUPT_PER_BUFFER
| (ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB)
| dpram_offset;
if (bmInterval)
// Fill in endpoint control register with buffer offset
uint32_t ep_reg = EP_CTRL_ENABLE_BITS
| EP_CTRL_INTERRUPT_PER_BUFFER
| (ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB)
| dpram_offset;
if ( bmInterval )
{
ep_reg |= (uint32_t) ((bmInterval - 1) << EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB);
}
*ep->endpoint_control = ep_reg;
pico_trace("endpoint control (0x%p) <- 0x%x\n", ep->endpoint_control, ep_reg);
ep->configured = true;
if ( ep != &epx )
{
// Endpoint has its own addr_endp and interrupt bits to be setup!
// This is an interrupt/async endpoint. so need to set up ADDR_ENDP register with:
// - device address
// - endpoint number / direction
// - preamble
uint32_t reg = (uint32_t) (dev_addr | (num << USB_ADDR_ENDP1_ENDPOINT_LSB));
if ( dir == TUSB_DIR_OUT )
{
ep_reg |= (uint32_t) ((bmInterval - 1) << EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB);
reg |= USB_ADDR_ENDP1_INTEP_DIR_BITS;
}
*ep->endpoint_control = ep_reg;
pico_trace("endpoint control (0x%p) <- 0x%x\n", ep->endpoint_control, ep_reg);
ep->configured = true;
if (ep != &epx)
if ( need_pre(dev_addr) )
{
// Endpoint has its own addr_endp and interrupt bits to be setup!
// This is an interrupt/async endpoint. so need to set up ADDR_ENDP register with:
// - device address
// - endpoint number / direction
// - preamble
uint32_t reg = (uint32_t) (dev_addr | (num << USB_ADDR_ENDP1_ENDPOINT_LSB));
if (dir == TUSB_DIR_OUT)
{
reg |= USB_ADDR_ENDP1_INTEP_DIR_BITS;
}
if (need_pre(dev_addr))
{
reg |= USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS;
}
usb_hw->int_ep_addr_ctrl[ep->interrupt_num] = reg;
// Finally, enable interrupt that endpoint
usb_hw_set->int_ep_ctrl = 1 << (ep->interrupt_num + 1);
// If it's an interrupt endpoint we need to set up the buffer control
// register
reg |= USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS;
}
usb_hw->int_ep_addr_ctrl[ep->interrupt_num] = reg;
// Finally, enable interrupt that endpoint
usb_hw_set->int_ep_ctrl = 1 << (ep->interrupt_num + 1);
// If it's an interrupt endpoint we need to set up the buffer control
// register
}
}
//--------------------------------------------------------------------+
@@ -434,16 +439,17 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport)
{
(void) rhport;
assert(rhport == 0);
// TODO: Should enumval this register
switch (dev_speed())
switch ( dev_speed() )
{
case 1:
return TUSB_SPEED_LOW;
case 2:
return TUSB_SPEED_FULL;
default:
panic("Invalid speed\n");
return TUSB_SPEED_INVALID;
case 1:
return TUSB_SPEED_LOW;
case 2:
return TUSB_SPEED_FULL;
default:
panic("Invalid speed\n");
return TUSB_SPEED_INVALID;
}
}
@@ -476,8 +482,8 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
uint32_t hcd_frame_number(uint8_t rhport)
{
(void) rhport;
return usb_hw->sof_rd;
(void) rhport;
return usb_hw->sof_rd;
}
void hcd_int_enable(uint8_t rhport)
@@ -501,117 +507,116 @@ void hcd_int_disable(uint8_t rhport)
bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
{
(void) rhport;
(void) rhport;
pico_trace("hcd_edpt_open dev_addr %d, ep_addr %d\n", dev_addr, ep_desc->bEndpointAddress);
pico_trace("hcd_edpt_open dev_addr %d, ep_addr %d\n", dev_addr, ep_desc->bEndpointAddress);
// Allocated differently based on if it's an interrupt endpoint or not
struct hw_endpoint *ep = _hw_endpoint_allocate(ep_desc->bmAttributes.xfer);
TU_ASSERT(ep);
// Allocated differently based on if it's an interrupt endpoint or not
struct hw_endpoint *ep = _hw_endpoint_allocate(ep_desc->bmAttributes.xfer);
TU_ASSERT(ep);
_hw_endpoint_init(ep,
dev_addr,
ep_desc->bEndpointAddress,
tu_edpt_packet_size(ep_desc),
ep_desc->bmAttributes.xfer,
ep_desc->bInterval);
_hw_endpoint_init(ep,
dev_addr,
ep_desc->bEndpointAddress,
tu_edpt_packet_size(ep_desc),
ep_desc->bmAttributes.xfer,
ep_desc->bInterval);
return true;
return true;
}
bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
{
(void) rhport;
(void) rhport;
pico_trace("hcd_edpt_xfer dev_addr %d, ep_addr 0x%x, len %d\n", dev_addr, ep_addr, buflen);
uint8_t const ep_num = tu_edpt_number(ep_addr);
tusb_dir_t const ep_dir = tu_edpt_dir(ep_addr);
pico_trace("hcd_edpt_xfer dev_addr %d, ep_addr 0x%x, len %d\n", dev_addr, ep_addr, buflen);
// Get appropriate ep. Either EPX or interrupt endpoint
struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
uint8_t const ep_num = tu_edpt_number(ep_addr);
tusb_dir_t const ep_dir = tu_edpt_dir(ep_addr);
TU_ASSERT(ep);
// Get appropriate ep. Either EPX or interrupt endpoint
struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
// EP should be inactive
assert(!ep->active);
TU_ASSERT(ep);
// Control endpoint can change direction 0x00 <-> 0x80
if ( ep_addr != ep->ep_addr )
{
assert(ep_num == 0);
// EP should be inactive
assert(!ep->active);
// Direction has flipped on endpoint control so re init it but with same properties
_hw_endpoint_init(ep, dev_addr, ep_addr, ep->wMaxPacketSize, ep->transfer_type, 0);
}
// Control endpoint can change direction 0x00 <-> 0x80
if ( ep_addr != ep->ep_addr )
{
assert(ep_num == 0);
// If a normal transfer (non-interrupt) then initiate using
// sie ctrl registers. Otherwise interrupt ep registers should
// already be configured
if (ep == &epx) {
hw_endpoint_xfer_start(ep, buffer, buflen);
// Direction has flipped on endpoint control so re init it but with same properties
_hw_endpoint_init(ep, dev_addr, ep_addr, ep->wMaxPacketSize, ep->transfer_type, 0);
}
// That has set up buffer control, endpoint control etc
// for host we have to initiate the transfer
usb_hw->dev_addr_ctrl = (uint32_t) (dev_addr | (ep_num << USB_ADDR_ENDP_ENDPOINT_LSB));
// If a normal transfer (non-interrupt) then initiate using
// sie ctrl registers. Otherwise interrupt ep registers should
// already be configured
if ( ep == &epx )
{
hw_endpoint_xfer_start(ep, buffer, buflen);
uint32_t flags = USB_SIE_CTRL_START_TRANS_BITS | SIE_CTRL_BASE |
(ep_dir ? USB_SIE_CTRL_RECEIVE_DATA_BITS : USB_SIE_CTRL_SEND_DATA_BITS);
// Set pre if we are a low speed device on full speed hub
flags |= need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0;
// That has set up buffer control, endpoint control etc
// for host we have to initiate the transfer
usb_hw->dev_addr_ctrl = (uint32_t) (dev_addr | (ep_num << USB_ADDR_ENDP_ENDPOINT_LSB));
usb_hw->sie_ctrl = flags;
}else
{
hw_endpoint_xfer_start(ep, buffer, buflen);
}
uint32_t flags = USB_SIE_CTRL_START_TRANS_BITS | SIE_CTRL_BASE |
(ep_dir ? USB_SIE_CTRL_RECEIVE_DATA_BITS : USB_SIE_CTRL_SEND_DATA_BITS) |
(need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0);
usb_hw->sie_ctrl = flags;
}else
{
hw_endpoint_xfer_start(ep, buffer, buflen);
}
return true;
return true;
}
bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
{
(void) rhport;
(void) rhport;
// Copy data into setup packet buffer
for(uint8_t i=0; i<8; i++)
{
usbh_dpram->setup_packet[i] = setup_packet[i];
}
// Copy data into setup packet buffer
for ( uint8_t i = 0; i < 8; i++ )
{
usbh_dpram->setup_packet[i] = setup_packet[i];
}
// Configure EP0 struct with setup info for the trans complete
struct hw_endpoint *ep = _hw_endpoint_allocate(0);
TU_ASSERT(ep);
// Configure EP0 struct with setup info for the trans complete
struct hw_endpoint * ep = _hw_endpoint_allocate(0);
TU_ASSERT(ep);
// EPX should be inactive
assert(!ep->active);
// EPX should be inactive
assert(!ep->active);
// EP0 out
_hw_endpoint_init(ep, dev_addr, 0x00, ep->wMaxPacketSize, 0, 0);
assert(ep->configured);
// EP0 out
_hw_endpoint_init(ep, dev_addr, 0x00, ep->wMaxPacketSize, 0, 0);
assert(ep->configured);
ep->remaining_len = 8;
ep->active = true;
ep->remaining_len = 8;
ep->active = true;
// Set device address
usb_hw->dev_addr_ctrl = dev_addr;
// Set device address
usb_hw->dev_addr_ctrl = dev_addr;
// Set pre if we are a low speed device on full speed hub
uint32_t const flags = SIE_CTRL_BASE | USB_SIE_CTRL_SEND_SETUP_BITS | USB_SIE_CTRL_START_TRANS_BITS |
(need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0);
// Set pre if we are a low speed device on full speed hub
uint32_t const flags = SIE_CTRL_BASE | USB_SIE_CTRL_SEND_SETUP_BITS | USB_SIE_CTRL_START_TRANS_BITS |
(need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0);
usb_hw->sie_ctrl = flags;
usb_hw->sie_ctrl = flags;
return true;
return true;
}
bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
{
(void) dev_addr;
(void) ep_addr;
(void) dev_addr;
(void) ep_addr;
panic("hcd_clear_stall");
return true;
panic("hcd_clear_stall");
return true;
}
#endif

54
src/portable/raspberrypi/rp2040/rp2040_usb.c
View File

@@ -47,6 +47,12 @@ TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_lock_update(__unused struc
static void _hw_endpoint_xfer_sync(struct hw_endpoint *ep);
static void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep);
// if usb hardware is in host mode
TU_ATTR_ALWAYS_INLINE static inline bool is_host_mode(void)
{
return (usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) ? true : false;
}
//--------------------------------------------------------------------+
//
//--------------------------------------------------------------------+
@@ -69,6 +75,8 @@ void rp2040_usb_init(void)
// Mux the controller to the onboard usb phy
usb_hw->muxing = USB_USB_MUXING_TO_PHY_BITS | USB_USB_MUXING_SOFTCON_BITS;
TU_LOG2_INT(sizeof(hw_endpoint_t));
}
void __tusb_irq_path_func(hw_endpoint_reset_transfer)(struct hw_endpoint *ep)
@@ -80,19 +88,23 @@ void __tusb_irq_path_func(hw_endpoint_reset_transfer)(struct hw_endpoint *ep)
}
void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask) {
uint32_t value = 0;
if (and_mask) {
value = *ep->buffer_control & and_mask;
}
if (or_mask) {
value |= or_mask;
if (or_mask & USB_BUF_CTRL_AVAIL) {
if (*ep->buffer_control & USB_BUF_CTRL_AVAIL) {
panic("ep %d %s was already available", tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
}
*ep->buffer_control = value & ~USB_BUF_CTRL_AVAIL;
// 12 cycle delay.. (should be good for 48*12Mhz = 576Mhz)
// Don't need delay in host mode as host is in charge
uint32_t value = 0;
if ( and_mask )
{
value = *ep->buffer_control & and_mask;
}
if ( or_mask )
{
value |= or_mask;
if ( or_mask & USB_BUF_CTRL_AVAIL )
{
if ( *ep->buffer_control & USB_BUF_CTRL_AVAIL )
{
panic("ep %d %s was already available", tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
}
*ep->buffer_control = value & ~USB_BUF_CTRL_AVAIL;
// 12 cycle delay.. (should be good for 48*12Mhz = 576Mhz)
// Don't need delay in host mode as host is in charge
#if !CFG_TUH_ENABLED
__asm volatile (
"b 1f\n"
@@ -104,9 +116,9 @@ void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoi
"1:\n"
: : : "memory");
#endif
}
}
*ep->buffer_control = value;
}
*ep->buffer_control = value;
}
// prepare buffer, return buffer control
@@ -152,12 +164,14 @@ static void __tusb_irq_path_func(_hw_endpoint_start_next_buffer)(struct hw_endpo
// always compute and start with buffer 0
uint32_t buf_ctrl = prepare_ep_buffer(ep, 0) | USB_BUF_CTRL_SEL;
// For now: skip double buffered for Device mode, OUT endpoint since
// For now: skip double buffered for OUT endpoint in Device mode, since
// host could send < 64 bytes and cause short packet on buffer0
// NOTE this could happen to Host mode IN endpoint
// Also, Host mode interrupt endpoint hardware is only single buffered
bool const force_single = (!(usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) && !tu_edpt_dir(ep->ep_addr)) ||
((usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) && tu_edpt_number(ep->ep_addr) != 0);
// NOTE: this could happen to Host mode IN endpoint
// Also, Host mode "interrupt" endpoint hardware is only single buffered,
// NOTE2: Currently Host bulk is implemented using "interrupt" endpoint
bool const is_host = is_host_mode();
bool const force_single = (!is_host && !tu_edpt_dir(ep->ep_addr)) ||
(is_host && tu_edpt_number(ep->ep_addr) != 0);
if(ep->remaining_len && !force_single)
{

42
src/portable/raspberrypi/rp2040/rp2040_usb.h
View File

@@ -82,26 +82,30 @@ void hw_endpoint_reset_transfer(struct hw_endpoint *ep);
void _hw_endpoint_buffer_control_update32(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask);
TU_ATTR_ALWAYS_INLINE static inline uint32_t _hw_endpoint_buffer_control_get_value32(struct hw_endpoint *ep) {
return *ep->buffer_control;
}
TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_value32(struct hw_endpoint *ep, uint32_t value) {
return _hw_endpoint_buffer_control_update32(ep, 0, value);
}
TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_mask32(struct hw_endpoint *ep, uint32_t value) {
return _hw_endpoint_buffer_control_update32(ep, ~value, value);
}
TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_clear_mask32(struct hw_endpoint *ep, uint32_t value) {
return _hw_endpoint_buffer_control_update32(ep, ~value, 0);
}
static inline uintptr_t hw_data_offset(uint8_t *buf)
TU_ATTR_ALWAYS_INLINE static inline uint32_t _hw_endpoint_buffer_control_get_value32 (struct hw_endpoint *ep)
{
// Remove usb base from buffer pointer
return (uintptr_t)buf ^ (uintptr_t)usb_dpram;
return *ep->buffer_control;
}
TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_value32 (struct hw_endpoint *ep, uint32_t value)
{
return _hw_endpoint_buffer_control_update32(ep, 0, value);
}
TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_mask32 (struct hw_endpoint *ep, uint32_t value)
{
return _hw_endpoint_buffer_control_update32(ep, ~value, value);
}
TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_clear_mask32 (struct hw_endpoint *ep, uint32_t value)
{
return _hw_endpoint_buffer_control_update32(ep, ~value, 0);
}
static inline uintptr_t hw_data_offset (uint8_t *buf)
{
// Remove usb base from buffer pointer
return (uintptr_t) buf ^ (uintptr_t) usb_dpram;
}
extern const char *ep_dir_string[];

2
src/portable/renesas/usba/hcd_usba.c
View File

@@ -600,7 +600,7 @@ uint32_t hcd_frame_number(uint8_t rhport)
bool hcd_port_connect_status(uint8_t rhport)
{
(void)rhport;
return USB0.INTSTS1.BIT.ATTCH ? true: false;
return USB0.INTSTS1.BIT.ATTCH ? true : false;
}
void hcd_port_reset(uint8_t rhport)

2
src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
View File

@@ -122,7 +122,7 @@
(TU_CHECK_MCU(OPT_MCU_STM32L4) && defined(STM32L4_FSDEV)) \
)
// In order to reduce the dependance on HAL, we undefine this.
// In order to reduce the dependence on HAL, we undefine this.
// Some definitions are copied to our private include file.
#undef USE_HAL_DRIVER

2
src/portable/sunxi/dcd_sunxi_musb.c
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@@ -243,7 +243,7 @@ static void USBC_Dev_SetAddress(u8 address)
static void __USBC_Dev_Tx_SendStall(void)
{
//send stall, and fifo is flushed automaticly
//send stall, and fifo is flushed automatically
USBC_REG_set_bit_w(USBC_BP_TXCSR_D_SEND_STALL, USBC_REG_TXCSR(USBC0_BASE));
}
static u32 __USBC_Dev_Tx_IsEpStall(void)

2
src/portable/sunxi/musb_def.h
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@@ -93,7 +93,7 @@
#define USBC1_BASE 0x01c14000
#define USBC2_BASE 0x01c1E000
//Some reg whithin musb
//Some reg within musb
#define USBPHY_CLK_REG 0x01c200CC
#define USBPHY_CLK_RST_BIT 0
#define USBPHY_CLK_GAT_BIT 1

11
src/portable/synopsys/dwc2/dcd_dwc2.c
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@@ -529,8 +529,10 @@ void dcd_init (uint8_t rhport)
dwc2->dcfg |= DCFG_NZLSOHSK;
// Clear all interrupts
dwc2->gintsts |= dwc2->gintsts;
dwc2->gotgint |= dwc2->gotgint;
uint32_t int_mask = dwc2->gintsts;
dwc2->gintsts |= int_mask;
int_mask = dwc2->gotgint;
dwc2->gotgint |= int_mask;
// Required as part of core initialization.
// TODO: How should mode mismatch be handled? It will cause
@@ -1003,7 +1005,7 @@ static void handle_rxflvl_irq(uint8_t rhport)
switch ( pktsts )
{
// Global OUT NAK: do nothign
// Global OUT NAK: do nothing
case GRXSTS_PKTSTS_GLOBALOUTNAK: break;
case GRXSTS_PKTSTS_SETUPRX:
@@ -1219,7 +1221,8 @@ void dcd_int_handler(uint8_t rhport)
{
dwc2_regs_t *dwc2 = DWC2_REG(rhport);
uint32_t const int_status = dwc2->gintsts & dwc2->gintmsk;
uint32_t const int_mask = dwc2->gintmsk;
uint32_t const int_status = dwc2->gintsts & int_mask;
if(int_status & GINTSTS_USBRST)
{

6
src/portable/synopsys/dwc2/dwc2_stm32.h
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@@ -116,19 +116,19 @@ static const dwc2_controller_t _dwc2_controller[] =
//
//--------------------------------------------------------------------+
// SystemCoreClock is alrady included by family header
// SystemCoreClock is already included by family header
// extern uint32_t SystemCoreClock;
TU_ATTR_ALWAYS_INLINE
static inline void dwc2_dcd_int_enable(uint8_t rhport)
{
NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum);
NVIC_EnableIRQ((IRQn_Type)_dwc2_controller[rhport].irqnum);
}
TU_ATTR_ALWAYS_INLINE
static inline void dwc2_dcd_int_disable (uint8_t rhport)
{
NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum);
NVIC_DisableIRQ((IRQn_Type)_dwc2_controller[rhport].irqnum);
}
TU_ATTR_ALWAYS_INLINE

2
src/portable/valentyusb/eptri/dcd_eptri.c
View File

@@ -465,7 +465,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
enable = 1;
usb_out_ctrl_write((0 << CSR_USB_OUT_CTRL_STALL_OFFSET) | (enable << CSR_USB_OUT_CTRL_ENABLE_OFFSET) | tu_edpt_number(ep_addr));
}
// IN endpoints will get unstalled when more data is written.
// IN endpoints will get un-stalled when more data is written.
}
bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)

345
src/portable/wch/ch32v307/ch32_usbhs_reg.h Normal file
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@@ -0,0 +1,345 @@
#ifndef _USB_CH32_USBHS_REG_H
#define _USB_CH32_USBHS_REG_H
#include <ch32v30x.h>
/******************* GLOBAL ******************/
// USB CONTROL
#define USBHS_CONTROL_OFFSET 0x00
#define USBHS_DMA_EN (1 << 0)
#define USBHS_ALL_CLR (1 << 1)
#define USBHS_FORCE_RST (1 << 2)
#define USBHS_INT_BUSY_EN (1 << 3)
#define USBHS_DEV_PU_EN (1 << 4)
#define USBHS_SPEED_MASK (3 << 5)
#define USBHS_FULL_SPEED (0 << 5)
#define USBHS_HIGH_SPEED (1 << 5)
#define USBHS_LOW_SPEED (2 << 5)
#define USBHS_HOST_MODE (1 << 7)
// USB_INT_EN
#define USBHS_INT_EN_OFFSET 0x02
#define USBHS_BUS_RST_EN (1 << 0)
#define USBHS_DETECT_EN (1 << 0)
#define USBHS_TRANSFER_EN (1 << 1)
#define USBHS_SUSPEND_EN (1 << 2)
#define USBHS_SOF_ACT_EN (1 << 3)
#define USBHS_FIFO_OV_EN (1 << 4)
#define USBHS_SETUP_ACT_EN (1 << 5)
#define USBHS_ISO_ACT_EN (1 << 6)
#define USBHS_DEV_NAK_EN (1 << 7)
// USB DEV AD
#define USBHS_DEV_AD_OFFSET 0x03
// USB FRAME_NO
#define USBHS_FRAME_NO_OFFSET 0x04
// USB SUSPEND
#define USBHS_SUSPEND_OFFSET 0x06
#define USBHS_DEV_REMOTE_WAKEUP (1 << 2)
#define USBHS_LINESTATE_MASK (2 << 4) /* Read Only */
// RESERVED0
// USB SPEED TYPE
#define USBHS_SPEED_TYPE_OFFSET 0x08
#define USBSPEED_MASK (0x03)
// USB_MIS_ST
#define USBHS_MIS_ST_OFFSET 0x09
#define USBHS_SPLIT_CAN (1 << 0)
#define USBHS_ATTACH (1 << 1)
#define USBHS_SUSPEND (1 << 2)
#define USBHS_BUS_RESET (1 << 3)
#define USBHS_R_FIFO_RDY (1 << 4)
#define USBHS_SIE_FREE (1 << 5)
#define USBHS_SOF_ACT (1 << 6)
#define USBHS_SOF_PRES (1 << 7)
// INT_FLAG
#define USBHS_INT_FLAG_OFFSET 0x0A
#define USBHS_BUS_RST_FLAG (1 << 0)
#define USBHS_DETECT_FLAG (1 << 0)
#define USBHS_TRANSFER_FLAG (1 << 1)
#define USBHS_SUSPEND_FLAG (1 << 2)
#define USBHS_HST_SOF_FLAG (1 << 3)
#define USBHS_FIFO_OV_FLAG (1 << 4)
#define USBHS_SETUP_FLAG (1 << 5)
#define USBHS_ISO_ACT_FLAG (1 << 6)
// INT_ST
#define USBHS_INT_ST_OFFSET 0x0B
#define USBHS_DEV_UIS_IS_NAK (1 << 7)
#define USBHS_DEV_UIS_TOG_OK (1 << 6)
#define MASK_UIS_TOKEN (3 << 4)
#define MASK_UIS_ENDP (0x0F)
#define MASK_UIS_H_RES (0x0F)
#define USBHS_TOGGLE_OK (0x40)
#define USBHS_HOST_RES (0x0f)
//USB_RX_LEN
#define USBHS_RX_LEN_OFFSET 0x0C
/******************* DEVICE ******************/
//UEP_CONFIG
#define USBHS_UEP_CONFIG_OFFSET 0x10
#define USBHS_EP0_T_EN (1 << 0)
#define USBHS_EP0_R_EN (1 << 16)
#define USBHS_EP1_T_EN (1 << 1)
#define USBHS_EP1_R_EN (1 << 17)
#define USBHS_EP2_T_EN (1 << 2)
#define USBHS_EP2_R_EN (1 << 18)
#define USBHS_EP3_T_EN (1 << 3)
#define USBHS_EP3_R_EN (1 << 19)
#define USBHS_EP4_T_EN (1 << 4)
#define USBHS_EP4_R_EN (1 << 20)
#define USBHS_EP5_T_EN (1 << 5)
#define USBHS_EP5_R_EN (1 << 21)
#define USBHS_EP6_T_EN (1 << 6)
#define USBHS_EP6_R_EN (1 << 22)
#define USBHS_EP7_T_EN (1 << 7)
#define USBHS_EP7_R_EN (1 << 23)
#define USBHS_EP8_T_EN (1 << 8)
#define USBHS_EP8_R_EN (1 << 24)
#define USBHS_EP9_T_EN (1 << 9)
#define USBHS_EP9_R_EN (1 << 25)
#define USBHS_EP10_T_EN (1 << 10)
#define USBHS_EP10_R_EN (1 << 26)
#define USBHS_EP11_T_EN (1 << 11)
#define USBHS_EP11_R_EN (1 << 27)
#define USBHS_EP12_T_EN (1 << 12)
#define USBHS_EP12_R_EN (1 << 28)
#define USBHS_EP13_T_EN (1 << 13)
#define USBHS_EP13_R_EN (1 << 29)
#define USBHS_EP14_T_EN (1 << 14)
#define USBHS_EP14_R_EN (1 << 30)
#define USBHS_EP15_T_EN (1 << 15)
#define USBHS_EP15_R_EN (1 << 31)
//UEP_TYPE
#define USBHS_UEP_TYPE_OFFSET 0x14
#define USBHS_EP0_T_TYP (1 << 0)
#define USBHS_EP0_R_TYP (1 << 16)
#define USBHS_EP1_T_TYP (1 << 1)
#define USBHS_EP1_R_TYP (1 << 17)
#define USBHS_EP2_T_TYP (1 << 2)
#define USBHS_EP2_R_TYP (1 << 18)
#define USBHS_EP3_T_TYP (1 << 3)
#define USBHS_EP3_R_TYP (1 << 19)
#define USBHS_EP4_T_TYP (1 << 4)
#define USBHS_EP4_R_TYP (1 << 20)
#define USBHS_EP5_T_TYP (1 << 5)
#define USBHS_EP5_R_TYP (1 << 21)
#define USBHS_EP6_T_TYP (1 << 6)
#define USBHS_EP6_R_TYP (1 << 22)
#define USBHS_EP7_T_TYP (1 << 7)
#define USBHS_EP7_R_TYP (1 << 23)
#define USBHS_EP8_T_TYP (1 << 8)
#define USBHS_EP8_R_TYP (1 << 24)
#define USBHS_EP9_T_TYP (1 << 8)
#define USBHS_EP9_R_TYP (1 << 25)
#define USBHS_EP10_T_TYP (1 << 10)
#define USBHS_EP10_R_TYP (1 << 26)
#define USBHS_EP11_T_TYP (1 << 11)
#define USBHS_EP11_R_TYP (1 << 27)
#define USBHS_EP12_T_TYP (1 << 12)
#define USBHS_EP12_R_TYP (1 << 28)
#define USBHS_EP13_T_TYP (1 << 13)
#define USBHS_EP13_R_TYP (1 << 29)
#define USBHS_EP14_T_TYP (1 << 14)
#define USBHS_EP14_R_TYP (1 << 30)
#define USBHS_EP15_T_TYP (1 << 15)
#define USBHS_EP15_R_TYP (1 << 31)
/* BUF_MOD UEP1~15 */
#define USBHS_BUF_MOD_OFFSET 0x18
#define USBHS_EP0_BUF_MOD (1 << 0)
#define USBHS_EP0_ISO_BUF_MOD (1 << 16)
#define USBHS_EP1_BUF_MOD (1 << 1)
#define USBHS_EP1_ISO_BUF_MOD (1 << 17)
#define USBHS_EP2_BUF_MOD (1 << 2)
#define USBHS_EP2_ISO_BUF_MOD (1 << 18)
#define USBHS_EP3_BUF_MOD (1 << 3)
#define USBHS_EP3_ISO_BUF_MOD (1 << 19)
#define USBHS_EP4_BUF_MOD (1 << 4)
#define USBHS_EP4_ISO_BUF_MOD (1 << 20)
#define USBHS_EP5_BUF_MOD (1 << 5)
#define USBHS_EP5_ISO_BUF_MOD (1 << 21)
#define USBHS_EP6_BUF_MOD (1 << 6)
#define USBHS_EP6_ISO_BUF_MOD (1 << 22)
#define USBHS_EP7_BUF_MOD (1 << 7)
#define USBHS_EP7_ISO_BUF_MOD (1 << 23)
#define USBHS_EP8_BUF_MOD (1 << 8)
#define USBHS_EP8_ISO_BUF_MOD (1 << 24)
#define USBHS_EP9_BUF_MOD (1 << 9)
#define USBHS_EP9_ISO_BUF_MOD (1 << 25)
#define USBHS_EP10_BUF_MOD (1 << 10)
#define USBHS_EP10_ISO_BUF_MOD (1 << 26)
#define USBHS_EP11_BUF_MOD (1 << 11)
#define USBHS_EP11_ISO_BUF_MOD (1 << 27)
#define USBHS_EP12_BUF_MOD (1 << 12)
#define USBHS_EP12_ISO_BUF_MOD (1 << 28)
#define USBHS_EP13_BUF_MOD (1 << 13)
#define USBHS_EP13_ISO_BUF_MOD (1 << 29)
#define USBHS_EP14_BUF_MOD (1 << 14)
#define USBHS_EP14_ISO_BUF_MOD (1 << 30)
#define USBHS_EP15_BUF_MOD (1 << 15)
#define USBHS_EP15_ISO_BUF_MOD (1 << 31)
//USBHS_EPn_T_EN USBHS_EPn_R_EN USBHS_EPn_BUF_MOD Description: Arrange from low to high with UEPn_DMA as the starting address
// 0 0 x The endpoint is disabled and the UEPn_*_DMA buffers are not used.
// 1 0 0 The first address of the receive (OUT) buffer is UEPn_RX_DMA
// 1 0 1 RB_UEPn_RX_TOG[0]=0, use buffer UEPn_RX_DMA RB_UEPn_RX_TOG[0]=1, use buffer UEPn_TX_DMA
// 0 1 0 The first address of the transmit (IN) buffer is UEPn_TX_DMA.
// 0 1 1 RB_UEPn_TX_TOG[0]=0, use buffer UEPn_TX_DMA RB_UEPn_TX_TOG[0]=1, use buffer UEPn_RX_DMA
/* USB0_DMA */
#define USBHS_UEP0_DMA_OFFSET(n) (0x1C) // endpoint 0 DMA buffer address
/* USBX_RX_DMA */
#define USBHS_UEPx_RX_DMA_OFFSET(n) (0x1C + 4 * (n)) // endpoint x DMA buffer address
#define USBHS_UEPx_TX_DMA_OFFSET(n) (0x58 + 4 * (n)) // endpoint x DMA buffer address
#define USBHS_UEPx_MAX_LEN_OFFSET(n) (0x98 + 4 * (n)) // endpoint x DMA buffer address
#define USBHS_UEPx_T_LEN_OFFSET(n) (0xD8 + 4 * (n)) // endpoint x DMA buffer address
#define USBHS_UEPx_TX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 2) // endpoint x DMA buffer address
#define USBHS_UEPx_RX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 3) // endpoint x DMA buffer address
// UEPn_T_LEN
#define USBHS_EP_T_LEN_MASK (0x7FF)
//UEPn_TX_CTRL
#define USBHS_EP_T_RES_MASK (3 << 0)
#define USBHS_EP_T_RES_ACK (0 << 0)
#define USBHS_EP_T_RES_NYET (1 << 0)
#define USBHS_EP_T_RES_NAK (2 << 0)
#define USBHS_EP_T_RES_STALL (3 << 0)
#define USBHS_EP_T_TOG_MASK (3 << 3)
#define USBHS_EP_T_TOG_0 (0 << 3)
#define USBHS_EP_T_TOG_1 (1 << 3)
#define USBHS_EP_T_TOG_2 (2 << 3)
#define USBHS_EP_T_TOG_M (3 << 3)
#define USBHS_EP_T_AUTOTOG (1 << 5)
//UEPn_RX_CTRL
#define USBHS_EP_R_RES_MASK (3 << 0)
#define USBHS_EP_R_RES_ACK (0 << 0)
#define USBHS_EP_R_RES_NYET (1 << 0)
#define USBHS_EP_R_RES_NAK (2 << 0)
#define USBHS_EP_R_RES_STALL (3 << 0)
#define USBHS_EP_R_TOG_MASK (3 << 3)
#define USBHS_EP_R_TOG_0 (0 << 3)
#define USBHS_EP_R_TOG_1 (1 << 3)
#define USBHS_EP_R_TOG_2 (2 << 3)
#define USBHS_EP_R_TOG_M (3 << 3)
#define USBHS_EP_R_AUTOTOG (1 << 5)
#define USBHS_TOG_MATCH (1 << 6)
/******************* HOST ******************/
// USB HOST_CTRL
#define USBHS_SEND_BUS_RESET (1 << 0)
#define USBHS_SEND_BUS_SUSPEND (1 << 1)
#define USBHS_SEND_BUS_RESUME (1 << 2)
#define USBHS_REMOTE_WAKE (1 << 3)
#define USBHS_PHY_SUSPENDM (1 << 4)
#define USBHS_UH_SOFT_FREE (1 << 6)
#define USBHS_SEND_SOF_EN (1 << 7)
//UH_CONFIG
#define USBHS_HOST_TX_EN (1 << 3)
#define USBHS_HOST_RX_EN (1 << 18)
// HOST_EP_TYPE
#define USBHS_ENDP_TX_ISO (1 << 3)
#define USBHS_ENDP_RX_ISO (1 << (16 + 2))
// R32_UH_EP_PID
#define USBHS_HOST_MASK_TOKEN (0x0f)
#define USBHS_HOST_MASK_ENDP (0x0f << 4)
//R8_UH_RX_CTRL
#define USBHS_EP_R_RES_MASK (3 << 0)
#define USBHS_EP_R_RES_ACK (0 << 0)
#define USBHS_EP_R_RES_NYET (1 << 0)
#define USBHS_EP_R_RES_NAK (2 << 0)
#define USBHS_EP_R_RES_STALL (3 << 0)
#define USBHS_UH_R_RES_NO (1 << 2)
#define USBHS_UH_R_TOG_1 (1 << 3)
#define USBHS_UH_R_TOG_2 (2 << 3)
#define USBHS_UH_R_TOG_3 (3 << 3)
#define USBHS_UH_R_TOG_AUTO (1 << 5)
#define USBHS_UH_R_DATA_NO (1 << 6)
//R8_UH_TX_CTRL
#define USBHS_UH_T_RES_MASK (3 << 0)
#define USBHS_UH_T_RES_ACK (0 << 0)
#define USBHS_UH_T_RES_NYET (1 << 0)
#define USBHS_UH_T_RES_NAK (2 << 0)
#define USBHS_UH_T_RES_STALL (3 << 0)
#define USBHS_UH_T_RES_NO (1 << 2)
#define USBHS_UH_T_TOG_1 (1 << 3)
#define USBHS_UH_T_TOG_2 (2 << 3)
#define USBHS_UH_T_TOG_3 (3 << 3)
#define USBHS_UH_T_TOG_AUTO (1 << 5)
#define USBHS_UH_T_DATA_NO (1 << 6)
// 00: OUT, 01:SOF, 10:IN, 11:SETUP
#define PID_OUT 0
#define PID_SOF 1
#define PID_IN 2
#define PID_SETUP 3
#endif

391
src/portable/wch/ch32v307/dcd_usbhs.c Normal file
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@@ -0,0 +1,391 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2022 Greg Davill
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#include "tusb_option.h"
#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_CH32V307)
#include "device/dcd.h"
#include "ch32_usbhs_reg.h"
#include "core_riscv.h"
// Max number of bi-directional endpoints including EP0
#define EP_MAX 16
typedef struct {
uint8_t *buffer;
// tu_fifo_t * ff; // TODO support dcd_edpt_xfer_fifo API
uint16_t total_len;
uint16_t queued_len;
uint16_t max_size;
bool short_packet;
} xfer_ctl_t;
#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
static xfer_ctl_t xfer_status[EP_MAX][2];
#define EP_TX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_TX_LEN) + (ep)*2)
#define EP_TX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_TX_CTRL) + (ep)*4)
#define EP_RX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_RX_CTRL) + (ep)*4)
#define EP_RX_MAX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_MAX_LEN) + (ep)*2)
#define EP_TX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_TX_DMA) + (ep - 1))
#define EP_RX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_RX_DMA) + (ep - 1))
/* Endpoint Buffer */
TU_ATTR_ALIGNED(4) uint8_t EP0_DatabufHD[64]; // ep0(64)
volatile uint8_t USBHS_Dev_Endp0_Tog = 0x01;
void dcd_init(uint8_t rhport) {
(void)rhport;
memset(&xfer_status, 0, sizeof(xfer_status));
USBHSD->HOST_CTRL = 0x00;
USBHSD->HOST_CTRL = USBHS_PHY_SUSPENDM;
USBHSD->CONTROL = 0;
#if TUD_OPT_HIGH_SPEED
USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_HIGH_SPEED;
#else
#error OPT_MODE_FULL_SPEED not currently supported on CH32V307
USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_FULL_SPEED;
#endif
USBHSD->INT_EN = 0;
USBHSD->INT_EN = USBHS_SETUP_ACT_EN | USBHS_TRANSFER_EN | USBHS_DETECT_EN | USBHS_SUSPEND_EN;
/* ALL endpoint enable */
USBHSD->ENDP_CONFIG = 0xffffffff;
USBHSD->ENDP_CONFIG = USBHS_EP0_T_EN | USBHS_EP0_R_EN;
USBHSD->ENDP_TYPE = 0x00;
USBHSD->BUF_MODE = 0x00;
USBHSD->UEP0_MAX_LEN = 64;
USBHSD->UEP0_DMA = (uint32_t)EP0_DatabufHD;
USBHSD->UEP0_TX_LEN = 0;
USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_NAK;
USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK;
for (int ep = 1; ep < EP_MAX; ep++) {
EP_TX_LEN(ep) = 0;
EP_TX_CTRL(ep) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK;
EP_RX_CTRL(ep) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK;
EP_RX_MAX_LEN(ep) = 512;
}
USBHSD->DEV_AD = 0;
USBHSD->CONTROL |= USBHS_DEV_PU_EN;
}
void dcd_int_enable(uint8_t rhport) {
(void)rhport;
NVIC_EnableIRQ(USBHS_IRQn);
}
void dcd_int_disable(uint8_t rhport) {
(void)rhport;
NVIC_DisableIRQ(USBHS_IRQn);
}
void dcd_edpt_close_all(uint8_t rhport) {
(void)rhport;
}
void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
(void)dev_addr;
// Response with zlp status
dcd_edpt_xfer(rhport, 0x80, NULL, 0);
}
void dcd_remote_wakeup(uint8_t rhport)
{
(void) rhport;
}
void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) {
(void)rhport;
if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
request->bRequest == TUSB_REQ_SET_ADDRESS) {
USBHSD->DEV_AD = (uint8_t)request->wValue;
}
EP_TX_CTRL(0) = USBHS_EP_T_RES_NAK;
EP_RX_CTRL(0) = USBHS_EP_R_RES_ACK;
}
bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) {
(void)rhport;
uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
TU_ASSERT(epnum < EP_MAX);
xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
xfer->max_size = tu_edpt_packet_size(desc_edpt);
if (epnum != 0) {
if (tu_edpt_dir(desc_edpt->bEndpointAddress) == TUSB_DIR_OUT) {
EP_RX_CTRL(epnum) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_ACK;
} else {
EP_TX_LEN(epnum) = 0;
EP_TX_CTRL(epnum) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0;
}
}
return true;
}
int usbd_ep_close(const uint8_t ep) {
(void)ep;
return 0;
}
void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
(void)rhport;
uint8_t const epnum = tu_edpt_number(ep_addr);
uint8_t const dir = tu_edpt_dir(ep_addr);
if (epnum == 0) {
if (dir == TUSB_DIR_OUT) {
USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_STALL;
} else {
USBHSD->UEP0_TX_LEN = 0;
USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_STALL;
}
} else {
if (dir == TUSB_DIR_OUT) {
EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~USBHS_EP_R_RES_MASK) | USBHS_EP_R_RES_STALL;
} else {
EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~USBHS_EP_T_RES_MASK) | USBHS_EP_T_RES_STALL;
}
}
}
void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
(void)rhport;
uint8_t const epnum = tu_edpt_number(ep_addr);
uint8_t const dir = tu_edpt_dir(ep_addr);
if (epnum == 0) {
if (dir == TUSB_DIR_OUT) {
USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK;
} else {
}
} else {
if (dir == TUSB_DIR_OUT) {
EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~(USBHS_EP_R_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_ACK;
} else {
EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_NAK;
}
}
}
bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) {
(void)rhport;
uint8_t const epnum = tu_edpt_number(ep_addr);
uint8_t const dir = tu_edpt_dir(ep_addr);
xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
xfer->buffer = buffer;
// xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API
xfer->total_len = total_bytes;
xfer->queued_len = 0;
xfer->short_packet = false;
// uint16_t num_packets = (total_bytes / xfer->max_size);
uint16_t short_packet_size = total_bytes % (xfer->max_size + 1);
// Zero-size packet is special case.
if (short_packet_size == 0 || (total_bytes == 0)) {
xfer->short_packet = true;
}
if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) {
if (!total_bytes) {
xfer->short_packet = true;
if (epnum == 0) {
USBHSD->UEP0_TX_LEN = 0;
USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0);
USBHS_Dev_Endp0_Tog ^= 1;
} else {
EP_TX_LEN(epnum) = 0;
EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK;
}
} else {
if (epnum == 0) {
xfer->queued_len += short_packet_size;
memcpy(&EP0_DatabufHD[0], buffer, short_packet_size);
USBHSD->UEP0_TX_LEN = short_packet_size;
USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0);
USBHS_Dev_Endp0_Tog ^= 1;
} else {
xfer->queued_len += short_packet_size;
EP_TX_DMA_ADDR(epnum) = (uint32_t)buffer;
USBHSD->ENDP_CONFIG |= (USBHS_EP0_T_EN << epnum);
EP_TX_LEN(epnum) = short_packet_size;
EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK;
}
}
} else { /* TUSB_DIR_OUT */
if (epnum == 0) {
uint32_t read_count = USBHSD->RX_LEN;
read_count = TU_MIN(read_count, total_bytes);
if ((total_bytes == 8)) {
read_count = 8;
memcpy(buffer, &EP0_DatabufHD[0], 8);
} else {
memcpy(buffer, &EP0_DatabufHD[0], read_count);
}
} else {
EP_RX_DMA_ADDR(epnum) = (uint32_t)xfer->buffer;
USBHSD->ENDP_CONFIG |= (USBHS_EP0_R_EN << epnum);
}
// usbd_ep_read(ep_addr, buffer, total_bytes, &ret_bytes);
}
return true;
}
static void receive_packet(xfer_ctl_t *xfer, uint16_t xfer_size) {
// xfer->queued_len = xfer->total_len - remaining;
uint16_t remaining = xfer->total_len - xfer->queued_len;
uint16_t to_recv_size;
if (remaining <= xfer->max_size) {
// Avoid buffer overflow.
to_recv_size = (xfer_size > remaining) ? remaining : xfer_size;
} else {
// Room for full packet, choose recv_size based on what the microcontroller
// claims.
to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size;
}
if (to_recv_size) {
}
xfer->queued_len += xfer_size;
// Per USB spec, a short OUT packet (including length 0) is always
// indicative of the end of a transfer (at least for ctl, bulk, int).
xfer->short_packet = (xfer_size < xfer->max_size);
}
void dcd_int_handler(uint8_t rhport) {
(void)rhport;
uint32_t end_num, rx_token;
uint8_t intflag = 0;
intflag = USBHSD->INT_FG;
if (intflag & USBHS_TRANSFER_FLAG) {
end_num = (USBHSD->INT_ST) & MASK_UIS_ENDP;
rx_token = (((USBHSD->INT_ST) & MASK_UIS_TOKEN) >> 4) & 0x03;
uint8_t endp = end_num | (rx_token == PID_IN ? TUSB_DIR_IN_MASK : 0);
xfer_ctl_t *xfer = XFER_CTL_BASE(end_num, tu_edpt_dir(endp));
if (rx_token == PID_OUT) {
uint16_t rx_len = USBHSD->RX_LEN;
receive_packet(xfer, rx_len);
if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) {
xfer->short_packet = false;
dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true);
}
if (end_num == 0) {
USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0;
}
} else if (rx_token == PID_IN) {
if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) {
xfer->short_packet = false;
xfer->total_len = 0;
dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true);
EP_TX_CTRL(end_num) = (EP_TX_CTRL(end_num) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_NAK;
if (end_num == 0) {
}
} else {
dcd_edpt_xfer(0, endp, xfer->buffer + xfer->queued_len, xfer->total_len - xfer->queued_len);
}
}
USBHSD->INT_FG = USBHS_TRANSFER_FLAG; /* Clear flag */
} else if (intflag & USBHS_SETUP_FLAG) {
USBHS_Dev_Endp0_Tog = 1;
dcd_event_setup_received(0, EP0_DatabufHD, true);
USBHSD->INT_FG = USBHS_SETUP_FLAG; /* Clear flag */
} else if (intflag & USBHS_DETECT_FLAG) {
USBHS_Dev_Endp0_Tog = 1;
xfer_status[0][TUSB_DIR_OUT].max_size = 64;
xfer_status[0][TUSB_DIR_IN].max_size = 64;
dcd_event_bus_reset(0, TUSB_SPEED_HIGH, true);
USBHSD->DEV_AD = 0;
USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0;
USBHSD->INT_FG = USBHS_DETECT_FLAG; /* Clear flag */
} else if (intflag & USBHS_SUSPEND_FLAG) {
dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SUSPEND };
dcd_event_handler(&event, true);
USBHSD->INT_FG = USBHS_SUSPEND_FLAG; /* Clear flag */
}
}
#endif