update segger rtt to fix cast align

hw/bsp/mcx/boards/mcxn947brk/board.cmake

@@ -10,6 +10,7 @@ function(update_board TARGET)
     CPU_MCXN947VDF_cm33_core0
     # port 1 is highspeed
     BOARD_TUD_RHPORT=1
+    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
     )
   target_sources(${TARGET} PUBLIC
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c

hw/bsp/mcx/boards/mcxn947brk/board.mk

@@ -4,8 +4,8 @@ PORT ?= 1
 
 CFLAGS += -DCPU_MCXN947VDF_cm33_core0
 
-JLINK_DEVICE = LPC55S69
-PYOCD_TARGET = LPC55S69
+JLINK_DEVICE = MCXN947_M33_0
+PYOCD_TARGET = MCXN947
 
 # flash using pyocd
-flash: flash-pyocd
+flash: flash-jlink

hw/bsp/mcx/family.cmake

@@ -14,7 +14,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
 set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
-set(FAMILY_MCUS LPC55XX CACHE INTERNAL "")
+set(FAMILY_MCUS MCXN9 CACHE INTERNAL "")
 
 # enable LTO if supported
 include(CheckIPOSupported)