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Merge pull request #3043 from hathach/hcd-close-ep

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feat(host) add endpoint close API and feat(HIL) improvement
This commit is contained in:
Ha Thach
2025-03-27 10:47:10 +07:00
committed by GitHub
parent cf76af1056 5531de4f2c
commit 8c1802e41d
56 changed files with 1166 additions and 900 deletions
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14
.idea/debugServers/rp2040.xml generated Normal file
View File

@@ -0,0 +1,14 @@
<component name="DebugServers">
<generic-debug-target name="rp2040" uniqueID="006ce655-8571-401e-a94b-6a4f6d519724">
<debugger version="1">
<debugger kind="GDB" isBundled="true" />
<env />
</debugger>
<gdbserver exe="/usr/local/bin/openocd" args="-f interface/cmsis-dap.cfg -f target/rp2040.cfg -c &quot;adapter speed 5000&quot;">
<env />
</gdbserver>
<console enabled="true" port="4444" />
<target download-type="UPDATED_ONLY" reset-before="false" />
<connection extended-remote="false" remote-string="tcp::3333" warmup-ms="500" />
</generic-debug-target>
</component>

14
.idea/debugServers/rp2350.xml generated Normal file
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@@ -0,0 +1,14 @@
<component name="DebugServers">
<generic-debug-target name="rp2350" uniqueID="939fdf16-9c30-4261-8435-3e8df7fd5800" selected="true">
<debugger version="1">
<debugger kind="GDB" isBundled="true" />
<env />
</debugger>
<gdbserver exe="/usr/local/bin/openocd" args="-f interface/cmsis-dap.cfg -f target/rp2350.cfg -c &quot;adapter speed 5000&quot;">
<env />
</gdbserver>
<console enabled="true" port="4444" />
<target download-type="UPDATED_ONLY" reset-before="false" />
<connection extended-remote="false" remote-string="tcp::3333" warmup-ms="500" />
</generic-debug-target>
</component>

13
.idea/debugServers/rt1060.xml generated Normal file
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@@ -0,0 +1,13 @@
<component name="DebugServers">
<jlink-debug-target name="rt1060" uniqueID="851396c6-2030-4694-b86d-21ba9547ddcb">
<debugger version="1">
<debugger kind="GDB" isBundled="true" />
<env />
</debugger>
<gdbserver exe="/usr/bin/JLinkGDBServerCLExe" />
<console port="2334" type="RTT" />
<target device="MIMXRT1062xxx6A" reset-before="false" />
<connection extended-remote="false" port="4444" warmup-ms="500" />
<swo />
</jlink-debug-target>
</component>

13
.idea/debugServers/rt1064.xml generated Normal file
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@@ -0,0 +1,13 @@
<component name="DebugServers">
<jlink-debug-target name="rt1064" uniqueID="9602472b-6ce8-4a2d-9636-1c03b5fcd6da">
<debugger version="1">
<debugger kind="GDB" isBundled="true" />
<env />
</debugger>
<gdbserver exe="/usr/bin/JLinkGDBServerCLExe" />
<console port="2334" type="RTT" />
<target device="MIMXRT1064xxx6A" reset-before="false" />
<connection extended-remote="false" port="4444" warmup-ms="500" />
<swo />
</jlink-debug-target>
</component>

13
.idea/debugServers/sam21.xml generated Normal file
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@@ -0,0 +1,13 @@
<component name="DebugServers">
<jlink-debug-target name="sam21" uniqueID="b22537b6-0924-4a2b-8721-48a8952239de">
<debugger version="1">
<debugger kind="GDB" isBundled="true" />
<env />
</debugger>
<gdbserver exe="/usr/bin/JLinkGDBServerCLExe" />
<console port="2334" type="RTT" />
<target device="ATSAMD21G18A" reset-before="false" />
<connection extended-remote="false" port="4444" warmup-ms="500" />
<swo />
</jlink-debug-target>
</component>

13
.idea/debugServers/sam51.xml generated Normal file
View File

@@ -0,0 +1,13 @@
<component name="DebugServers">
<jlink-debug-target name="sam51" uniqueID="481ff0d4-6501-4394-8b6b-f7a2ca4c2675">
<debugger version="1">
<debugger kind="GDB" isBundled="true" />
<env />
</debugger>
<gdbserver exe="/usr/bin/JLinkGDBServerCLExe" />
<console port="2334" type="RTT" />
<target device="ATSAMD51J19A" reset-before="false" />
<connection extended-remote="false" port="4444" warmup-ms="500" />
<swo />
</jlink-debug-target>
</component>

164
examples/dual/host_info_to_device_cdc/src/main.c
View File

@@ -70,8 +70,11 @@ enum {
static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
static bool is_print[CFG_TUH_DEVICE_MAX+1] = { 0 };
static tusb_desc_device_t descriptor_device[CFG_TUH_DEVICE_MAX+1];
static void print_utf16(uint16_t *temp_buf, size_t buf_len);
static void print_device_info(uint8_t daddr, const tusb_desc_device_t* desc_device);
void led_blinking_task(void);
void cdc_task(void);
@@ -135,84 +138,20 @@ void tud_resume_cb(void) {
blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
}
#if 1
#define cdc_printf(...) \
do { \
char _tempbuf[256]; \
int count = sprintf(_tempbuf, __VA_ARGS__); \
tud_cdc_write(_tempbuf, (uint32_t) count); \
tud_cdc_write_flush(); \
tud_task(); \
} while(0)
#endif
//#define cdc_printf printf
void print_device_info(uint8_t daddr) {
tusb_desc_device_t desc_device;
uint8_t xfer_result = tuh_descriptor_get_device_sync(daddr, &desc_device, 18);
if (XFER_RESULT_SUCCESS != xfer_result) {
tud_cdc_write_str("Failed to get device descriptor\r\n");
void cdc_task(void) {
if (!tud_cdc_connected()) {
// delay a bit otherwise we can outpace host's terminal. Linux will set LineState (DTR) then Line Coding.
// If we send data before Linux's terminal set Line Coding, it can be ignored --> missing data with hardware test loop
board_delay(20);
return;
}
// Get String descriptor using Sync API
uint16_t serial[64];
uint16_t buf[128];
cdc_printf("Device %u: ID %04x:%04x SN ", daddr, desc_device.idVendor, desc_device.idProduct);
xfer_result = tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, serial, sizeof(serial));
if (XFER_RESULT_SUCCESS != xfer_result) {
serial[0] = 'n';
serial[1] = '/';
serial[2] = 'a';
serial[3] = 0;
}
print_utf16(serial, TU_ARRAY_SIZE(serial));
tud_cdc_write_str("\r\n");
cdc_printf("Device Descriptor:\r\n");
cdc_printf(" bLength %u\r\n" , desc_device.bLength);
cdc_printf(" bDescriptorType %u\r\n" , desc_device.bDescriptorType);
cdc_printf(" bcdUSB %04x\r\n" , desc_device.bcdUSB);
cdc_printf(" bDeviceClass %u\r\n" , desc_device.bDeviceClass);
cdc_printf(" bDeviceSubClass %u\r\n" , desc_device.bDeviceSubClass);
cdc_printf(" bDeviceProtocol %u\r\n" , desc_device.bDeviceProtocol);
cdc_printf(" bMaxPacketSize0 %u\r\n" , desc_device.bMaxPacketSize0);
cdc_printf(" idVendor 0x%04x\r\n" , desc_device.idVendor);
cdc_printf(" idProduct 0x%04x\r\n" , desc_device.idProduct);
cdc_printf(" bcdDevice %04x\r\n" , desc_device.bcdDevice);
cdc_printf(" iManufacturer %u " , desc_device.iManufacturer);
xfer_result = tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, buf, sizeof(buf));
if (XFER_RESULT_SUCCESS == xfer_result ) {
print_utf16(buf, TU_ARRAY_SIZE(buf));
}
tud_cdc_write_str("\r\n");
cdc_printf(" iProduct %u " , desc_device.iProduct);
xfer_result = tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, buf, sizeof(buf));
if (XFER_RESULT_SUCCESS == xfer_result) {
print_utf16(buf, TU_ARRAY_SIZE(buf));
}
tud_cdc_write_str("\r\n");
cdc_printf(" iSerialNumber %u " , desc_device.iSerialNumber);
tud_cdc_write_str((char*)serial); // serial is already to UTF-8
tud_cdc_write_str("\r\n");
cdc_printf(" bNumConfigurations %u\r\n" , desc_device.bNumConfigurations);
}
void cdc_task(void) {
if (tud_cdc_connected()) {
for (uint8_t daddr = 1; daddr <= CFG_TUH_DEVICE_MAX; daddr++) {
if (tuh_mounted(daddr)) {
if (is_print[daddr]) {
is_print[daddr] = false;
print_device_info(daddr);
tud_cdc_write_flush();
}
for (uint8_t daddr = 1; daddr <= CFG_TUH_DEVICE_MAX; daddr++) {
if (tuh_mounted(daddr)) {
if (is_print[daddr]) {
is_print[daddr] = false;
print_device_info(daddr, &descriptor_device[daddr]);
tud_cdc_write_flush();
}
}
}
@@ -221,6 +160,77 @@ void cdc_task(void) {
//--------------------------------------------------------------------+
// Host Get device information
//--------------------------------------------------------------------+
#define cdc_printf(...) \
do { \
char _tempbuf[256]; \
char* _bufptr = _tempbuf; \
uint32_t count = (uint32_t) sprintf(_tempbuf, __VA_ARGS__); \
while (count > 0) { \
uint32_t wr_count = tud_cdc_write(_bufptr, count); \
count -= wr_count; \
_bufptr += wr_count; \
if (count > 0){ \
tud_task();\
tud_cdc_write_flush(); \
} \
} \
} while(0)
static void print_device_info(uint8_t daddr, const tusb_desc_device_t* desc_device) {
// Get String descriptor using Sync API
uint16_t serial[64];
uint16_t buf[128];
(void) buf;
cdc_printf("Device %u: ID %04x:%04x SN ", daddr, desc_device->idVendor, desc_device->idProduct);
uint8_t xfer_result = tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, serial, sizeof(serial));
if (XFER_RESULT_SUCCESS != xfer_result) {
serial[0] = 'n';
serial[1] = '/';
serial[2] = 'a';
serial[3] = 0;
}
print_utf16(serial, TU_ARRAY_SIZE(serial));
cdc_printf("\r\n");
cdc_printf("Device Descriptor:\r\n");
cdc_printf(" bLength %u\r\n" , desc_device->bLength);
cdc_printf(" bDescriptorType %u\r\n" , desc_device->bDescriptorType);
cdc_printf(" bcdUSB %04x\r\n" , desc_device->bcdUSB);
cdc_printf(" bDeviceClass %u\r\n" , desc_device->bDeviceClass);
cdc_printf(" bDeviceSubClass %u\r\n" , desc_device->bDeviceSubClass);
cdc_printf(" bDeviceProtocol %u\r\n" , desc_device->bDeviceProtocol);
cdc_printf(" bMaxPacketSize0 %u\r\n" , desc_device->bMaxPacketSize0);
cdc_printf(" idVendor 0x%04x\r\n" , desc_device->idVendor);
cdc_printf(" idProduct 0x%04x\r\n" , desc_device->idProduct);
cdc_printf(" bcdDevice %04x\r\n" , desc_device->bcdDevice);
cdc_printf(" iManufacturer %u " , desc_device->iManufacturer);
xfer_result = tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, buf, sizeof(buf));
if (XFER_RESULT_SUCCESS == xfer_result) {
print_utf16(buf, TU_ARRAY_SIZE(buf));
}
cdc_printf("\r\n");
cdc_printf(" iProduct %u " , desc_device->iProduct);
xfer_result = tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, buf, sizeof(buf));
if (XFER_RESULT_SUCCESS == xfer_result) {
print_utf16(buf, TU_ARRAY_SIZE(buf));
}
cdc_printf("\r\n");
cdc_printf(" iSerialNumber %u " , desc_device->iSerialNumber);
cdc_printf((char*)serial); // serial is already to UTF-8
cdc_printf("\r\n");
cdc_printf(" bNumConfigurations %u\r\n" , desc_device->bNumConfigurations);
}
void tuh_enum_descriptor_device_cb(uint8_t daddr, tusb_desc_device_t const* desc_device) {
(void) daddr;
descriptor_device[daddr] = *desc_device; // save device descriptor
}
void tuh_mount_cb(uint8_t daddr) {
printf("mounted device %u\r\n", daddr);
is_print[daddr] = true;
@@ -296,7 +306,5 @@ static void print_utf16(uint16_t *temp_buf, size_t buf_len) {
_convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len);
((uint8_t*) temp_buf)[utf8_len] = '\0';
tud_cdc_write(temp_buf, utf8_len);
tud_cdc_write_flush();
tud_task();
cdc_printf((char*) temp_buf);
}

244
examples/host/bare_api/src/main.c
View File

@@ -55,16 +55,15 @@ uint8_t* get_hid_buf(uint8_t daddr);
void free_hid_buf(uint8_t daddr);
/*------------- MAIN -------------*/
int main(void)
{
int main(void) {
board_init();
printf("TinyUSB Bare API Example\r\n");
// init host stack on configured roothub port
tusb_rhport_init_t host_init = {
.role = TUSB_ROLE_HOST,
.speed = TUSB_SPEED_AUTO
.role = TUSB_ROLE_HOST,
.speed = TUSB_SPEED_AUTO
};
tusb_init(BOARD_TUH_RHPORT, &host_init);
@@ -72,8 +71,7 @@ int main(void)
board_init_after_tusb();
}
while (1)
{
while (1) {
// tinyusb host task
tuh_task();
led_blinking_task();
@@ -85,8 +83,7 @@ int main(void)
/*------------- TinyUSB Callbacks -------------*/
// Invoked when device is mounted (configured)
void tuh_mount_cb (uint8_t daddr)
{
void tuh_mount_cb(uint8_t daddr) {
printf("Device attached, address = %d\r\n", daddr);
// Get Device Descriptor
@@ -95,8 +92,7 @@ void tuh_mount_cb (uint8_t daddr)
}
/// Invoked when device is unmounted (bus reset/unplugged)
void tuh_umount_cb(uint8_t daddr)
{
void tuh_umount_cb(uint8_t daddr) {
printf("Device removed, address = %d\r\n", daddr);
free_hid_buf(daddr);
}
@@ -104,11 +100,8 @@ void tuh_umount_cb(uint8_t daddr)
//--------------------------------------------------------------------+
// Device Descriptor
//--------------------------------------------------------------------+
void print_device_descriptor(tuh_xfer_t* xfer)
{
if ( XFER_RESULT_SUCCESS != xfer->result )
{
void print_device_descriptor(tuh_xfer_t *xfer) {
if (XFER_RESULT_SUCCESS != xfer->result) {
printf("Failed to get device descriptor\r\n");
return;
}
@@ -131,33 +124,29 @@ void print_device_descriptor(tuh_xfer_t* xfer)
// Get String descriptor using Sync API
uint16_t temp_buf[128];
printf(" iManufacturer %u " , desc_device.iManufacturer);
if (XFER_RESULT_SUCCESS == tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf)) )
{
printf(" iManufacturer %u ", desc_device.iManufacturer);
if (XFER_RESULT_SUCCESS == tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf))) {
print_utf16(temp_buf, TU_ARRAY_SIZE(temp_buf));
}
printf("\r\n");
printf(" iProduct %u " , desc_device.iProduct);
if (XFER_RESULT_SUCCESS == tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf)))
{
printf(" iProduct %u ", desc_device.iProduct);
if (XFER_RESULT_SUCCESS == tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf))) {
print_utf16(temp_buf, TU_ARRAY_SIZE(temp_buf));
}
printf("\r\n");
printf(" iSerialNumber %u " , desc_device.iSerialNumber);
if (XFER_RESULT_SUCCESS == tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf)))
{
printf(" iSerialNumber %u ", desc_device.iSerialNumber);
if (XFER_RESULT_SUCCESS == tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf))) {
print_utf16(temp_buf, TU_ARRAY_SIZE(temp_buf));
}
printf("\r\n");
printf(" bNumConfigurations %u\r\n" , desc_device.bNumConfigurations);
printf(" bNumConfigurations %u\r\n", desc_device.bNumConfigurations);
// Get configuration descriptor with sync API
if (XFER_RESULT_SUCCESS == tuh_descriptor_get_configuration_sync(daddr, 0, temp_buf, sizeof(temp_buf)))
{
parse_config_descriptor(daddr, (tusb_desc_configuration_t*) temp_buf);
if (XFER_RESULT_SUCCESS == tuh_descriptor_get_configuration_sync(daddr, 0, temp_buf, sizeof(temp_buf))) {
parse_config_descriptor(daddr, (tusb_desc_configuration_t *) temp_buf);
}
}
@@ -171,37 +160,33 @@ uint16_t count_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_
void open_hid_interface(uint8_t daddr, tusb_desc_interface_t const *desc_itf, uint16_t max_len);
// simple configuration parser to open and listen to HID Endpoint IN
void parse_config_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg)
{
uint8_t const* desc_end = ((uint8_t const*) desc_cfg) + tu_le16toh(desc_cfg->wTotalLength);
uint8_t const* p_desc = tu_desc_next(desc_cfg);
void parse_config_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const *desc_cfg) {
uint8_t const *desc_end = ((uint8_t const *) desc_cfg) + tu_le16toh(desc_cfg->wTotalLength);
uint8_t const *p_desc = tu_desc_next(desc_cfg);
// parse each interfaces
while( p_desc < desc_end )
{
while (p_desc < desc_end) {
uint8_t assoc_itf_count = 1;
// Class will always starts with Interface Association (if any) and then Interface descriptor
if ( TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc) )
{
tusb_desc_interface_assoc_t const * desc_iad = (tusb_desc_interface_assoc_t const *) p_desc;
if (TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc)) {
tusb_desc_interface_assoc_t const *desc_iad = (tusb_desc_interface_assoc_t const *) p_desc;
assoc_itf_count = desc_iad->bInterfaceCount;
p_desc = tu_desc_next(p_desc); // next to Interface
p_desc = tu_desc_next(p_desc);// next to Interface
}
// must be interface from now
if( TUSB_DESC_INTERFACE != tu_desc_type(p_desc) ) return;
tusb_desc_interface_t const* desc_itf = (tusb_desc_interface_t const*) p_desc;
if (TUSB_DESC_INTERFACE != tu_desc_type(p_desc)) { return; }
tusb_desc_interface_t const *desc_itf = (tusb_desc_interface_t const *) p_desc;
uint16_t const drv_len = count_interface_total_len(desc_itf, assoc_itf_count, (uint16_t) (desc_end-p_desc));
uint16_t const drv_len = count_interface_total_len(desc_itf, assoc_itf_count, (uint16_t) (desc_end - p_desc));
// probably corrupted descriptor
if(drv_len < sizeof(tusb_desc_interface_t)) return;
if (drv_len < sizeof(tusb_desc_interface_t)) { return; }
// only open and listen to HID endpoint IN
if (desc_itf->bInterfaceClass == TUSB_CLASS_HID)
{
if (desc_itf->bInterfaceClass == TUSB_CLASS_HID) {
open_hid_interface(dev_addr, desc_itf, drv_len);
}
@@ -210,25 +195,21 @@ void parse_config_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const*
}
}
uint16_t count_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len)
{
uint8_t const* p_desc = (uint8_t const*) desc_itf;
uint16_t count_interface_total_len(tusb_desc_interface_t const *desc_itf, uint8_t itf_count, uint16_t max_len) {
uint8_t const *p_desc = (uint8_t const *) desc_itf;
uint16_t len = 0;
while (itf_count--)
{
while (itf_count--) {
// Next on interface desc
len += tu_desc_len(desc_itf);
p_desc = tu_desc_next(p_desc);
while (len < max_len)
{
while (len < max_len) {
// return on IAD regardless of itf count
if ( tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION ) return len;
if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION) { return len; }
if ( (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) &&
((tusb_desc_interface_t const*) p_desc)->bAlternateSetting == 0 )
{
if ((tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) &&
((tusb_desc_interface_t const *) p_desc)->bAlternateSetting == 0) {
break;
}
@@ -246,46 +227,45 @@ uint16_t count_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_
void hid_report_received(tuh_xfer_t* xfer);
void open_hid_interface(uint8_t daddr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
{
void open_hid_interface(uint8_t daddr, tusb_desc_interface_t const *desc_itf, uint16_t max_len) {
// len = interface + hid + n*endpoints
uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) +
desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t));
// corrupted descriptor
if (max_len < drv_len) return;
if (max_len < drv_len) { return; }
uint8_t const *p_desc = (uint8_t const *) desc_itf;
// HID descriptor
p_desc = tu_desc_next(p_desc);
tusb_hid_descriptor_hid_t const *desc_hid = (tusb_hid_descriptor_hid_t const *) p_desc;
if(HID_DESC_TYPE_HID != desc_hid->bDescriptorType) return;
if (HID_DESC_TYPE_HID != desc_hid->bDescriptorType) { return; }
// Endpoint descriptor
p_desc = tu_desc_next(p_desc);
tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
for(int i = 0; i < desc_itf->bNumEndpoints; i++)
{
if (TUSB_DESC_ENDPOINT != desc_ep->bDescriptorType) return;
for (int i = 0; i < desc_itf->bNumEndpoints; i++) {
if (TUSB_DESC_ENDPOINT != desc_ep->bDescriptorType) { return; }
if(tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN)
{
// skip if failed to open endpoint
if ( ! tuh_edpt_open(daddr, desc_ep) ) return;
if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) {
if (!tuh_edpt_open(daddr, desc_ep)) {
return; // skip if failed to open endpoint
}
uint8_t* buf = get_hid_buf(daddr);
if (!buf) return; // out of memory
uint8_t *buf = get_hid_buf(daddr);
if (!buf) {
return;// out of memory
}
tuh_xfer_t xfer =
{
.daddr = daddr,
.ep_addr = desc_ep->bEndpointAddress,
.buflen = 64,
.buffer = buf,
.complete_cb = hid_report_received,
.user_data = (uintptr_t) buf, // since buffer is not available in callback, use user data to store the buffer
tuh_xfer_t xfer = {
.daddr = daddr,
.ep_addr = desc_ep->bEndpointAddress,
.buflen = 64,
.buffer = buf,
.complete_cb = hid_report_received,
.user_data = (uintptr_t) buf,// since buffer is not available in callback, use user data to store the buffer
};
// submit transfer for this EP
@@ -299,18 +279,17 @@ void open_hid_interface(uint8_t daddr, tusb_desc_interface_t const *desc_itf, ui
}
}
void hid_report_received(tuh_xfer_t* xfer)
{
void hid_report_received(tuh_xfer_t *xfer) {
// Note: not all field in xfer is available for use (i.e filled by tinyusb stack) in callback to save sram
// For instance, xfer->buffer is NULL. We have used user_data to store buffer when submitted callback
uint8_t* buf = (uint8_t*) xfer->user_data;
uint8_t *buf = (uint8_t *) xfer->user_data;
if (xfer->result == XFER_RESULT_SUCCESS)
{
if (xfer->result == XFER_RESULT_SUCCESS) {
printf("[dev %u: ep %02x] HID Report:", xfer->daddr, xfer->ep_addr);
for(uint32_t i=0; i<xfer->actual_len; i++)
{
if (i%16 == 0) printf("\r\n ");
for (uint32_t i = 0; i < xfer->actual_len; i++) {
if (i % 16 == 0) {
printf("\r\n ");
}
printf("%02X ", buf[i]);
}
printf("\r\n");
@@ -329,12 +308,9 @@ void hid_report_received(tuh_xfer_t* xfer)
//--------------------------------------------------------------------+
// get an buffer from pool
uint8_t* get_hid_buf(uint8_t daddr)
{
for(size_t i=0; i<BUF_COUNT; i++)
{
if (buf_owner[i] == 0)
{
uint8_t *get_hid_buf(uint8_t daddr) {
for (size_t i = 0; i < BUF_COUNT; i++) {
if (buf_owner[i] == 0) {
buf_owner[i] = daddr;
return buf_pool[i];
}
@@ -345,10 +321,8 @@ uint8_t* get_hid_buf(uint8_t daddr)
}
// free all buffer owned by device
void free_hid_buf(uint8_t daddr)
{
for(size_t i=0; i<BUF_COUNT; i++)
{
void free_hid_buf(uint8_t daddr) {
for (size_t i = 0; i < BUF_COUNT; i++) {
if (buf_owner[i] == daddr) buf_owner[i] = 0;
}
}
@@ -356,70 +330,70 @@ void free_hid_buf(uint8_t daddr)
//--------------------------------------------------------------------+
// Blinking Task
//--------------------------------------------------------------------+
void led_blinking_task(void)
{
void led_blinking_task(void) {
const uint32_t interval_ms = 1000;
static uint32_t start_ms = 0;
static bool led_state = false;
// Blink every interval ms
if ( board_millis() - start_ms < interval_ms) return; // not enough time
if (board_millis() - start_ms < interval_ms) {
return; // not enough time
}
start_ms += interval_ms;
board_led_write(led_state);
led_state = 1 - led_state; // toggle
led_state = 1 - led_state;// toggle
}
//--------------------------------------------------------------------+
// String Descriptor Helper
//--------------------------------------------------------------------+
static void _convert_utf16le_to_utf8(const uint16_t *utf16, size_t utf16_len, uint8_t *utf8, size_t utf8_len) {
// TODO: Check for runover.
(void)utf8_len;
// Get the UTF-16 length out of the data itself.
// TODO: Check for runover.
(void) utf8_len;
// Get the UTF-16 length out of the data itself.
for (size_t i = 0; i < utf16_len; i++) {
uint16_t chr = utf16[i];
if (chr < 0x80) {
*utf8++ = chr & 0xffu;
} else if (chr < 0x800) {
*utf8++ = (uint8_t)(0xC0 | (chr >> 6 & 0x1F));
*utf8++ = (uint8_t)(0x80 | (chr >> 0 & 0x3F));
} else {
// TODO: Verify surrogate.
*utf8++ = (uint8_t)(0xE0 | (chr >> 12 & 0x0F));
*utf8++ = (uint8_t)(0x80 | (chr >> 6 & 0x3F));
*utf8++ = (uint8_t)(0x80 | (chr >> 0 & 0x3F));
}
// TODO: Handle UTF-16 code points that take two entries.
for (size_t i = 0; i < utf16_len; i++) {
uint16_t chr = utf16[i];
if (chr < 0x80) {
*utf8++ = chr & 0xffu;
} else if (chr < 0x800) {
*utf8++ = (uint8_t) (0xC0 | (chr >> 6 & 0x1F));
*utf8++ = (uint8_t) (0x80 | (chr >> 0 & 0x3F));
} else {
// TODO: Verify surrogate.
*utf8++ = (uint8_t) (0xE0 | (chr >> 12 & 0x0F));
*utf8++ = (uint8_t) (0x80 | (chr >> 6 & 0x3F));
*utf8++ = (uint8_t) (0x80 | (chr >> 0 & 0x3F));
}
// TODO: Handle UTF-16 code points that take two entries.
}
}
// Count how many bytes a utf-16-le encoded string will take in utf-8.
static int _count_utf8_bytes(const uint16_t *buf, size_t len) {
size_t total_bytes = 0;
for (size_t i = 0; i < len; i++) {
uint16_t chr = buf[i];
if (chr < 0x80) {
total_bytes += 1;
} else if (chr < 0x800) {
total_bytes += 2;
} else {
total_bytes += 3;
}
// TODO: Handle UTF-16 code points that take two entries.
size_t total_bytes = 0;
for (size_t i = 0; i < len; i++) {
uint16_t chr = buf[i];
if (chr < 0x80) {
total_bytes += 1;
} else if (chr < 0x800) {
total_bytes += 2;
} else {
total_bytes += 3;
}
return (int) total_bytes;
// TODO: Handle UTF-16 code points that take two entries.
}
return (int) total_bytes;
}
static void print_utf16(uint16_t *temp_buf, size_t buf_len) {
if ((temp_buf[0] & 0xff) == 0) return; // empty
size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t);
size_t utf8_len = (size_t) _count_utf8_bytes(temp_buf + 1, utf16_len);
_convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len);
((uint8_t*) temp_buf)[utf8_len] = '\0';
if ((temp_buf[0] & 0xff) == 0) return;// empty
size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t);
size_t utf8_len = (size_t) _count_utf8_bytes(temp_buf + 1, utf16_len);
_convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len);
((uint8_t *) temp_buf)[utf8_len] = '\0';
printf("%s", (char*)temp_buf);
printf("%s", (char *) temp_buf);
}

2
examples/host/cdc_msc_hid/src/cdc_app.c
View File

@@ -27,7 +27,7 @@
#include "tusb.h"
#include "bsp/board_api.h"
size_t get_console_inputs(uint8_t* buf, size_t bufsize) {
static size_t get_console_inputs(uint8_t* buf, size_t bufsize) {
size_t count = 0;
while (count < bufsize) {
int ch = board_getchar();

3
examples/host/cdc_msc_hid/src/hid_app.c
View File

@@ -165,8 +165,7 @@ static void process_kbd_report(hid_keyboard_report_t const *report)
// Mouse
//--------------------------------------------------------------------+
void cursor_movement(int8_t x, int8_t y, int8_t wheel)
{
static void cursor_movement(int8_t x, int8_t y, int8_t wheel) {
#if USE_ANSI_ESCAPE
// Move X using ansi escape
if ( x < 0)

12
examples/host/cdc_msc_hid/src/main.c
View File

@@ -31,18 +31,12 @@
#include "tusb.h"
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF PROTYPES
// MACRO CONSTANT TYPEDEF PROTOTYPES
//--------------------------------------------------------------------+
void led_blinking_task(void);
extern void cdc_app_task(void);
extern void hid_app_task(void);
#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
// API to read/rite MAX3421's register. Implemented by TinyUSB
extern uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr);
extern bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr);
#endif
/*------------- MAIN -------------*/
int main(void) {
board_init();
@@ -101,7 +95,9 @@ void led_blinking_task(void) {
static bool led_state = false;
// Blink every interval ms
if (board_millis() - start_ms < interval_ms) return; // not enough time
if (board_millis() - start_ms < interval_ms) {
return;// not enough time
}
start_ms += interval_ms;
board_led_write(led_state);

2
examples/host/cdc_msc_hid_freertos/src/cdc_app.c
View File

@@ -52,7 +52,7 @@ void cdc_app_init(void) {
}
// helper
size_t get_console_inputs(uint8_t *buf, size_t bufsize) {
static size_t get_console_inputs(uint8_t *buf, size_t bufsize) {
size_t count = 0;
while (count < bufsize) {
int ch = board_getchar();

6
examples/host/cdc_msc_hid_freertos/src/main.c
View File

@@ -69,12 +69,6 @@ extern void cdc_app_init(void);
extern void hid_app_init(void);
extern void msc_app_init(void);
#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
// API to read/rite MAX3421's register. Implemented by TinyUSB
extern uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr);
extern bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr);
#endif
/*------------- MAIN -------------*/
int main(void) {
board_init();

2
examples/host/cdc_msc_hid_freertos/src/msc_app.c
View File

@@ -34,7 +34,7 @@ void msc_app_init(void) {
// nothing to do
}
bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const *cb_data) {
static bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const *cb_data) {
msc_cbw_t const *cbw = cb_data->cbw;
msc_csw_t const *csw = cb_data->csw;

2
examples/host/device_info/src/main.c
View File

@@ -81,7 +81,7 @@ void init_freertos_task(void);
//--------------------------------------------------------------------
// Main
//--------------------------------------------------------------------
void init_tinyusb(void) {
static void init_tinyusb(void) {
// init host stack on configured roothub port
tusb_rhport_init_t host_init = {
.role = TUSB_ROLE_HOST,

17
examples/host/hid_controller/src/hid_app.c
View File

@@ -231,14 +231,12 @@ void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance)
}
// check if different than 2
bool diff_than_2(uint8_t x, uint8_t y)
{
static inline bool diff_than_2(uint8_t x, uint8_t y) {
return (x - y > 2) || (y - x > 2);
}
// check if 2 reports are different enough
bool diff_report(sony_ds4_report_t const* rpt1, sony_ds4_report_t const* rpt2)
{
static bool diff_report(sony_ds4_report_t const* rpt1, sony_ds4_report_t const* rpt2) {
bool result;
// x, y, z, rz must different than 2 to be counted
@@ -251,7 +249,7 @@ bool diff_report(sony_ds4_report_t const* rpt1, sony_ds4_report_t const* rpt2)
return result;
}
void process_sony_ds4(uint8_t const* report, uint16_t len)
static void process_sony_ds4(uint8_t const* report, uint16_t len)
{
(void)len;
const char* dpad_str[] = { "N", "NE", "E", "SE", "S", "SW", "W", "NW", "none" };
@@ -310,16 +308,13 @@ void process_sony_ds4(uint8_t const* report, uint16_t len)
}
// Invoked when received report from device via interrupt endpoint
void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len)
{
if ( is_sony_ds4(dev_addr) )
{
void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t const *report, uint16_t len) {
if (is_sony_ds4(dev_addr)) {
process_sony_ds4(report, len);
}
// continue to request to receive report
if ( !tuh_hid_receive_report(dev_addr, instance) )
{
if (!tuh_hid_receive_report(dev_addr, instance)) {
printf("Error: cannot request to receive report\r\n");
}
}

2
examples/host/msc_file_explorer/src/msc_app.c
View File

@@ -34,6 +34,8 @@
#define EMBEDDED_CLI_IMPL
#include "embedded_cli.h"
#include "msc_app.h"
//--------------------------------------------------------------------+
// MACRO TYPEDEF CONSTANT ENUM DECLARATION

4
hw/bsp/family_support.cmake
View File

@@ -270,10 +270,6 @@ function(family_add_tinyusb TARGET OPT_MCU)
# Add TinyUSB sources, include and common define
tinyusb_target_add(${TARGET})
# path to tusb_config.h
target_include_directories(${TARGET} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src)
target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_MCU=${OPT_MCU})
if (DEFINED LOG)
target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_DEBUG=${LOG})

4
hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c
View File

@@ -15,11 +15,11 @@
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v11.0
product: Clocks v15.0
processor: MIMXRT1015xxxxx
package_id: MIMXRT1015DAF5A
mcu_data: ksdk2_0
processor_version: 13.0.2
processor_version: 24.12.10
board: MIMXRT1015-EVK
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/

66
hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h
View File

@@ -36,39 +36,39 @@ void BOARD_InitBootClocks(void);
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 196363636UL
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, USB, WDOG1, WDOG2 */
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */
#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL /* Clock consumers of ENET_500M_REF_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 196363636UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC_ETC, AOI, ARM, BEE, CCM, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, EWM, FLEXIO1, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO5, IOMUXC, KPP, LPI2C1, LPI2C2, LPSPI1, LPSPI2, LPUART1, LPUART2, LPUART3, LPUART4, NVIC, OCOTP, PWM1, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TRNG, USB, WDOG1, WDOG2, XBARA, XBARB */
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2 */
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2 */
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4 */
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB */
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
*/

35
hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.c
View File

@@ -6,11 +6,11 @@
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v13.1
product: Pins v17.0
processor: MIMXRT1015xxxxx
package_id: MIMXRT1015DAF5A
mcu_data: ksdk2_0
processor_version: 13.0.2
processor_version: 24.12.10
board: MIMXRT1015-EVK
external_user_signals: {}
pin_labels:
@@ -32,6 +32,7 @@ power_domains: {NVCC_GPIO: '3.3'}
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void) {
BOARD_InitPins();
BOARD_InitDEBUG_UARTPins();
}
/*
@@ -40,8 +41,6 @@ BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '1', peripheral: GPIO2, signal: 'gpio_io, 09', pin_signal: GPIO_EMC_09, direction: INPUT, pull_keeper_select: Pull, pull_up_down_config: Pull_Up_47K_Ohm}
- {pin_num: '68', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07, pull_up_down_config: Pull_Down_100K_Ohm}
- {pin_num: '72', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06}
- {pin_num: '21', peripheral: GPIO3, signal: 'gpio_io, 21', pin_signal: GPIO_SD_B1_01, direction: OUTPUT}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
@@ -73,15 +72,11 @@ void BOARD_InitPins(void) {
/* Initialize GPIO functionality on GPIO_SD_B1_01 (pin 21) */
GPIO_PinInit(GPIO3, 21U, &USER_LED_config);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_GPIO2_IO09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_GPIO3_IO21, 0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0x10B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_09_GPIO2_IO09, 0x70B0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitQSPIPins:
@@ -113,6 +108,30 @@ void BOARD_InitQSPIPins(void) {
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B, 0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitDEBUG_UARTPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '68', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07, slew_rate: Slow}
- {pin_num: '72', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06, slew_rate: Slow}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitDEBUG_UARTPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitDEBUG_UARTPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0x10B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0x10B0U);
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

30
hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.h
View File

@@ -37,7 +37,7 @@ extern "C" {
*/
void BOARD_InitBootPins(void);
/* GPIO_EMC_09 (number 1), USER_BUTTON */
/* GPIO_EMC_09 (number 1), USER_BUTTON/SW4 */
/* Routed pin properties */
#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO2 /*!< Peripheral name */
#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */
@@ -51,16 +51,6 @@ void BOARD_InitBootPins(void);
#define BOARD_INITPINS_USER_BUTTON_PIN 9U /*!< PORT pin number */
#define BOARD_INITPINS_USER_BUTTON_PIN_MASK (1U << 9U) /*!< PORT pin mask */
/* GPIO_AD_B0_07 (number 68), LPUART1_RXD */
/* Routed pin properties */
#define BOARD_INITPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITPINS_UART1_RXD_SIGNAL RX /*!< Signal name */
/* GPIO_AD_B0_06 (number 72), LPUART1_TXD */
/* Routed pin properties */
#define BOARD_INITPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITPINS_UART1_TXD_SIGNAL TX /*!< Signal name */
/* GPIO_SD_B1_01 (number 21), GPIO SD_B1_01 */
/* Routed pin properties */
#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO3 /*!< Peripheral name */
@@ -69,6 +59,7 @@ void BOARD_InitBootPins(void);
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_USER_LED_GPIO GPIO3 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */
#define BOARD_INITPINS_USER_LED_GPIO_PIN 21U /*!< GPIO pin number */
#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 21U) /*!< GPIO pin mask */
#define BOARD_INITPINS_USER_LED_PORT GPIO3 /*!< PORT peripheral base pointer */
@@ -119,6 +110,23 @@ void BOARD_InitPins(void);
*/
void BOARD_InitQSPIPins(void);
/* GPIO_AD_B0_07 (number 68), LPUART1_RXD */
/* Routed pin properties */
#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RX /*!< Signal name */
/* GPIO_AD_B0_06 (number 72), LPUART1_TXD */
/* Routed pin properties */
#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TX /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitDEBUG_UARTPins(void);
#if defined(__cplusplus)
}
#endif

63
hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding= "UTF-8" ?>
<configuration name="MIMXRT1015-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="4be4468a-3124-4ac9-9d4f-05d5f8ad6399" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<configuration name="MIMXRT1015-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_17 http://mcuxpresso.nxp.com/XSD/mex_configuration_17.xsd" uuid="4be4468a-3124-4ac9-9d4f-05d5f8ad6399" version="17" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_17" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<common>
<processor>MIMXRT1015xxxxx</processor>
<package>MIMXRT1015DAF5A</package>
@@ -13,19 +13,18 @@
</common>
<preferences>
<validate_boot_init_only>true</validate_boot_init_only>
<generate_extended_information>false</generate_extended_information>
<generate_code_modified_registers_only>false</generate_code_modified_registers_only>
<update_include_paths>true</update_include_paths>
<generate_registers_defines>false</generate_registers_defines>
</preferences>
<tools>
<pins name="Pins" version="13.1" enabled="true" update_project_code="true">
<pins name="Pins" version="17.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/pin_mux.c" update_enabled="true"/>
<file path="board/pin_mux.h" update_enabled="true"/>
</generated_project_files>
<pins_profile>
<processor_version>13.0.2</processor_version>
<processor_version>24.12.10</processor_version>
<pin_labels>
<pin_label pin_num="21" pin_signal="GPIO_SD_B1_01" label="GPIO SD_B1_01" identifier="USER_LED"/>
</pin_labels>
@@ -45,12 +44,7 @@
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="GPIO2" description="Peripheral GPIO2 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
<dependency resourceType="Peripheral" resourceId="GPIO2" description="Peripheral GPIO2 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
@@ -79,12 +73,6 @@
<pin_feature name="pull_up_down_config" value="Pull_Up_47K_Ohm"/>
</pin_features>
</pin>
<pin peripheral="LPUART1" signal="RX" pin_num="68" pin_signal="GPIO_AD_B0_07">
<pin_features>
<pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
</pin_features>
</pin>
<pin peripheral="LPUART1" signal="TX" pin_num="72" pin_signal="GPIO_AD_B0_06"/>
<pin peripheral="GPIO3" signal="gpio_io, 21" pin_num="21" pin_signal="GPIO_SD_B1_01">
<pin_features>
<pin_feature name="direction" value="OUTPUT"/>
@@ -100,7 +88,7 @@
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins">
<dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitQSPIPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
@@ -125,15 +113,52 @@
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="8" pin_signal="GPIO_SD_B1_11"/>
</pins>
</function>
<function name="BOARD_InitDEBUG_UARTPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<callFromInitBoot>true</callFromInitBoot>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="LPUART1" signal="RX" pin_num="68" pin_signal="GPIO_AD_B0_07">
<pin_features>
<pin_feature name="slew_rate" value="Slow"/>
</pin_features>
</pin>
<pin peripheral="LPUART1" signal="TX" pin_num="72" pin_signal="GPIO_AD_B0_06">
<pin_features>
<pin_feature name="slew_rate" value="Slow"/>
</pin_features>
</pin>
</pins>
</function>
</functions_list>
</pins>
<clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
<clocks name="Clocks" version="15.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/clock_config.c" update_enabled="true"/>
<file path="board/clock_config.h" update_enabled="true"/>
</generated_project_files>
<clocks_profile>
<processor_version>13.0.2</processor_version>
<processor_version>24.12.10</processor_version>
</clocks_profile>
<clock_configurations>
<clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">

4
hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c
View File

@@ -15,11 +15,11 @@
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v11.0
product: Clocks v15.0
processor: MIMXRT1064xxxxA
package_id: MIMXRT1064DVL6A
mcu_data: ksdk2_0
processor_version: 13.0.2
processor_version: 24.12.10
board: MIMXRT1064-EVK
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/

100
hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h
View File

@@ -36,56 +36,56 @@ void BOARD_InitBootClocks(void);
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL
#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL
#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXIO3, FLEXSPI, FLEXSPI2, GPIO6, GPIO7, GPIO8, GPIO9 */
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2, CAN3 */
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */
#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL /* Clock consumers of ENET2_125M_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL /* Clock consumers of ENET2_REF_CLK output : ENET2 */
#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL /* Clock consumers of ENET2_TX_CLK output : ENET2 */
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET, ENET2 */
#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2, FLEXIO3 */
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CAN3, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, ENET2, EWM, FLEXIO1, FLEXIO2, FLEXIO3, FLEXRAM, FLEXSPI, FLEXSPI2, GPC, GPIO1, GPIO10, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, NVIC, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */
#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */
#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL /* Clock consumers of LVDS1_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */
#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */
#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL /* Clock consumers of USBPHY2_CLK output : USB2 */
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
*/

13
hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.c
View File

@@ -6,11 +6,11 @@
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v13.1
product: Pins v17.0
processor: MIMXRT1064xxxxA
package_id: MIMXRT1064DVL6A
mcu_data: ksdk2_0
processor_version: 13.0.2
processor_version: 24.12.10
board: MIMXRT1064-EVK
pin_labels:
- {pin_num: F14, pin_signal: GPIO_AD_B0_09, label: 'JTAG_TDI/J21[5]/ENET_RST/J22[5]', identifier: USER_LED}
@@ -81,7 +81,6 @@ void BOARD_InitPins(void) {
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0x50A0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitDEBUG_UARTPins:
@@ -109,7 +108,6 @@ void BOARD_InitDEBUG_UARTPins(void) {
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitSDRAMPins:
@@ -209,7 +207,6 @@ void BOARD_InitSDRAMPins(void) {
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_39_SEMC_DQS, 0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitCSIPins:
@@ -267,7 +264,6 @@ void BOARD_InitCSIPins(void) {
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0xD8B0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitLCDPins:
@@ -360,7 +356,6 @@ void BOARD_InitLCDPins(void) {
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0x10B0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitCANPins:
@@ -384,7 +379,6 @@ void BOARD_InitCANPins(void) {
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX, 0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitENETPins:
@@ -424,7 +418,6 @@ void BOARD_InitENETPins(void) {
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitUSDHCPins:
@@ -458,7 +451,6 @@ void BOARD_InitUSDHCPins(void) {
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitQSPIPins:
@@ -491,7 +483,6 @@ void BOARD_InitQSPIPins(void) {
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U);
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

1
hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.h
View File

@@ -47,6 +47,7 @@ void BOARD_InitBootPins(void);
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_USER_LED_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */
#define BOARD_INITPINS_USER_LED_GPIO_PIN 9U /*!< GPIO pin number */
#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 9U) /*!< GPIO pin mask */
#define BOARD_INITPINS_USER_LED_PORT GPIO1 /*!< PORT peripheral base pointer */

36
hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding= "UTF-8" ?>
<configuration name="MIMXRT1064-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="d75e55f6-68ab-46ef-814b-b94593af7f06" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<configuration name="MIMXRT1064-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_17 http://mcuxpresso.nxp.com/XSD/mex_configuration_17.xsd" uuid="d75e55f6-68ab-46ef-814b-b94593af7f06" version="17" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_17" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<common>
<processor>MIMXRT1064xxxxA</processor>
<package>MIMXRT1064DVL6A</package>
@@ -13,19 +13,18 @@
</common>
<preferences>
<validate_boot_init_only>true</validate_boot_init_only>
<generate_extended_information>false</generate_extended_information>
<generate_code_modified_registers_only>false</generate_code_modified_registers_only>
<update_include_paths>true</update_include_paths>
<generate_registers_defines>false</generate_registers_defines>
</preferences>
<tools>
<pins name="Pins" version="13.1" enabled="true" update_project_code="true">
<pins name="Pins" version="17.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/pin_mux.c" update_enabled="true"/>
<file path="board/pin_mux.h" update_enabled="true"/>
</generated_project_files>
<pins_profile>
<processor_version>13.0.2</processor_version>
<processor_version>24.12.10</processor_version>
<pin_labels>
<pin_label pin_num="F14" pin_signal="GPIO_AD_B0_09" label="JTAG_TDI/J21[5]/ENET_RST/J22[5]" identifier="USER_LED"/>
<pin_label pin_num="L6" pin_signal="WAKEUP" label="SD_PWREN" identifier="USER_BUTTON"/>
@@ -41,7 +40,7 @@
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="GPIO5" description="Peripheral GPIO5 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
<dependency resourceType="Peripheral" resourceId="GPIO5" description="Peripheral GPIO5 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
@@ -84,7 +83,7 @@
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
<dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
@@ -137,7 +136,7 @@
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins">
<dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitSDRAMPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
@@ -204,12 +203,12 @@
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="CSI" description="Peripheral CSI is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins">
<dependency resourceType="Peripheral" resourceId="CSI" description="Peripheral CSI signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitCSIPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins">
<dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitCSIPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
@@ -277,7 +276,7 @@
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="LCDIF" description="Peripheral LCDIF is not initialized" problem_level="1" source="Pins:BOARD_InitLCDPins">
<dependency resourceType="Peripheral" resourceId="LCDIF" description="Peripheral LCDIF signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitLCDPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
@@ -450,7 +449,7 @@
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="CAN2" description="Peripheral CAN2 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins">
<dependency resourceType="Peripheral" resourceId="CAN2" description="Peripheral CAN2 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitCANPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
@@ -479,7 +478,7 @@
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins">
<dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitENETPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
@@ -516,7 +515,7 @@
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins">
<dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitUSDHCPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
@@ -550,7 +549,7 @@
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins">
<dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitQSPIPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
@@ -578,13 +577,13 @@
</function>
</functions_list>
</pins>
<clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
<clocks name="Clocks" version="15.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/clock_config.c" update_enabled="true"/>
<file path="board/clock_config.h" update_enabled="true"/>
</generated_project_files>
<clocks_profile>
<processor_version>13.0.2</processor_version>
<processor_version>24.12.10</processor_version>
</clocks_profile>
<clock_configurations>
<clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
@@ -751,10 +750,7 @@
<dcdx_configurations/>
</dcdx>
<periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true">
<generated_project_files>
<file path="board/peripherals.c" update_enabled="true"/>
<file path="board/peripherals.h" update_enabled="true"/>
</generated_project_files>
<generated_project_files/>
<peripherals_profile>
<processor_version>13.0.2</processor_version>
</peripherals_profile>

4
hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c
View File

@@ -11,11 +11,11 @@
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v14.0
product: Clocks v15.0
processor: MIMXRT1176xxxxx
package_id: MIMXRT1176DVMAA
mcu_data: ksdk2_0
processor_version: 16.3.0
processor_version: 24.12.10
board: MIMXRT1170-EVKB
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/

56
hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c
View File

@@ -6,11 +6,11 @@
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v16.0
product: Pins v17.0
processor: MIMXRT1176xxxxx
package_id: MIMXRT1176DVMAA
mcu_data: ksdk2_0
processor_version: 16.3.0
processor_version: 24.12.10
board: MIMXRT1170-EVKB
external_user_signals: {}
pin_labels:
@@ -31,6 +31,7 @@ pin_labels:
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void) {
BOARD_InitPins();
BOARD_InitDEBUG_UARTPins();
}
/*
@@ -38,10 +39,6 @@ void BOARD_InitBootPins(void) {
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'}
- pin_list:
- {pin_num: M15, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AD_25, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
open_drain: Disable, drive_strength: High, slew_rate: Slow}
- {pin_num: L13, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AD_24, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
open_drain: Disable, drive_strength: High, slew_rate: Slow}
- {pin_num: M13, peripheral: GPIO9, signal: 'gpio_io, 03', pin_signal: GPIO_AD_04, identifier: USER_LED, direction: OUTPUT, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper}
- {pin_num: T8, peripheral: GPIO13, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT, pull_up_down_config: Pull_Up}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
@@ -77,12 +74,6 @@ void BOARD_InitPins(void) {
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_04_GPIO9_IO03, /* GPIO_AD_04 is configured as GPIO9_IO03 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 is configured as LPUART1_TXD */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 is configured as LPUART1_RXD */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_WAKEUP_DIG_GPIO13_IO00, /* WAKEUP_DIG is configured as GPIO13_IO00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
@@ -95,6 +86,40 @@ void BOARD_InitPins(void) {
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_WAKEUP_DIG_GPIO13_IO00, /* WAKEUP_DIG PAD functional properties : */
0x0EU); /* Pull / Keep Select Field: Pull Enable
Pull Up / Down Config. Field: Weak pull up
Open Drain SNVS Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitDEBUG_UARTPins:
- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'}
- pin_list:
- {pin_num: L13, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AD_24, pull_keeper_select: Keeper, slew_rate: Slow}
- {pin_num: M15, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AD_25, pull_keeper_select: Keeper, slew_rate: Slow}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitDEBUG_UARTPins, assigned for the Cortex-M7F core.
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitDEBUG_UARTPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 is configured as LPUART1_TXD */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 is configured as LPUART1_RXD */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 PAD functional properties : */
0x02U); /* Slew Rate Field: Slow Slew Rate
@@ -113,13 +138,6 @@ void BOARD_InitPins(void) {
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_WAKEUP_DIG_GPIO13_IO00, /* WAKEUP_DIG PAD functional properties : */
0x0EU); /* Pull / Keep Select Field: Pull Enable
Pull Up / Down Config. Field: Weak pull up
Open Drain SNVS Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
}
/***********************************************************************************************************************
* EOF

27
hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.h
View File

@@ -25,16 +25,6 @@ extern "C" {
*/
void BOARD_InitBootPins(void);
/* GPIO_AD_25 (coord M15), LPUART1_RXD */
/* Routed pin properties */
#define BOARD_INITPINS_LPUART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITPINS_LPUART1_RXD_SIGNAL RXD /*!< Signal name */
/* GPIO_AD_24 (coord L13), LPUART1_TXD */
/* Routed pin properties */
#define BOARD_INITPINS_LPUART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITPINS_LPUART1_TXD_SIGNAL TXD /*!< Signal name */
/* GPIO_AD_04 (coord M13), SIM1_PD/J44[C8]/USER_LED_CTL1/J9[8]/J25[7] */
/* Routed pin properties */
#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO9 /*!< Peripheral name */
@@ -43,6 +33,7 @@ void BOARD_InitBootPins(void);
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_USER_LED_GPIO GPIO9 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */
#define BOARD_INITPINS_USER_LED_GPIO_PIN 3U /*!< GPIO pin number */
#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 3U) /*!< GPIO pin mask */
@@ -63,6 +54,22 @@ void BOARD_InitBootPins(void);
*/
void BOARD_InitPins(void); /* Function assigned for the Cortex-M7F */
/* GPIO_AD_24 (coord L13), LPUART1_TXD */
/* Routed pin properties */
#define BOARD_INITDEBUG_UARTPINS_LPUART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITDEBUG_UARTPINS_LPUART1_TXD_SIGNAL TXD /*!< Signal name */
/* GPIO_AD_25 (coord M15), LPUART1_RXD */
/* Routed pin properties */
#define BOARD_INITDEBUG_UARTPINS_LPUART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITDEBUG_UARTPINS_LPUART1_RXD_SIGNAL RXD /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M7F */
#if defined(__cplusplus)
}
#endif

75
hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding= "UTF-8" ?>
<configuration name="MIMXRT1176xxxxx" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_16 http://mcuxpresso.nxp.com/XSD/mex_configuration_16.xsd" uuid="060646c1-2247-47a8-b52d-03c1968b4426" version="16" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_16" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<configuration name="MIMXRT1176xxxxx" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_17 http://mcuxpresso.nxp.com/XSD/mex_configuration_17.xsd" uuid="060646c1-2247-47a8-b52d-03c1968b4426" version="17" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_17" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<common>
<processor>MIMXRT1176xxxxx</processor>
<package>MIMXRT1176DVMAA</package>
@@ -13,19 +13,18 @@
</common>
<preferences>
<validate_boot_init_only>true</validate_boot_init_only>
<generate_extended_information>false</generate_extended_information>
<generate_code_modified_registers_only>false</generate_code_modified_registers_only>
<update_include_paths>true</update_include_paths>
<generate_registers_defines>false</generate_registers_defines>
</preferences>
<tools>
<pins name="Pins" version="16.0" enabled="true" update_project_code="true">
<pins name="Pins" version="17.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/pin_mux.c" update_enabled="true"/>
<file path="board/pin_mux.h" update_enabled="true"/>
</generated_project_files>
<pins_profile>
<processor_version>16.3.0</processor_version>
<processor_version>24.12.10</processor_version>
<pin_labels>
<pin_label pin_num="M13" pin_signal="GPIO_AD_04" label="SIM1_PD/J44[C8]/USER_LED_CTL1/J9[8]/J25[7]" identifier="SIM1_PD;LED;USER_LED"/>
</pin_labels>
@@ -43,11 +42,6 @@
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="cm7">
<data>true</data>
@@ -65,26 +59,6 @@
</dependency>
</dependencies>
<pins>
<pin peripheral="LPUART1" signal="RXD" pin_num="M15" pin_signal="GPIO_AD_25">
<pin_features>
<pin_feature name="software_input_on" value="Disable"/>
<pin_feature name="pull_up_down_config" value="Pull_Down"/>
<pin_feature name="pull_keeper_select" value="Keeper"/>
<pin_feature name="open_drain" value="Disable"/>
<pin_feature name="drive_strength" value="High"/>
<pin_feature name="slew_rate" value="Slow"/>
</pin_features>
</pin>
<pin peripheral="LPUART1" signal="TXD" pin_num="L13" pin_signal="GPIO_AD_24">
<pin_features>
<pin_feature name="software_input_on" value="Disable"/>
<pin_feature name="pull_up_down_config" value="Pull_Down"/>
<pin_feature name="pull_keeper_select" value="Keeper"/>
<pin_feature name="open_drain" value="Disable"/>
<pin_feature name="drive_strength" value="High"/>
<pin_feature name="slew_rate" value="Slow"/>
</pin_features>
</pin>
<pin peripheral="GPIO9" signal="gpio_io, 03" pin_num="M13" pin_signal="GPIO_AD_04">
<pin_features>
<pin_feature name="identifier" value="USER_LED"/>
@@ -101,15 +75,54 @@
</pin>
</pins>
</function>
<function name="BOARD_InitDEBUG_UARTPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<callFromInitBoot>true</callFromInitBoot>
<coreID>cm7</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
<feature name="enabled" evaluation="equal" configuration="cm7">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
<feature name="enabled" evaluation="equal" configuration="cm7">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="LPUART1" signal="TXD" pin_num="L13" pin_signal="GPIO_AD_24">
<pin_features>
<pin_feature name="pull_keeper_select" value="Keeper"/>
<pin_feature name="slew_rate" value="Slow"/>
</pin_features>
</pin>
<pin peripheral="LPUART1" signal="RXD" pin_num="M15" pin_signal="GPIO_AD_25">
<pin_features>
<pin_feature name="pull_keeper_select" value="Keeper"/>
<pin_feature name="slew_rate" value="Slow"/>
</pin_features>
</pin>
</pins>
</function>
</functions_list>
</pins>
<clocks name="Clocks" version="14.0" enabled="true" update_project_code="true">
<clocks name="Clocks" version="15.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/clock_config.c" update_enabled="true"/>
<file path="board/clock_config.h" update_enabled="true"/>
</generated_project_files>
<clocks_profile>
<processor_version>16.3.0</processor_version>
<processor_version>24.12.10</processor_version>
</clocks_profile>
<clock_configurations>
<clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">

10
hw/bsp/imxrt/family.c
View File

@@ -61,7 +61,7 @@
- Define CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable")))
*/
static void BOARD_ConfigMPU(void);
// static void BOARD_ConfigMPU(void);
// needed by fsl_flexspi_nor_boot
TU_ATTR_USED const uint8_t dcd_data[] = {0x00};
@@ -109,8 +109,8 @@ static void init_usb_phy(uint8_t usb_id) {
}
void board_init(void) {
BOARD_ConfigMPU();
BOARD_InitPins();
// BOARD_ConfigMPU();
BOARD_InitBootPins();
BOARD_BootClockRUN();
SystemCoreClockUpdate();
@@ -258,6 +258,7 @@ void _exit(int __status) {
//--------------------------------------------------------------------
// MPU configuration
//--------------------------------------------------------------------
#if 0 // TODO move to per board specific
#if __CORTEX_M == 7
static void BOARD_ConfigMPU(void) {
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
@@ -455,7 +456,7 @@ static void BOARD_ConfigMPU(void) {
#elif __CORTEX_M == 4
void BOARD_ConfigMPU(void) {
static void BOARD_ConfigMPU(void) {
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$RW_m_ncache$$Base[];
/* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
@@ -636,3 +637,4 @@ void BOARD_ConfigMPU(void) {
LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK;
}
#endif
#endif

4
hw/bsp/imxrt/family.cmake
View File

@@ -123,8 +123,6 @@ function(family_configure_example TARGET RTOS)
# Board target
add_board_target(board_${BOARD})
#---------- Port Specific ----------
# These files are built for each example since it depends on example's tusb_config.h
target_sources(${TARGET} PUBLIC
# BSP
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
@@ -146,8 +144,6 @@ function(family_configure_example TARGET RTOS)
)
target_link_libraries(${TARGET} PUBLIC board_${BOARD})
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})

38
src/class/cdc/cdc_device.c
View File

@@ -82,7 +82,7 @@ typedef struct {
static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC];
CFG_TUD_MEM_SECTION static cdcd_epbuf_t _cdcd_epbuf[CFG_TUD_CDC];
static tud_cdc_configure_fifo_t _cdcd_fifo_cfg;
static tud_cdc_configure_t _cdcd_cfg = TUD_CDC_CONFIGURE_DEFAULT();
static bool _prep_out_transaction(uint8_t itf) {
const uint8_t rhport = 0;
@@ -119,9 +119,9 @@ static bool _prep_out_transaction(uint8_t itf) {
// APPLICATION API
//--------------------------------------------------------------------+
bool tud_cdc_configure_fifo(const tud_cdc_configure_fifo_t* cfg) {
TU_VERIFY(cfg);
_cdcd_fifo_cfg = (*cfg);
bool tud_cdc_configure(const tud_cdc_configure_t* driver_cfg) {
TU_VERIFY(driver_cfg);
_cdcd_cfg = *driver_cfg;
return true;
}
@@ -175,7 +175,7 @@ void tud_cdc_n_read_flush(uint8_t itf) {
//--------------------------------------------------------------------+
uint32_t tud_cdc_n_write(uint8_t itf, const void* buffer, uint32_t bufsize) {
cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) TU_MIN(bufsize, UINT16_MAX));
uint16_t wr_count = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) TU_MIN(bufsize, UINT16_MAX));
// flush if queue more than packet size
if (tu_fifo_count(&p_cdc->tx_ff) >= BULK_PACKET_SIZE
@@ -186,7 +186,7 @@ uint32_t tud_cdc_n_write(uint8_t itf, const void* buffer, uint32_t bufsize) {
tud_cdc_n_write_flush(itf);
}
return ret;
return wr_count;
}
uint32_t tud_cdc_n_write_flush(uint8_t itf) {
@@ -233,8 +233,6 @@ bool tud_cdc_n_write_clear(uint8_t itf) {
//--------------------------------------------------------------------+
void cdcd_init(void) {
tu_memclr(_cdcd_itf, sizeof(_cdcd_itf));
tu_memclr(&_cdcd_fifo_cfg, sizeof(_cdcd_fifo_cfg));
for (uint8_t i = 0; i < CFG_TUD_CDC; i++) {
cdcd_interface_t* p_cdc = &_cdcd_itf[i];
@@ -249,10 +247,10 @@ void cdcd_init(void) {
// Config RX fifo
tu_fifo_config(&p_cdc->rx_ff, p_cdc->rx_ff_buf, TU_ARRAY_SIZE(p_cdc->rx_ff_buf), 1, false);
// Config TX fifo as overwritable at initialization and will be changed to non-overwritable
// if terminal supports DTR bit. Without DTR we do not know if data is actually polled by terminal.
// In this way, the most current data is prioritized.
tu_fifo_config(&p_cdc->tx_ff, p_cdc->tx_ff_buf, TU_ARRAY_SIZE(p_cdc->tx_ff_buf), 1, true);
// TX fifo can be configured to change to overwritable if not connected (DTR bit not set). Without DTR we do not
// know if data is actually polled by terminal. This way the most current data is prioritized.
// Default: is overwritable
tu_fifo_config(&p_cdc->tx_ff, p_cdc->tx_ff_buf, TU_ARRAY_SIZE(p_cdc->tx_ff_buf), 1, _cdcd_cfg.tx_overwritabe_if_not_connected);
#if OSAL_MUTEX_REQUIRED
osal_mutex_t mutex_rd = osal_mutex_create(&p_cdc->rx_ff_mutex);
@@ -294,13 +292,13 @@ void cdcd_reset(uint8_t rhport) {
cdcd_interface_t* p_cdc = &_cdcd_itf[i];
tu_memclr(p_cdc, ITF_MEM_RESET_SIZE);
if (!_cdcd_fifo_cfg.rx_persistent) {
if (!_cdcd_cfg.rx_persistent) {
tu_fifo_clear(&p_cdc->rx_ff);
}
if (!_cdcd_fifo_cfg.tx_persistent) {
if (!_cdcd_cfg.tx_persistent) {
tu_fifo_clear(&p_cdc->tx_ff);
}
tu_fifo_set_overwritable(&p_cdc->tx_ff, true);
tu_fifo_set_overwritable(&p_cdc->tx_ff, _cdcd_cfg.tx_overwritabe_if_not_connected);
}
}
@@ -414,8 +412,12 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, const tusb_control_requ
p_cdc->line_state = (uint8_t) request->wValue;
// Disable fifo overwriting if DTR bit is set
tu_fifo_set_overwritable(&p_cdc->tx_ff, !dtr);
// If enabled: fifo overwriting is disabled if DTR bit is set and vice versa
if (_cdcd_cfg.tx_overwritabe_if_not_connected) {
tu_fifo_set_overwritable(&p_cdc->tx_ff, !dtr);
} else {
tu_fifo_set_overwritable(&p_cdc->tx_ff, false);
}
TU_LOG_DRV(" Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts);
@@ -496,7 +498,7 @@ bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
// xferred_bytes is multiple of EP Packet size and not zero
if (!tu_fifo_count(&p_cdc->tx_ff) && xferred_bytes && (0 == (xferred_bytes & (BULK_PACKET_SIZE - 1)))) {
if (usbd_edpt_claim(rhport, p_cdc->ep_in)) {
usbd_edpt_xfer(rhport, p_cdc->ep_in, NULL, 0);
TU_ASSERT(usbd_edpt_xfer(rhport, p_cdc->ep_in, NULL, 0));
}
}
}

22
src/class/cdc/cdc_device.h
View File

@@ -48,14 +48,24 @@
//--------------------------------------------------------------------+
// Driver Configuration
//--------------------------------------------------------------------+
typedef struct TU_ATTR_PACKED {
uint8_t rx_persistent : 1; // keep rx fifo on bus reset or disconnect
uint8_t tx_persistent : 1; // keep tx fifo on bus reset or disconnect
} tud_cdc_configure_fifo_t;
uint8_t rx_persistent : 1; // keep rx fifo data even with bus reset or disconnect
uint8_t tx_persistent : 1; // keep tx fifo data even with reset or disconnect
uint8_t tx_overwritabe_if_not_connected : 1; // if not connected, tx fifo can be overwritten
} tud_cdc_configure_t;
// Configure CDC FIFOs behavior
bool tud_cdc_configure_fifo(tud_cdc_configure_fifo_t const* cfg);
#define TUD_CDC_CONFIGURE_DEFAULT() { \
.rx_persistent = 0, \
.tx_persistent = 0, \
.tx_overwritabe_if_not_connected = 1, \
}
// Configure CDC driver behavior
bool tud_cdc_configure(const tud_cdc_configure_t* driver_cfg);
// Backward compatible
#define tud_cdc_configure_fifo_t tud_cdc_configure_t
#define tud_cdc_configure_fifo tud_cdc_configure
//--------------------------------------------------------------------+
// Application API (Multiple Ports) i.e. CFG_TUD_CDC > 1

7
src/common/tusb_fifo.c
View File

@@ -916,8 +916,11 @@ bool tu_fifo_clear(tu_fifo_t *f)
Overwritable mode the fifo is set to
*/
/******************************************************************************/
bool tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable)
{
bool tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable) {
if (f->overwritable == overwritable) {
return true;
}
_ff_lock(f->mutex_wr);
_ff_lock(f->mutex_rd);

9
src/device/usbd.c
View File

@@ -561,8 +561,7 @@ static void usbd_reset(uint8_t rhport) {
}
bool tud_task_event_ready(void) {
// Skip if stack is not initialized
if (!tud_inited()) return false;
TU_VERIFY(tud_inited()); // Skip if stack is not initialized
return !osal_queue_empty(_usbd_q);
}
@@ -684,7 +683,9 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) {
case USBD_EVENT_FUNC_CALL:
TU_LOG_USBD("\r\n");
if (event.func_call.func) event.func_call.func(event.func_call.param);
if (event.func_call.func) {
event.func_call.func(event.func_call.param);
}
break;
case DCD_EVENT_SOF:
@@ -701,7 +702,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) {
#if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO
// return if there is no more events, for application to run other background
if (osal_queue_empty(_usbd_q)) return;
if (osal_queue_empty(_usbd_q)) { return; }
#endif
}
}

3
src/host/hcd.h
View File

@@ -165,6 +165,9 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr);
// Open an endpoint
bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * ep_desc);
// Close an endpoint
bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr);
// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen);

83
src/host/usbh.c
View File

@@ -52,21 +52,25 @@ enum {
// Weak stubs: invoked if no strong implementation is available
//--------------------------------------------------------------------+
TU_ATTR_WEAK bool hcd_deinit(uint8_t rhport) {
(void) rhport;
return false;
(void) rhport; return false;
}
TU_ATTR_WEAK bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
(void) rhport;
(void) cfg_id;
(void) cfg_param;
(void) rhport; (void) cfg_id; (void) cfg_param;
return false;
}
TU_ATTR_WEAK void tuh_enum_descriptor_device_cb(uint8_t daddr, const tusb_desc_device_t *desc_device) {
(void) daddr; (void) desc_device;
}
TU_ATTR_WEAK bool tuh_enum_descriptor_configuration_cb(uint8_t daddr, uint8_t cfg_index, const tusb_desc_configuration_t *desc_config) {
(void) daddr; (void) cfg_index; (void) desc_config;
return true;
}
TU_ATTR_WEAK void tuh_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr) {
(void) rhport;
(void) eventid;
(void) in_isr;
(void) rhport; (void) eventid; (void) in_isr;
}
TU_ATTR_WEAK bool hcd_dcache_clean(const void* addr, uint32_t data_size) {
@@ -126,6 +130,7 @@ typedef struct {
uint8_t i_manufacturer;
uint8_t i_product;
uint8_t i_serial;
uint8_t bNumConfigurations;
// Configuration Descriptor
// uint8_t interface_count; // bNumInterfaces alias
@@ -230,7 +235,6 @@ static usbh_class_driver_t const usbh_class_drivers[] = {
};
enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) };
enum { CONFIG_NUM = 1 }; // default to use configuration 1
// Additional class drivers implemented by application
tu_static usbh_class_driver_t const * _app_driver = NULL;
@@ -516,7 +520,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) {
// Loop until there is no more events in the queue
while (1) {
hcd_event_t event;
if (!osal_queue_receive(_usbh_q, &event, timeout_ms)) return;
if (!osal_queue_receive(_usbh_q, &event, timeout_ms)) { return; }
switch (event.event_id) {
case HCD_EVENT_DEVICE_ATTACH:
@@ -990,6 +994,12 @@ bool tuh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const* desc_ep) {
return hcd_edpt_open(usbh_get_rhport(dev_addr), dev_addr, desc_ep);
}
bool tuh_edpt_close(uint8_t daddr, uint8_t ep_addr) {
TU_VERIFY(0 != tu_edpt_number(ep_addr)); // cannot close EP0
tuh_edpt_abort_xfer(daddr, ep_addr); // abort any pending transfer
return hcd_edpt_close(usbh_get_rhport(daddr), daddr, ep_addr);
}
bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr) {
usbh_device_t* dev = get_device(dev_addr);
TU_VERIFY(dev);
@@ -1372,8 +1382,8 @@ enum {
ENUM_CONFIG_DRIVER
};
static bool enum_request_set_addr(void);
static bool _parse_configuration_descriptor (uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg);
static bool enum_request_set_addr(tusb_desc_device_t const* desc_device);
static bool enum_parse_configuration_desc (uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg);
static void enum_full_complete(void);
// process device enumeration
@@ -1489,7 +1499,7 @@ static void process_enumeration(tuh_xfer_t* xfer) {
#endif
case ENUM_SET_ADDR:
enum_request_set_addr();
enum_request_set_addr((tusb_desc_device_t*) _usbh_epbuf.ctrl);
break;
case ENUM_GET_DEVICE_DESC: {
@@ -1523,6 +1533,9 @@ static void process_enumeration(tuh_xfer_t* xfer) {
dev->i_manufacturer = desc_device->iManufacturer;
dev->i_product = desc_device->iProduct;
dev->i_serial = desc_device->iSerialNumber;
dev->bNumConfigurations = desc_device->bNumConfigurations;
tuh_enum_descriptor_device_cb(daddr, desc_device); // callback
tuh_descriptor_get_string_langid(daddr, _usbh_epbuf.ctrl, CFG_TUH_ENUMERATION_BUFSIZE,
process_enumeration, ENUM_GET_STRING_MANUFACTURER);
@@ -1574,8 +1587,8 @@ static void process_enumeration(tuh_xfer_t* xfer) {
case ENUM_GET_9BYTE_CONFIG_DESC: {
// Get 9-byte for total length
uint8_t const config_idx = CONFIG_NUM - 1;
TU_LOG_USBH("Get Configuration[0] Descriptor (9 bytes)\r\n");
uint8_t const config_idx = 0;
TU_LOG_USBH("Get Configuration[%u] Descriptor (9 bytes)\r\n", config_idx);
TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_epbuf.ctrl, 9,
process_enumeration, ENUM_GET_FULL_CONFIG_DESC),);
break;
@@ -1585,25 +1598,32 @@ static void process_enumeration(tuh_xfer_t* xfer) {
uint8_t const* desc_config = _usbh_epbuf.ctrl;
// Use offsetof to avoid pointer to the odd/misaligned address
uint16_t const total_len = tu_le16toh(
tu_unaligned_read16(desc_config + offsetof(tusb_desc_configuration_t, wTotalLength)));
uint16_t const total_len = tu_le16toh(tu_unaligned_read16(desc_config + offsetof(tusb_desc_configuration_t, wTotalLength)));
// TODO not enough buffer to hold configuration descriptor
TU_ASSERT(total_len <= CFG_TUH_ENUMERATION_BUFSIZE,);
// Get full configuration descriptor
uint8_t const config_idx = CONFIG_NUM - 1;
TU_LOG_USBH("Get Configuration[0] Descriptor\r\n");
uint8_t const config_idx = (uint8_t) tu_le16toh(xfer->setup->wIndex);
TU_LOG_USBH("Get Configuration[%u] Descriptor\r\n", config_idx);
TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_epbuf.ctrl, total_len,
process_enumeration, ENUM_SET_CONFIG),);
break;
}
case ENUM_SET_CONFIG:
// tuh_desc_configuration_cb(daddr, CONFIG_NUM-1, (const tusb_desc_configuration_t*) _usbh_epbuf.ctrl);
TU_ASSERT(tuh_configuration_set(daddr, CONFIG_NUM, process_enumeration, ENUM_CONFIG_DRIVER),);
case ENUM_SET_CONFIG: {
uint8_t config_idx = (uint8_t) tu_le16toh(xfer->setup->wIndex);
if (tuh_enum_descriptor_configuration_cb(daddr, config_idx, (const tusb_desc_configuration_t*) _usbh_epbuf.ctrl)) {
TU_ASSERT(tuh_configuration_set(daddr, config_idx+1, process_enumeration, ENUM_CONFIG_DRIVER),);
} else {
config_idx++;
TU_ASSERT(config_idx < dev->bNumConfigurations,);
TU_LOG_USBH("Get Configuration[%u] Descriptor (9 bytes)\r\n", config_idx);
TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_epbuf.ctrl, 9,
process_enumeration, ENUM_GET_FULL_CONFIG_DESC),);
}
break;
}
case ENUM_CONFIG_DRIVER: {
TU_LOG_USBH("Device configured\r\n");
@@ -1613,7 +1633,7 @@ static void process_enumeration(tuh_xfer_t* xfer) {
// Parse configuration & set up drivers
// driver_open() must not make any usb transfer
TU_ASSERT(_parse_configuration_descriptor(daddr, (tusb_desc_configuration_t*) _usbh_epbuf.ctrl),);
TU_ASSERT(enum_parse_configuration_desc(daddr, (tusb_desc_configuration_t*) _usbh_epbuf.ctrl),);
// Start the Set Configuration process for interfaces (itf = TUSB_INDEX_INVALID_8)
// Since driver can perform control transfer within its set_config, this is done asynchronously.
@@ -1624,14 +1644,11 @@ static void process_enumeration(tuh_xfer_t* xfer) {
}
default:
// stop enumeration if unknown state
enum_full_complete();
enum_full_complete(); // stop enumeration if unknown state
break;
}
}
static bool enum_new_device(hcd_event_t* event) {
_dev0.rhport = event->rhport;
_dev0.hub_addr = event->connection.hub_addr;
@@ -1701,9 +1718,7 @@ static uint8_t get_new_address(bool is_hub) {
return 0; // invalid address
}
static bool enum_request_set_addr(void) {
tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_epbuf.ctrl;
static bool enum_request_set_addr(tusb_desc_device_t const* desc_device) {
// Get new address
uint8_t const new_addr = get_new_address(desc_device->bDeviceClass == TUSB_CLASS_HUB);
TU_ASSERT(new_addr != 0);
@@ -1741,7 +1756,7 @@ static bool enum_request_set_addr(void) {
return true;
}
static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg) {
static bool enum_parse_configuration_desc(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg) {
usbh_device_t* dev = get_device(dev_addr);
uint16_t const total_len = tu_le16toh(desc_cfg->wTotalLength);
uint8_t const* desc_end = ((uint8_t const*) desc_cfg) + total_len;
@@ -1858,7 +1873,9 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) {
TU_LOG_USBH("HUB address = %u is mounted\r\n", dev_addr);
}else {
// Invoke callback if available
if (tuh_mount_cb) tuh_mount_cb(dev_addr);
if (tuh_mount_cb) {
tuh_mount_cb(dev_addr);
}
}
}
}

23
src/host/usbh.h
View File

@@ -33,6 +33,10 @@
#include "common/tusb_common.h"
#if CFG_TUH_MAX3421
#include "portable/analog/max3421/hcd_max3421.h"
#endif
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
@@ -100,10 +104,13 @@ typedef union {
//--------------------------------------------------------------------+
// Invoked when enumeration get device descriptor
// TU_ATTR_WEAK void tuh_descriptor_device_cb(uint8_t daddr, const tusb_desc_device_t *desc_device);
// Device is not ready to communicate yet, application can copy the descriptor if needed
void tuh_enum_descriptor_device_cb(uint8_t daddr, const tusb_desc_device_t *desc_device);
// Invoked when enumeration get configuration descriptor
// TU_ATTR_WEAK void tuh_desc_configuration_cb(uint8_t daddr, uint8_t cfg_index, const tusb_desc_configuration_t *desc_config);
// For multi-configuration device return false to skip, true to proceed with this configuration (may not be implemented yet)
// Device is not ready to communicate yet, application can copy the descriptor if needed
bool tuh_enum_descriptor_configuration_cb(uint8_t daddr, uint8_t cfg_index, const tusb_desc_configuration_t *desc_config);
// Invoked when a device is mounted (configured)
TU_ATTR_WEAK void tuh_mount_cb (uint8_t daddr);
@@ -155,8 +162,7 @@ bool tuh_inited(void);
void tuh_task_ext(uint32_t timeout_ms, bool in_isr);
// Task function should be called in main/rtos loop
TU_ATTR_ALWAYS_INLINE static inline
void tuh_task(void) {
TU_ATTR_ALWAYS_INLINE static inline void tuh_task(void) {
tuh_task_ext(UINT32_MAX, false);
}
@@ -197,16 +203,14 @@ bool tuh_mounted(uint8_t daddr);
bool tuh_connected(uint8_t daddr);
// Check if device is suspended
TU_ATTR_ALWAYS_INLINE static inline
bool tuh_suspended(uint8_t daddr) {
TU_ATTR_ALWAYS_INLINE static inline bool tuh_suspended(uint8_t daddr) {
// TODO implement suspend & resume on host
(void) daddr;
return false;
}
// Check if device is ready to communicate with
TU_ATTR_ALWAYS_INLINE static inline
bool tuh_ready(uint8_t daddr) {
TU_ATTR_ALWAYS_INLINE static inline bool tuh_ready(uint8_t daddr) {
return tuh_mounted(daddr) && !tuh_suspended(daddr);
}
@@ -227,6 +231,9 @@ bool tuh_edpt_xfer(tuh_xfer_t* xfer);
// Open a non-control endpoint
bool tuh_edpt_open(uint8_t daddr, tusb_desc_endpoint_t const * desc_ep);
// Close a non-control endpoint, it will abort any pending transfer
bool tuh_edpt_close(uint8_t daddr, uint8_t ep_addr);
// Abort a queued transfer. Note: it can only abort transfer that has not been started
// Return true if a queued transfer is aborted, false if there is no transfer to abort
bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr);

40
src/portable/analog/max3421/hcd_max3421.c
View File

@@ -252,28 +252,6 @@ static tuh_configure_max3421_t _tuh_cfg = {
.pinctl = 0, // default: negative edge interrupt
};
//--------------------------------------------------------------------+
// API: SPI transfer with MAX3421E
// - spi_cs_api(), spi_xfer_api(), int_api(): must be implemented by application
// - reg_read(), reg_write(): is implemented by this driver, can be used by application
//--------------------------------------------------------------------+
// API to control MAX3421 SPI CS
extern void tuh_max3421_spi_cs_api(uint8_t rhport, bool active);
// API to transfer data with MAX3421 SPI
// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only
extern bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes);
// API to enable/disable MAX3421 INTR pin interrupt
extern void tuh_max3421_int_api(uint8_t rhport, bool enabled);
// API to read MAX3421's register. Implemented by TinyUSB
uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr);
// API to write MAX3421's register. Implemented by TinyUSB
bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr);
//--------------------------------------------------------------------+
// SPI Commands and Helper
//--------------------------------------------------------------------+
@@ -632,6 +610,9 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e
if (daddr == 0 && ep_num == 0) {
ep = &_hcd_data.ep[0];
}else {
if (NULL != find_ep_not_addr0(daddr, ep_num, ep_dir)) {
return false; // endpoint already opened
}
ep = allocate_ep();
TU_ASSERT(ep);
ep->daddr = daddr;
@@ -645,6 +626,21 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e
return true;
}
bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
(void) rhport;
uint8_t const ep_num = tu_edpt_number(ep_addr);
tusb_dir_t const ep_dir = tu_edpt_dir(ep_addr);
max3421_ep_t * ep = find_ep_not_addr0(daddr, ep_num, ep_dir);
if (!ep) {
return false; // not opened
}
tu_memclr(ep, sizeof(max3421_ep_t));
return true;
}
/* The microcontroller repeatedly writes the SNDFIFO register R2 to load the FIFO with up to 64 data bytes.
* Then the microcontroller writes the SNDBC register, which this does three things:
* 1. Tells the MAX3421E SIE (Serial Interface Engine) how many bytes in the FIFO to send.

63
src/portable/analog/max3421/hcd_max3421.h Normal file
View File

@@ -0,0 +1,63 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2025 Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#ifndef TUSB_HCD_MAX3421_H
#define TUSB_HCD_MAX3421_H
#ifdef __cplusplus
extern "C" {
#endif
//--------------------------------------------------------------------+
// SPI transfer API with MAX3421E are implemented by application
// - spi_cs_api(), spi_xfer_api(), int_api()
//--------------------------------------------------------------------+
// API to control MAX3421 SPI CS
extern void tuh_max3421_spi_cs_api(uint8_t rhport, bool active);
// API to transfer data with MAX3421 SPI
// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only
extern bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes);
// API to enable/disable MAX3421 INTR pin interrupt
extern void tuh_max3421_int_api(uint8_t rhport, bool enabled);
//--------------------------------------------------------------------+
// API for read/write MAX3421 registers
// are implemented by this driver, can be used by application
//--------------------------------------------------------------------+
// API to read MAX3421's register. Implemented by TinyUSB
uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr);
// API to write MAX3421's register. Implemented by TinyUSB
bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr);
#ifdef __cplusplus
}
#endif
#endif

259
src/portable/ehci/ehci.c
View File

@@ -62,8 +62,7 @@
#define QHD_MAX (CFG_TUH_DEVICE_MAX*CFG_TUH_ENDPOINT_MAX + CFG_TUH_HUB)
#define QTD_MAX QHD_MAX
typedef struct
{
typedef struct {
ehci_link_t period_framelist[FRAMELIST_SIZE];
// TODO only implement 1 ms & 2 ms & 4 ms, 8 ms (framelist)
@@ -139,6 +138,12 @@ static ehci_qhd_t* qhd_get_from_addr (uint8_t dev_addr, uint8_t ep_addr);
static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
static void qhd_attach_qtd(ehci_qhd_t *qhd, ehci_qtd_t *qtd);
static void qhd_remove_qtd(ehci_qhd_t *qhd);
TU_ATTR_ALWAYS_INLINE static inline bool qhd_is_periodic(ehci_qhd_t const *qhd) {
return qhd->int_smask != 0;
}
TU_ATTR_ALWAYS_INLINE static inline uint8_t qhd_ep_addr(ehci_qhd_t const *qhd) {
return tu_edpt_addr(qhd->ep_number, qhd->pid);
}
TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t* qtd_control(uint8_t dev_addr);
TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t* qtd_find_free (void);
@@ -146,9 +151,10 @@ static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes)
TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_get_period_head(uint8_t rhport, uint32_t interval_ms);
TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* list_get_async_head(uint8_t rhport);
TU_ATTR_ALWAYS_INLINE static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type);
TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_next (ehci_link_t const *p_link);
static void list_remove_qhd_by_daddr(ehci_link_t* list_head, uint8_t dev_addr);
TU_ATTR_ALWAYS_INLINE static inline void list_insert (ehci_link_t *current, ehci_link_t *entry, uint8_t type);
TU_ATTR_ALWAYS_INLINE static inline void list_remove(ehci_link_t* head, ehci_link_t* prev, ehci_qhd_t* qhd);
static void list_remove_qhd_by_addr(ehci_link_t *list_head, uint8_t dev_addr, uint8_t ep_addr);
static void ehci_disable_schedule(ehci_registers_t* regs, bool is_period) {
// maybe have a timeout for status
@@ -175,15 +181,12 @@ static void ehci_enable_schedule(ehci_registers_t* regs, bool is_period) {
//--------------------------------------------------------------------+
// HCD API
//--------------------------------------------------------------------+
uint32_t hcd_frame_number(uint8_t rhport)
{
uint32_t hcd_frame_number(uint8_t rhport) {
(void) rhport;
return (ehci_data.uframe_number + ehci_data.regs->frame_index) >> 3;
}
void hcd_port_reset(uint8_t rhport)
{
void hcd_port_reset(uint8_t rhport) {
(void) rhport;
ehci_registers_t* regs = ehci_data.regs;
@@ -204,8 +207,7 @@ void hcd_port_reset(uint8_t rhport)
regs->portsc = portsc;
}
void hcd_port_reset_end(uint8_t rhport)
{
void hcd_port_reset_end(uint8_t rhport) {
(void) rhport;
ehci_registers_t* regs = ehci_data.regs;
@@ -221,32 +223,29 @@ void hcd_port_reset_end(uint8_t rhport)
regs->portsc = portsc;
}
bool hcd_port_connect_status(uint8_t rhport)
{
bool hcd_port_connect_status(uint8_t rhport) {
(void) rhport;
return ehci_data.regs->portsc_bm.current_connect_status;
}
tusb_speed_t hcd_port_speed_get(uint8_t rhport)
{
tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
(void) rhport;
return (tusb_speed_t) ehci_data.regs->portsc_bm.nxp_port_speed; // NXP specific port speed
}
// Close all opened endpoint belong to this device
void hcd_device_close(uint8_t rhport, uint8_t daddr)
{
void hcd_device_close(uint8_t rhport, uint8_t daddr) {
// skip dev0
if (daddr == 0) {
return;
}
// Remove from async list
list_remove_qhd_by_daddr((ehci_link_t *) list_get_async_head(rhport), daddr);
// Remove from async list all endpoints of this device
list_remove_qhd_by_addr((ehci_link_t *) list_get_async_head(rhport), daddr, TUSB_INDEX_INVALID_8);
// Remove from all interval period list
for(uint8_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++) {
list_remove_qhd_by_daddr((ehci_link_t *) &ehci_data.period_head_arr[i], daddr);
// Remove from all interval period list of this device
for (uint8_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++) {
list_remove_qhd_by_addr((ehci_link_t *) &ehci_data.period_head_arr[i], daddr, TUSB_INDEX_INVALID_8);
}
// Async doorbell (EHCI 4.8.2 for operational details)
@@ -358,12 +357,10 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
}
#if 0
static void ehci_stop(uint8_t rhport)
{
static void ehci_stop(uint8_t rhport) {
(void) rhport;
ehci_registers_t* regs = ehci_data.regs;
regs->command_bm.run_stop = 0;
// USB Spec: controller has to stop within 16 uframe = 2 frames
@@ -375,41 +372,44 @@ static void ehci_stop(uint8_t rhport)
// Endpoint API
//--------------------------------------------------------------------+
bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
{
(void) rhport;
bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) {
// TODO not support ISO yet
TU_ASSERT (ep_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
//------------- Prepare Queue Head -------------//
ehci_qhd_t *p_qhd = (ep_desc->bEndpointAddress == 0) ? qhd_control(dev_addr) : qhd_find_free();
ehci_qhd_t *p_qhd;
if (ep_desc->bEndpointAddress == 0) {
p_qhd = qhd_control(dev_addr);
} else {
TU_VERIFY(NULL == qhd_get_from_addr(dev_addr, ep_desc->bEndpointAddress)); // ep not opened yet
p_qhd = qhd_find_free();
}
TU_ASSERT(p_qhd);
qhd_init(p_qhd, dev_addr, ep_desc);
// control of dev0 is always present as async head
if ( dev_addr == 0 ) return true;
// control of dev0 always exists as async head
if (dev_addr == 0) {
return true;
}
// Insert to list
ehci_link_t * list_head = NULL;
switch (ep_desc->bmAttributes.xfer)
{
switch (ep_desc->bmAttributes.xfer) {
case TUSB_XFER_CONTROL:
case TUSB_XFER_BULK:
list_head = (ehci_link_t*) list_get_async_head(rhport);
break;
list_head = (ehci_link_t *) list_get_async_head(rhport);
break;
case TUSB_XFER_INTERRUPT:
list_head = list_get_period_head(rhport, p_qhd->interval_ms);
break;
break;
case TUSB_XFER_ISOCHRONOUS:
// TODO iso is not supported
break;
break;
default: break;
default:
break;
}
TU_ASSERT(list_head);
@@ -421,8 +421,23 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
return true;
}
bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
{
bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
ehci_qhd_t* qhd = qhd_get_from_addr(daddr, ep_addr);
TU_VERIFY(qhd != NULL);
ehci_link_t * list_head;
if (qhd_is_periodic(qhd)) {
// interrupt endpoint
list_head = list_get_period_head(rhport, qhd->interval_ms);;
} else {
list_head = (ehci_link_t *) list_get_async_head(rhport);
}
list_remove_qhd_by_addr(list_head, daddr, ep_addr);
return true;
}
bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) {
(void) rhport;
ehci_qhd_t* qhd = &ehci_data.control[dev_addr].qhd;
@@ -444,14 +459,14 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
return true;
}
bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
{
bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
(void) rhport;
uint8_t const epnum = tu_edpt_number(ep_addr);
uint8_t const dir = tu_edpt_dir(ep_addr);
ehci_qhd_t* qhd = qhd_get_from_addr(dev_addr, ep_addr);
TU_VERIFY(qhd != NULL);
ehci_qtd_t* qtd;
if (epnum == 0) {
@@ -540,8 +555,7 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
// This isr mean it is safe to modify previously removed queue head from async list.
// In tinyusb, queue head is only removed when device is unplugged.
TU_ATTR_ALWAYS_INLINE static inline
void async_advance_isr(uint8_t rhport)
{
void async_advance_isr(uint8_t rhport) {
(void) rhport;
ehci_qhd_t *qhd_pool = ehci_data.qhd_pool;
@@ -612,8 +626,7 @@ void qhd_xfer_complete_isr(ehci_qhd_t * qhd) {
}
TU_ATTR_ALWAYS_INLINE static inline
void proccess_async_xfer_isr(ehci_qhd_t * const list_head)
{
void proccess_async_xfer_isr(ehci_qhd_t * const list_head) {
ehci_qhd_t *qhd = list_head;
do {
@@ -623,8 +636,7 @@ void proccess_async_xfer_isr(ehci_qhd_t * const list_head)
}
TU_ATTR_ALWAYS_INLINE static inline
void process_period_xfer_isr(uint8_t rhport, uint32_t interval_ms)
{
void process_period_xfer_isr(uint8_t rhport, uint32_t interval_ms) {
uint32_t const period_1ms_addr = (uint32_t) list_get_period_head(rhport, 1u);
ehci_link_t next_link = *list_get_period_head(rhport, interval_ms);
@@ -726,51 +738,55 @@ TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_next(ehci_link_t const *p_
return (ehci_link_t*) tu_align32(p_link->address);
}
TU_ATTR_ALWAYS_INLINE static inline void list_insert(ehci_link_t *current, ehci_link_t *new, uint8_t new_type)
{
new->address = current->address;
current->address = ((uint32_t) new) | (new_type << 1);
TU_ATTR_ALWAYS_INLINE static inline void list_insert(ehci_link_t *current, ehci_link_t *entry, uint8_t type) {
entry->address = current->address;
current->address = ((uint32_t) entry) | (type << 1);
}
// Remove all queue head belong to this device address
static void list_remove_qhd_by_daddr(ehci_link_t* list_head, uint8_t dev_addr) {
ehci_link_t* prev = list_head;
// Remove a queue head from the list.
// Per EHCI 4.8.2 the removed qhd's next is linked to list head (which always reachable by Host Controller)
// TODO support iTD/siTD
TU_ATTR_ALWAYS_INLINE static inline void list_remove(ehci_link_t* head, ehci_link_t* prev, ehci_qhd_t* qhd) {
// TODO deactivate all TD, wait for QHD to inactive before removal
prev->address = qhd->next.address;
// link the removed qhd's next to list head
qhd->next.address = ((uint32_t) head) | (EHCI_QTYPE_QHD << 1);
if (qhd_is_periodic(qhd)) {
// period list queue element is guarantee to be free in the next frame (1 ms)
qhd->used = 0;
} else {
// async list use async advance handshake. Mark as removing, will completely re-usable when async advance isr occurs
qhd->removing = 1;
}
hcd_dcache_clean(qhd, sizeof(ehci_qhd_t));
hcd_dcache_clean(prev, sizeof(ehci_qhd_t));
}
// Remove queue head belong to this device address
static void list_remove_qhd_by_addr(ehci_link_t *list_head, uint8_t dev_addr, uint8_t ep_addr) {
ehci_link_t *prev = list_head;
while (prev && !prev->terminate) {
ehci_qhd_t* qhd = (ehci_qhd_t*) (uintptr_t) list_next(prev);
ehci_qhd_t *qhd = (ehci_qhd_t *) (uintptr_t) list_next(prev);
// done if loop back to head
if ( (uintptr_t) qhd == (uintptr_t) list_head) {
if ((uintptr_t) qhd == (uintptr_t) list_head) {
break;
}
if ( qhd->dev_addr == dev_addr ) {
// TODO deactivate all TD, wait for QHD to inactive before removal
prev->address = qhd->next.address;
// EHCI 4.8.2 link the removed qhd's next to async head (which always reachable by Host Controller)
qhd->next.address = ((uint32_t) list_head) | (EHCI_QTYPE_QHD << 1);
if ( qhd->int_smask )
{
// period list queue element is guarantee to be free in the next frame (1 ms)
qhd->used = 0;
}else
{
// async list use async advance handshake
// mark as removing, will completely re-usable when async advance isr occurs
qhd->removing = 1;
}
hcd_dcache_clean(qhd, sizeof(ehci_qhd_t));
hcd_dcache_clean(prev, sizeof(ehci_qhd_t));
}else {
// ep_addr is 0xff means all endpoints of this device address
if (qhd->dev_addr == dev_addr &&
(ep_addr == TUSB_INDEX_INVALID_8 || qhd_ep_addr(qhd) == ep_addr)) {
list_remove(list_head, prev, qhd);
} else {
prev = list_next(prev);
}
}
}
//--------------------------------------------------------------------+
// Queue Header helper
//--------------------------------------------------------------------+
@@ -782,8 +798,10 @@ TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* qhd_control(uint8_t dev_addr) {
// Find a free queue head
TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t *qhd_find_free(void) {
for ( uint32_t i = 0; i < QHD_MAX; i++ ) {
if ( !ehci_data.qhd_pool[i].used ) return &ehci_data.qhd_pool[i];
for (uint32_t i = 0; i < QHD_MAX; i++) {
if (!ehci_data.qhd_pool[i].used) {
return &ehci_data.qhd_pool[i];
}
}
return NULL;
}
@@ -800,10 +818,9 @@ static ehci_qhd_t *qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr) {
}
ehci_qhd_t *qhd_pool = ehci_data.qhd_pool;
for ( uint32_t i = 0; i < QHD_MAX; i++ ) {
if ( (qhd_pool[i].dev_addr == dev_addr) &&
ep_addr == tu_edpt_addr(qhd_pool[i].ep_number, qhd_pool[i].pid) ) {
for (uint32_t i = 0; i < QHD_MAX; i++) {
if ((qhd_pool[i].dev_addr == dev_addr) &&
ep_addr == qhd_ep_addr(&qhd_pool[i])) {
return &qhd_pool[i];
}
}
@@ -812,8 +829,7 @@ static ehci_qhd_t *qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr) {
}
// Init queue head with endpoint descriptor
static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
{
static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) {
// address 0 is used as async head, which always on the list --> cannot be cleared (ehci halted otherwise)
if (dev_addr != 0) {
tu_memclr(p_qhd, sizeof(ehci_qhd_t));
@@ -830,39 +846,43 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c
p_qhd->ep_number = tu_edpt_number(ep_desc->bEndpointAddress);
p_qhd->ep_speed = devtree_info.speed;
p_qhd->data_toggle_control= (xfer_type == TUSB_XFER_CONTROL) ? 1 : 0;
p_qhd->head_list_flag = (dev_addr == 0) ? 1 : 0; // addr0's endpoint is the static asyn list head
p_qhd->head_list_flag = (dev_addr == 0) ? 1 : 0; // addr0's endpoint is the static async list head
p_qhd->max_packet_size = tu_edpt_packet_size(ep_desc);
p_qhd->fl_ctrl_ep_flag = ((xfer_type == TUSB_XFER_CONTROL) && (p_qhd->ep_speed != TUSB_SPEED_HIGH)) ? 1 : 0;
p_qhd->nak_reload = 0;
// Bulk/Control -> smask = cmask = 0
// TODO Isochronous
if (TUSB_XFER_INTERRUPT == xfer_type)
{
if (TUSB_SPEED_HIGH == p_qhd->ep_speed)
{
TU_ASSERT( interval <= 16, );
if ( interval < 4) // sub millisecond interval
{
p_qhd->interval_ms = 0;
p_qhd->int_smask = (interval == 1) ? TU_BIN8(11111111) :
(interval == 2) ? TU_BIN8(10101010) : TU_BIN8(01000100);
}else
{
p_qhd->interval_ms = (uint8_t) tu_min16( 1 << (interval-4), 255 );
p_qhd->int_smask = TU_BIT(interval % 8);
switch (xfer_type) {
case TUSB_XFER_CONTROL:
case TUSB_XFER_BULK:
p_qhd->int_smask = p_qhd->fl_int_cmask = 0;
break;
case TUSB_XFER_INTERRUPT:
if (TUSB_SPEED_HIGH == p_qhd->ep_speed) {
TU_ASSERT(interval <= 16, );
if (interval < 4) {
// sub millisecond interval
p_qhd->interval_ms = 0;
p_qhd->int_smask = (interval == 1) ? TU_BIN8(11111111) :
(interval == 2) ? TU_BIN8(10101010): TU_BIN8(01000100);
} else {
p_qhd->interval_ms = (uint8_t) tu_min16(1 << (interval - 4), 255);
p_qhd->int_smask = TU_BIT(interval % 8);
}
} else {
TU_ASSERT(0 != interval, );
// Full/Low: 4.12.2.1 (EHCI) case 1 schedule start split at 1 us & complete split at 2,3,4 uframes
p_qhd->int_smask = 0x01;
p_qhd->fl_int_cmask = TU_BIN8(11100);
p_qhd->interval_ms = interval;
}
}else
{
TU_ASSERT( 0 != interval, );
// Full/Low: 4.12.2.1 (EHCI) case 1 schedule start split at 1 us & complete split at 2,3,4 uframes
p_qhd->int_smask = 0x01;
p_qhd->fl_int_cmask = TU_BIN8(11100);
p_qhd->interval_ms = interval;
}
}else
{
p_qhd->int_smask = p_qhd->fl_int_cmask = 0;
break;
case TUSB_XFER_ISOCHRONOUS:
// TODO not support ISO yet
break;
default: break;
}
p_qhd->fl_hub_addr = devtree_info.hub_addr;
@@ -880,8 +900,7 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c
p_qhd->qtd_overlay.next.terminate = 1;
p_qhd->qtd_overlay.alternate.terminate = 1;
if (TUSB_XFER_BULK == xfer_type && p_qhd->ep_speed == TUSB_SPEED_HIGH && p_qhd->pid == EHCI_PID_OUT)
{
if (TUSB_XFER_BULK == xfer_type && p_qhd->ep_speed == TUSB_SPEED_HIGH && p_qhd->pid == EHCI_PID_OUT) {
p_qhd->qtd_overlay.ping_err = 1; // do PING for Highspeed Bulk OUT, EHCI section 4.11
}
}

280
src/portable/ehci/ehci.h
View File

@@ -49,15 +49,14 @@
// TODO merge OHCI with EHCI
enum {
EHCI_MAX_ITD = 4,
EHCI_MAX_ITD = 4,
EHCI_MAX_SITD = 16
};
//--------------------------------------------------------------------+
// EHCI Data Structure
//--------------------------------------------------------------------+
enum
{
enum {
EHCI_QTYPE_ITD = 0 ,
EHCI_QTYPE_QHD ,
EHCI_QTYPE_SITD ,
@@ -65,8 +64,7 @@ enum
};
/// EHCI PID
enum
{
enum {
EHCI_PID_OUT = 0 ,
EHCI_PID_IN ,
EHCI_PID_SETUP
@@ -74,187 +72,182 @@ enum
/// Link pointer
typedef union {
uint32_t address;
struct {
uint32_t terminate : 1;
uint32_t type : 2;
};
}ehci_link_t;
uint32_t address;
struct {
uint32_t terminate : 1;
uint32_t type : 2;
};
} ehci_link_t;
TU_VERIFY_STATIC( sizeof(ehci_link_t) == 4, "size is not correct" );
/// Queue Element Transfer Descriptor
/// Qtd is used to declare overlay in ehci_qhd_t -> cannot be declared with TU_ATTR_ALIGNED(32)
typedef struct
{
// Word 0: Next QTD Pointer
ehci_link_t next;
typedef struct {
// Word 0 Next QTD Pointer
ehci_link_t next;
// Word 1: Alternate Next QTD Pointer (not used)
union{
ehci_link_t alternate;
struct {
uint32_t : 5;
uint32_t used : 1;
uint32_t : 10;
uint32_t expected_bytes : 16;
};
};
// Word 1 Alternate Next QTD Pointer (not used)
union {
ehci_link_t alternate;
struct {
uint32_t : 5;
uint32_t used : 1;
uint32_t : 10;
uint32_t expected_bytes : 16;
};
};
// Word 2: qTQ Token
volatile uint32_t ping_err : 1 ; ///< For Highspeed: 0 Out, 1 Ping. Full/Slow used as error indicator
volatile uint32_t non_hs_split_state : 1 ; ///< Used by HC to track the state of split transaction
volatile uint32_t non_hs_missed_uframe : 1 ; ///< HC misses a complete split transaction
volatile uint32_t xact_err : 1 ; ///< Error (Timeout, CRC, Bad PID ... )
volatile uint32_t babble_err : 1 ; ///< Babble detected, also set Halted bit to 1
volatile uint32_t buffer_err : 1 ; ///< Data overrun/underrun error
volatile uint32_t halted : 1 ; ///< Serious error or STALL received
volatile uint32_t active : 1 ; ///< Start transfer, clear by HC when complete
// Word 2 qTQ Token
volatile uint32_t ping_err : 1; // For Highspeed: 0 Out, 1 Ping. Full/Slow used as error indicator
volatile uint32_t non_hs_split_state : 1; // Used by HC to track the state of split transaction
volatile uint32_t non_hs_missed_uframe : 1; // HC misses a complete split transaction
volatile uint32_t xact_err : 1; // Error (Timeout, CRC, Bad PID ... )
volatile uint32_t babble_err : 1; // Babble detected, also set Halted bit to 1
volatile uint32_t buffer_err : 1; // Data overrun/underrun error
volatile uint32_t halted : 1; // Serious error or STALL received
volatile uint32_t active : 1; // Start transfer, clear by HC when complete
uint32_t pid : 2 ; ///< 0: OUT, 1: IN, 2 Setup
volatile uint32_t err_count : 2 ; ///< Error Counter of consecutive errors
volatile uint32_t current_page : 3 ; ///< Index into the qTD buffer pointer list
uint32_t int_on_complete : 1 ; ///< Interrupt on complete
volatile uint32_t total_bytes : 15 ; ///< Transfer bytes, decreased during transaction
volatile uint32_t data_toggle : 1 ; ///< Data Toggle bit
uint32_t pid : 2; // 0: OUT, 1: IN, 2 Setup
volatile uint32_t err_count : 2; // Error Counter of consecutive errors
volatile uint32_t current_page : 3; // Index into the qTD buffer pointer list
uint32_t int_on_complete : 1; // Interrupt on complete
volatile uint32_t total_bytes : 15; // Transfer bytes, decreased during transaction
volatile uint32_t data_toggle : 1; // Data Toggle bit
/// Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
uint32_t buffer[5];
// Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address.
// The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
uint32_t buffer[5];
} ehci_qtd_t;
TU_VERIFY_STATIC( sizeof(ehci_qtd_t) == 32, "size is not correct" );
/// Queue Head
typedef struct TU_ATTR_ALIGNED(32)
{
// Word 0: Next QHD
ehci_link_t next;
typedef struct TU_ATTR_ALIGNED(32) {
// Word 0 Next QHD
ehci_link_t next;
// Word 1: Endpoint Characteristics
uint32_t dev_addr : 7 ; ///< device address
uint32_t fl_inactive_next_xact : 1 ; ///< Only valid for Periodic with Full/Slow speed
uint32_t ep_number : 4 ; ///< EP number
uint32_t ep_speed : 2 ; ///< 0: Full, 1: Low, 2: High
uint32_t data_toggle_control : 1 ; ///< 0: use DT in qHD, 1: use DT in qTD
uint32_t head_list_flag : 1 ; ///< Head of the queue
uint32_t max_packet_size : 11 ; ///< Max packet size
uint32_t fl_ctrl_ep_flag : 1 ; ///< 1 if is Full/Low speed control endpoint
uint32_t nak_reload : 4 ; ///< Used by HC
// Word 1 Endpoint Characteristics
uint32_t dev_addr : 7; // device address
uint32_t fl_inactive_next_xact : 1; // Only valid for Periodic with Full/Slow speed
uint32_t ep_number : 4; // EP number
uint32_t ep_speed : 2; // Full (0), Low (1), High (2)
uint32_t data_toggle_control : 1; // 0 use DT in qHD, 1 use DT in qTD
uint32_t head_list_flag : 1; // Head of the queue
uint32_t max_packet_size : 11; // Max packet size
uint32_t fl_ctrl_ep_flag : 1; // 1 if is Full/Low speed control endpoint
uint32_t nak_reload : 4; // Used by HC
// Word 2: Endpoint Capabilities
uint32_t int_smask : 8 ; ///< Interrupt Schedule Mask
uint32_t fl_int_cmask : 8 ; ///< Split Completion Mask for Full/Slow speed
uint32_t fl_hub_addr : 7 ; ///< Hub Address for Full/Slow speed
uint32_t fl_hub_port : 7 ; ///< Hub Port for Full/Slow speed
uint32_t mult : 2 ; ///< Transaction per micro frame
// Word 2 Endpoint Capabilities
uint32_t int_smask : 8; // Interrupt Schedule Mask
uint32_t fl_int_cmask : 8; // Split Completion Mask for Full/Slow speed
uint32_t fl_hub_addr : 7; // Hub Address for Full/Slow speed
uint32_t fl_hub_port : 7; // Hub Port for Full/Slow speed
uint32_t mult : 2; // Transaction per micro frame
// Word 3: Current qTD Pointer
volatile uint32_t qtd_addr;
// Word 3 Current qTD Pointer
volatile uint32_t qtd_addr;
// Word 4-11: Transfer Overlay
volatile ehci_qtd_t qtd_overlay;
// Word 4-11 Transfer Overlay
volatile ehci_qtd_t qtd_overlay;
//--------------------------------------------------------------------+
/// Due to the fact QHD is 32 bytes aligned but occupies only 48 bytes
/// thus there are 16 bytes padding free that we can make use of.
//--------------------------------------------------------------------+
uint8_t used;
uint8_t removing; // removed from asyn list, waiting for async advance
uint8_t pid;
uint8_t interval_ms; // polling interval in frames (or millisecond)
/// Due to the fact QHD is 32 bytes aligned but occupies only 48 bytes
/// thus there are 16 bytes padding free that we can make use of.
//--------------------------------------------------------------------+
uint8_t used;
uint8_t removing;// removed from asyn list, waiting for async advance
uint8_t pid;
uint8_t interval_ms;// polling interval in frames (or millisecond)
uint8_t TU_RESERVED[4];
uint8_t TU_RESERVED[4];
// Attached TD management, note usbh will only queue 1 TD per QHD.
// buffer for dcache invalidate since td's buffer is modified by HC and finding initial buffer address is not trivial
uint32_t attached_buffer;
ehci_qtd_t * volatile attached_qtd;
ehci_qtd_t *volatile attached_qtd;
} ehci_qhd_t;
TU_VERIFY_STATIC( sizeof(ehci_qhd_t) == 64, "size is not correct" );
/// Highspeed Isochronous Transfer Descriptor (section 3.3)
typedef struct TU_ATTR_ALIGNED(32) {
// Word 0: Next Link Pointer
ehci_link_t next;
// Word 0: Next Link Pointer
ehci_link_t next;
// Word 1-8: iTD Transaction Status and Control List
struct {
// iTD Control
volatile uint32_t offset : 12 ; ///< This field is a value that is an offset, expressed in bytes, from the beginning of a buffer.
volatile uint32_t page_select : 3 ; ///< These bits are set by software to indicate which of the buffer page pointers the offset field in this slot should be concatenated to produce the starting memory address for this transaction. The valid range of values for this field is 0 to 6
uint32_t int_on_complete : 1 ; ///< If this bit is set to a one, it specifies that when this transaction completes, the Host Controller should issue an interrupt at the next interrupt threshold
volatile uint32_t length : 12 ; ///< For an OUT, this field is the number of data bytes the host controller will send during the transaction. The host controller is not required to update this field to reflect the actual number of bytes transferred during the transfer
///< For an IN, the initial value of the field is the number of bytes the host expects the endpoint to deliver. During the status update, the host controller writes back the number of bytes successfully received. The value in this register is the actual byte count
// iTD Status
volatile uint32_t error : 1 ; ///< Set to a one by the Host Controller during status update in the case where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.). This bit may only be set for isochronous IN transactions.
volatile uint32_t babble_err : 1 ; ///< Set to a 1 by the Host Controller during status update when a babble is detected during the transaction
volatile uint32_t buffer_err : 1 ; ///< Set to a 1 by the Host Controller during status update to indicate that the Host Controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (underrun).
volatile uint32_t active : 1 ; ///< Set to 1 by software to enable the execution of an isochronous transaction by the Host Controller
} xact[8];
// Word 1-8: iTD Transaction Status and Control List
struct {
// iTD Control
volatile uint32_t offset : 12; // offset in bytes, from the beginning of a buffer.
volatile uint32_t page_select : 3; // buffer page pointers the offset field in this slot should be concatenated to produce the starting memory address for this transaction. The valid range of values for this field is 0 to 6
uint32_t int_on_complete : 1; // If this bit is set to a one, it specifies that when this transaction completes, the Host Controller should issue an interrupt at the next interrupt threshold
volatile uint32_t length : 12; // For an OUT, this field is the number of data bytes the host controller will send during the transaction. The host controller is not required to update this field to reflect the actual number of bytes transferred during the transfer
// For an IN, the initial value of the field is the number of bytes the host expects the endpoint to deliver. During the status update, the host controller writes back the number of bytes successfully received. The value in this register is the actual byte count
// iTD Status
volatile uint32_t error : 1; // Set to a one by the Host Controller during status update in the case where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.). This bit may only be set for isochronous IN transactions.
volatile uint32_t babble_err : 1; // Set to a 1 by the Host Controller during status update when a babble is detected during the transaction
volatile uint32_t buffer_err : 1; // Set to a 1 by the Host Controller during status update to indicate that the Host Controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (underrun).
volatile uint32_t active : 1; // Set to 1 by software to enable the execution of an isochronous transaction by the Host Controller
} xact[8];
// Word 9-15 Buffer Page Pointer List (Plus)
uint32_t BufferPointer[7];
// Word 9-15 Buffer Page Pointer List (Plus)
uint32_t BufferPointer[7];
// // FIXME: Store meta data into buffer pointer reserved for saving memory
// /*---------- HCD Area ----------*/
// uint32_t used;
// uint32_t IhdIdx;
// uint32_t reserved[6];
// FIXME: Store meta data into buffer pointer reserved for saving memory
//---------- HCD Area ----------
// uint32_t used;
// uint32_t IhdIdx;
// uint32_t reserved[6];
} ehci_itd_t;
TU_VERIFY_STATIC( sizeof(ehci_itd_t) == 64, "size is not correct" );
/// Split (Full-Speed) Isochronous Transfer Descriptor
typedef struct TU_ATTR_ALIGNED(32)
{
typedef struct TU_ATTR_ALIGNED(32) {
// Word 0: Next Link Pointer
ehci_link_t next;
ehci_link_t next;
// Word 1: siTD Endpoint Characteristics
uint32_t dev_addr : 7; ///< This field selects the specific device serving as the data source or sink.
uint32_t : 1; ///< reserved
uint32_t ep_number : 4; ///< This 4-bit field selects the particular endpoint number on the device serving as the data source or sink.
uint32_t : 4; ///< This field is reserved and should be set to zero.
uint32_t hub_addr : 7; ///< This field holds the device address of the transaction translators’ hub.
uint32_t : 1; ///< reserved
uint32_t port_number : 7; ///< This field is the port number of the recipient transaction translator.
uint32_t direction : 1; ///< 0 = OUT; 1 = IN. This field encodes whether the full-speed transaction should be an IN or OUT.
// Word 1: siTD Endpoint Characteristics
uint32_t dev_addr : 7; ///< This field selects the specific device serving as the data source or sink.
uint32_t : 1; ///< reserved
uint32_t ep_number : 4; ///< This 4-bit field selects the particular endpoint number on the device serving as the data source or sink.
uint32_t : 4; ///< This field is reserved and should be set to zero.
uint32_t hub_addr : 7; ///< This field holds the device address of the transaction translators’ hub.
uint32_t : 1; ///< reserved
uint32_t port_number : 7; ///< This field is the port number of the recipient transaction translator.
uint32_t direction : 1; ///< 0 = OUT; 1 = IN. This field encodes whether the full-speed transaction should be an IN or OUT.
// Word 2: Micro-frame Schedule Control
uint8_t int_smask ; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute complete-split transactions
uint8_t fl_int_cmask; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute start-split transactions.
uint16_t reserved ; ///< reserved
// Word 2: Micro-frame Schedule Control
uint8_t int_smask ; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute complete-split transactions
uint8_t fl_int_cmask; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute start-split transactions.
uint16_t reserved ; ///< reserved
// Word 3: siTD Transfer Status and Control
// Status [7:0] TODO identical to qTD Token'status --> refactor later
volatile uint32_t : 1 ; // reserved
volatile uint32_t split_state : 1 ;
volatile uint32_t missed_uframe : 1 ;
volatile uint32_t xact_err : 1 ;
volatile uint32_t babble_err : 1 ;
volatile uint32_t buffer_err : 1 ;
volatile uint32_t error : 1 ;
volatile uint32_t active : 1 ;
// Micro-frame Schedule Control
volatile uint32_t cmask_progress : 8 ; ///< This field is used by the host controller to record which split-completes have been executed. See Section 4.12.3.3.2 for behavioral requirements.
volatile uint32_t total_bytes : 10 ; ///< This field is initialized by software to the total number of bytes expected in this transfer. Maximum value is 1023
volatile uint32_t : 4 ; ///< reserved
volatile uint32_t page_select : 1 ; ///< Used to indicate which data page pointer should be concatenated with the CurrentOffsetfield to construct a data buffer pointer
uint32_t int_on_complete : 1 ; ///< Do not interrupt when transaction is complete. 1 = Do interrupt when transaction is complete
uint32_t : 0 ; // padding to the end of current storage unit
// Word 3: siTD Transfer Status and Control
// Status [7:0] TODO identical to qTD Token'status --> refactor later
volatile uint32_t : 1 ; // reserved
volatile uint32_t split_state : 1 ;
volatile uint32_t missed_uframe : 1 ;
volatile uint32_t xact_err : 1 ;
volatile uint32_t babble_err : 1 ;
volatile uint32_t buffer_err : 1 ;
volatile uint32_t error : 1 ;
volatile uint32_t active : 1 ;
// Micro-frame Schedule Control
volatile uint32_t cmask_progress : 8 ; ///< This field is used by the host controller to record which split-completes have been executed. See Section 4.12.3.3.2 for behavioral requirements.
volatile uint32_t total_bytes : 10 ; ///< This field is initialized by software to the total number of bytes expected in this transfer. Maximum value is 1023
volatile uint32_t : 4 ; ///< reserved
volatile uint32_t page_select : 1 ; ///< Used to indicate which data page pointer should be concatenated with the CurrentOffsetfield to construct a data buffer pointer
uint32_t int_on_complete : 1 ; ///< Do not interrupt when transaction is complete. 1 = Do interrupt when transaction is complete
uint32_t : 0 ; // padding to the end of current storage unit
/// Word 4-5: Buffer Pointer List
uint32_t buffer[2]; // buffer[1] TP: Transaction Position - T-Count: Transaction Count
/// Word 4-5: Buffer Pointer List
uint32_t buffer[2]; // buffer[1] TP: Transaction Position - T-Count: Transaction Count
/*---------- Word 6 ----------*/
ehci_link_t back;
/*---------- Word 6 ----------*/
ehci_link_t back;
/// SITD is 32-byte aligned but occupies only 28 --> 4 bytes for storing extra data
uint8_t used;
uint8_t ihd_idx;
uint8_t reserved2[2];
/// SITD is 32-byte aligned but occupies only 28 --> 4 bytes for storing extra data
uint8_t used;
uint8_t ihd_idx;
uint8_t reserved2[2];
} ehci_sitd_t;
TU_VERIFY_STATIC( sizeof(ehci_sitd_t) == 32, "size is not correct" );
@@ -315,8 +308,7 @@ enum {
EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE
};
typedef volatile struct
{
typedef volatile struct {
union {
uint32_t command; // 0x00

5
src/portable/mentor/musb/hcd_musb.c
View File

@@ -804,6 +804,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
return true;
}
bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
(void) rhport; (void) daddr; (void) ep_addr;
return false; // TODO not implemented yet
}
bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen)
{
(void)rhport;

5
src/portable/nxp/khci/hcd_khci.c
View File

@@ -541,6 +541,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
return true;
}
bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
(void) rhport; (void) daddr; (void) ep_addr;
return false; // TODO not implemented yet
}
/* The address of buffer must be aligned to 4 byte boundary. And it must be at least 4 bytes long.
* DMA writes data in 4 byte unit */
bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)

6
src/portable/ohci/ohci.c
View File

@@ -451,7 +451,6 @@ static void td_insert_to_ed(ohci_ed_t* p_ed, ohci_gtd_t * p_gtd)
//--------------------------------------------------------------------+
// Endpoint API
//--------------------------------------------------------------------+
bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
{
(void) rhport;
@@ -486,6 +485,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
return true;
}
bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
(void) rhport; (void) daddr; (void) ep_addr;
return false; // TODO not implemented yet
}
bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
{
(void) rhport;

5
src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
View File

@@ -122,6 +122,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
return pio_usb_host_endpoint_open(pio_rhport, dev_addr, (uint8_t const *) desc_ep, need_pre);
}
bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
uint8_t const pio_rhport = RHPORT_PIO(rhport);
return pio_usb_host_endpoint_close(pio_rhport, daddr, ep_addr);
}
bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) {
uint8_t const pio_rhport = RHPORT_PIO(rhport);
return pio_usb_host_endpoint_transfer(pio_rhport, dev_addr, ep_addr, buffer, buflen);

6
src/portable/raspberrypi/rp2040/hcd_rp2040.c
View File

@@ -514,7 +514,6 @@ void hcd_int_disable(uint8_t rhport)
//--------------------------------------------------------------------+
// Endpoint API
//--------------------------------------------------------------------+
bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
{
(void) rhport;
@@ -535,6 +534,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
return true;
}
bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
(void) rhport; (void) daddr; (void) ep_addr;
return false; // TODO not implemented yet
}
bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
{
(void) rhport;

5
src/portable/renesas/rusb2/hcd_rusb2.c
View File

@@ -718,6 +718,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
return true;
}
bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
(void) rhport; (void) daddr; (void) ep_addr;
return false; // TODO not implemented yet
}
bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen)
{
bool r;

5
src/portable/synopsys/dwc2/hcd_dwc2.c
View File

@@ -506,6 +506,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t*
return true;
}
bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
(void) rhport; (void) daddr; (void) ep_addr;
return false; // TODO not implemented yet
}
// clean up channel after part of transfer is done but the whole urb is not complete
static void channel_xfer_out_wrapup(dwc2_regs_t* dwc2, uint8_t ch_id) {
hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id];

49
src/portable/template/hcd_template.c
View File

@@ -36,24 +36,19 @@
// optional hcd configuration, called by tuh_configure()
bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
(void) rhport;
(void) cfg_id;
(void) cfg_param;
(void) rhport; (void) cfg_id; (void) cfg_param;
return false;
}
// Initialize controller to host mode
bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
(void) rhport;
(void) rh_init;
(void) rhport; (void) rh_init;
return false;
}
// Interrupt Handler
void hcd_int_handler(uint8_t rhport, bool in_isr) {
(void) rhport;
(void) in_isr;
(void) rhport; (void) in_isr;
}
// Enable USB interrupt
@@ -69,7 +64,6 @@ void hcd_int_disable(uint8_t rhport) {
// Get frame number (1ms)
uint32_t hcd_frame_number(uint8_t rhport) {
(void) rhport;
return 0;
}
@@ -80,7 +74,6 @@ uint32_t hcd_frame_number(uint8_t rhport) {
// Get the current connect status of roothub port
bool hcd_port_connect_status(uint8_t rhport) {
(void) rhport;
return false;
}
@@ -98,14 +91,12 @@ void hcd_port_reset_end(uint8_t rhport) {
// Get port link speed
tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
(void) rhport;
return TUSB_SPEED_FULL;
}
// HCD closes all opened endpoints belong to this device
void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
(void) rhport;
(void) dev_addr;
(void) rhport; (void) dev_addr;
}
//--------------------------------------------------------------------+
@@ -114,49 +105,37 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
// Open an endpoint
bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) {
(void) rhport;
(void) dev_addr;
(void) ep_desc;
(void) rhport; (void) dev_addr; (void) ep_desc;
return false;
}
bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
(void) rhport; (void) daddr; (void) ep_addr;
return false; // TODO not implemented yet
}
// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
(void) rhport;
(void) dev_addr;
(void) ep_addr;
(void) buffer;
(void) buflen;
(void) rhport; (void) dev_addr; (void) ep_addr; (void) buffer; (void) buflen;
return false;
}
// Abort a queued transfer. Note: it can only abort transfer that has not been started
// Return true if a queued transfer is aborted, false if there is no transfer to abort
bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
(void) rhport;
(void) dev_addr;
(void) ep_addr;
(void) rhport; (void) dev_addr; (void) ep_addr;
return false;
}
// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) {
(void) rhport;
(void) dev_addr;
(void) setup_packet;
(void) rhport; (void) dev_addr; (void) setup_packet;
return false;
}
// clear stall, data toggle is also reset to DATA0
bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
(void) rhport;
(void) dev_addr;
(void) ep_addr;
(void) rhport; (void) dev_addr; (void) ep_addr;
return false;
}

52
test/hil/hil_test.py
View File

@@ -81,7 +81,7 @@ def get_serial_dev(id, vendor_str, product_str, ifnum):
return f'/dev/serial/by-id/usb-{vendor_str}_{product_str}_{id}-if{ifnum:02d}'
else:
# just use id: mostly for cp210x/ftdi flasher
pattern = f'/dev/serial/by-id/usb-*_{id}-if{ifnum:02d}*'
pattern = f'/dev/serial/by-id/usb-*_{id}-if*'
port_list = glob.glob(pattern)
return port_list[0]
@@ -98,20 +98,18 @@ def get_hid_dev(id, vendor_str, product_str, event):
def open_serial_dev(port):
timeout = ENUM_TIMEOUT
ser = None
while timeout:
while timeout > 0:
if os.path.exists(port):
try:
# slight delay since kernel may occupy the port briefly
time.sleep(0.5)
timeout = timeout - 0.5
ser = serial.Serial(port, baudrate=115200, timeout=5)
break
except serial.SerialException:
print(f'serial {port} not reaady {timeout} sec')
pass
time.sleep(0.5)
timeout = timeout - 0.5
time.sleep(0.1)
timeout -= 0.1
assert timeout, f'Cannot open port f{port}' if os.path.exists(port) else f'Port {port} not existed'
assert timeout > 0, f'Cannot open port f{port}' if os.path.exists(port) else f'Port {port} not existed'
return ser
@@ -119,7 +117,7 @@ def read_disk_file(uid, lun, fname):
# open_fs("fat://{dev}) require 'pip install pyfatfs'
dev = get_disk_dev(uid, 'TinyUSB', lun)
timeout = ENUM_TIMEOUT
while timeout:
while timeout > 0:
if os.path.exists(dev):
fat = fs.open_fs(f'fat://{dev}?read_only=true')
try:
@@ -132,7 +130,7 @@ def read_disk_file(uid, lun, fname):
time.sleep(1)
timeout -= 1
assert timeout, f'Storage {dev} not existed'
assert timeout > 0, f'Storage {dev} not existed'
return None
@@ -202,14 +200,14 @@ def reset_stflash(board):
def flash_openocd(board, firmware):
flasher = board['flasher']
ret = run_cmd(f'openocd -c "tcl_port disabled" -c "gdb_port disabled" -c "adapter serial {flasher["uid"]}" '
f'{flasher["args"]} -c init -c halt -c "program {firmware}.elf verify" -c reset -c exit')
f'{flasher["args"]} -c "init; halt; program {firmware}.elf verify; reset; exit"')
return ret
def reset_openocd(board):
flasher = board['flasher']
ret = run_cmd(f'openocd -c "tcl_port disabled" -c "gdb_port disabled" -c "adapter serial {flasher["uid"]}" '
f'{flasher["args"]} -c "reset exit"')
f'{flasher["args"]} -c "init; reset run; exit"')
return ret
@@ -304,11 +302,11 @@ def test_dual_host_info_to_device_cdc(board):
ser = open_serial_dev(port)
# read from cdc, first line should contain vid/pid and serial
data = ser.read(1000)
data = ser.read(10000)
ser.close()
if len(data) == 0:
assert False, 'No data from device'
lines = data.decode('utf-8').splitlines()
lines = data.decode('utf-8', errors='ignore').splitlines()
enum_dev_sn = []
for l in lines:
@@ -319,6 +317,7 @@ def test_dual_host_info_to_device_cdc(board):
if set(declared_devs) != set(enum_dev_sn):
failed_msg = f'Expected {declared_devs}, Enumerated {enum_dev_sn}'
print('\n'.join(lines))
assert False, failed_msg
return 0
@@ -337,12 +336,12 @@ def test_host_device_info(board):
ret = globals()[f'reset_{flasher["name"].lower()}'](board)
assert ret.returncode == 0, 'Failed to reset device'
data = ser.read(1000)
data = ser.read(10000)
ser.close()
if len(data) == 0:
assert False, 'No data from device'
lines = data.decode('utf-8', errors='ignore').splitlines()
lines = data.decode('utf-8').splitlines()
enum_dev_sn = []
for l in lines:
vid_pid_sn = re.search(r'ID ([0-9a-fA-F]+):([0-9a-fA-F]+) SN (\w+)', l)
@@ -352,8 +351,8 @@ def test_host_device_info(board):
if set(declared_devs) != set(enum_dev_sn):
failed_msg = f'Expected {declared_devs}, Enumerated {enum_dev_sn}'
print('\n'.join(lines))
assert False, failed_msg
return 0
@@ -419,7 +418,7 @@ def test_device_dfu(board):
# Wait device enum
timeout = ENUM_TIMEOUT
while timeout:
while timeout > 0:
ret = run_cmd(f'dfu-util -l')
stdout = ret.stdout.decode()
if f'serial="{uid}"' in stdout and 'Found DFU: [cafe:4000]' in stdout:
@@ -427,7 +426,7 @@ def test_device_dfu(board):
time.sleep(1)
timeout = timeout - 1
assert timeout, 'Device not available'
assert timeout > 0, 'Device not available'
f_dfu0 = f'dfu0_{uid}'
f_dfu1 = f'dfu1_{uid}'
@@ -460,7 +459,7 @@ def test_device_dfu_runtime(board):
# Wait device enum
timeout = ENUM_TIMEOUT
while timeout:
while timeout > 0:
ret = run_cmd(f'dfu-util -l')
stdout = ret.stdout.decode()
if f'serial="{uid}"' in stdout and 'Found Runtime: [cafe:4000]' in stdout:
@@ -468,7 +467,7 @@ def test_device_dfu_runtime(board):
time.sleep(1)
timeout = timeout - 1
assert timeout, 'Device not available'
assert timeout > 0, 'Device not available'
def test_device_hid_boot_interface(board):
@@ -478,13 +477,13 @@ def test_device_hid_boot_interface(board):
mouse2 = get_hid_dev(uid, 'TinyUSB', 'TinyUSB_Device', 'if01-mouse')
# Wait device enum
timeout = ENUM_TIMEOUT
while timeout:
while timeout > 0:
if os.path.exists(kbd) and os.path.exists(mouse1) and os.path.exists(mouse2):
break
time.sleep(1)
timeout = timeout - 1
assert timeout, 'HID device not available'
assert timeout > 0, 'HID device not available'
def test_device_hid_composite_freertos(id):
@@ -561,6 +560,9 @@ def test_board(board):
print('Skip (no binary)')
continue
if verbose:
print(f'Flashing {fw_name}.elf')
# flash firmware. It may fail randomly, retry a few times
max_rety = 2
for i in range(max_rety):
@@ -577,10 +579,10 @@ def test_board(board):
print(f' {e}')
else:
print()
print(f' Test failed: {e}, retry {i+1}')
print(f' Test failed: {e}, retry {i+2}/{max_rety}')
time.sleep(1)
else:
print(f'Flashing failed, retry {i+1}')
print(f'Flashing failed, retry {i+2}/{max_rety}')
time.sleep(1)
if ret.returncode != 0:

29
test/hil/tinyusb.json
View File

@@ -60,7 +60,7 @@
"name": "metro_m4_express",
"uid": "9995AD485337433231202020FF100A34",
"tests": {
"device": true, "host": false, "dual": false,
"device": true, "host": false, "dual": true,
"dev_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2002130"}]
},
"flasher": {
@@ -69,6 +69,19 @@
"args": "-device ATSAMD51J19"
}
},
{
"name": "mimxrt1064_evk",
"uid": "BAE96FB95AFA6DBB8F00005002001200",
"tests": {
"device": true, "host": true, "dual": true,
"dev_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2023299"}]
},
"flasher": {
"name": "jlink",
"uid": "000725299165",
"args": "-device MIMXRT1064xxx6A"
}
},
{
"name": "lpcxpresso11u37",
"uid": "17121919",
@@ -98,8 +111,11 @@
{
"name": "raspberry_pi_pico",
"uid": "E6614C311B764A37",
"build" : {
"flags_on": ["CFG_TUH_RPI_PIO_USB"]
},
"tests": {
"device": true, "host": false, "dual": false,
"device": true, "host": true, "dual": true,
"dev_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2002470"}]
},
"flasher": {
@@ -111,8 +127,11 @@
{
"name": "raspberry_pi_pico2",
"uid": "560AE75E1C7152C9",
"build" : {
"flags_on": ["CFG_TUH_RPI_PIO_USB"]
},
"tests": {
"device": true, "host": false, "dual": false,
"device": true, "host": true, "dual": true,
"dev_attached": [{"vid_pid": "1a86_55d4", "serial": "533D004242"}]
},
"flasher": {
@@ -157,9 +176,9 @@
"device": true, "host": false, "dual": false
},
"flasher": {
"name": "stlink",
"name": "openocd",
"uid": "004C00343137510F39383538",
"args": ""
"args": "-f interface/stlink.cfg -f target/stm32h7x.cfg"
}
},
{

4
tools/get_deps.py
View File

@@ -58,8 +58,8 @@ deps_optional = {
'hw/mcu/nxp/mcux-sdk': ['https://github.com/hathach/mcux-sdk.git',
'144f1eb7ea8c06512e12f12b27383601c0272410',
'kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt'],
'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git',
'0ca3657d55ea20e7fa4483bbd21ce951bc1d6fa5',
'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/hathach/Pico-PIO-USB.git',
'810653f66adadba3e0e4b4b56d5167ac4f7fdbf7',
'rp2040'],
'hw/mcu/renesas/fsp': ['https://github.com/renesas/fsp.git',
'edcc97d684b6f716728a60d7a6fea049d9870bd6',