Merge pull request #3228 from espressif/feat/dcd_dwc_v4.30a
fix(dcd/dwc2): Fix reset procedure for versions >=4.20a
This commit is contained in:
@@ -1,7 +1,7 @@
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/*
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/*
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* The MIT License (MIT)
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* The MIT License (MIT)
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*
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*
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* Copyright (c) 2024 Ha Thach (tinyusb.org)
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* Copyright (c) 2024-2025 Ha Thach (tinyusb.org)
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*
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* of this software and associated documentation files (the "Software"), to deal
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@@ -45,11 +45,14 @@
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//
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//
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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static void reset_core(dwc2_regs_t* dwc2) {
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static void reset_core(dwc2_regs_t* dwc2) {
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// load gsnpsid (it is not readable after reset is asserted)
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uint32_t gsnpsid = dwc2->gsnpsid;
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// reset core
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// reset core
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dwc2->grstctl |= GRSTCTL_CSRST;
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dwc2->grstctl |= GRSTCTL_CSRST;
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if ((dwc2->gsnpsid & DWC2_CORE_REV_MASK) < (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) {
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if ((gsnpsid & DWC2_CORE_REV_MASK) < (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) {
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// prior v42.0 CSRST is self-clearing
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// prior v4.20a CSRST is self-clearing
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while (dwc2->grstctl & GRSTCTL_CSRST) {}
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while (dwc2->grstctl & GRSTCTL_CSRST) {}
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} else {
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} else {
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// From v4.20a CSRST bit is write only, CSRT_DONE (w1c) is introduced for checking.
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// From v4.20a CSRST bit is write only, CSRT_DONE (w1c) is introduced for checking.
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