move gahbcfg/gintmsk with dma to dwc2 common

src/portable/synopsys/dwc2/dwc2_common.h

@@ -57,6 +57,8 @@ enum {
   DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller)
 };
 
+
+//------------- Core -------------//
 TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) {
   if (rhport >= DWC2_CONTROLLER_COUNT) {
     // user mis-configured, ignore and use first controller
@@ -68,4 +70,39 @@ TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) {
 bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init);
 bool dwc2_core_init(uint8_t rhport, const tusb_rhport_init_t* rh_init);
 
+//------------- DFIFO -------------//
+TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_tx(dwc2_regs_t* dwc2, uint8_t fnum) {
+  // flush TX fifo and wait for it cleared
+  dwc2->grstctl = GRSTCTL_TXFFLSH | (fnum << GRSTCTL_TXFNUM_Pos);
+  while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {}
+}
+TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_rx(dwc2_regs_t* dwc2) {
+  // flush RX fifo and wait for it cleared
+  dwc2->grstctl = GRSTCTL_RXFFLSH;
+  while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {}
+}
+
+//------------- DMA -------------//
+TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dma_enabled(const dwc2_regs_t* dwc2, tusb_role_t role) {
+  (void) dwc2;
+
+  if (CFG_TUD_DWC2_DMA == 0 && role == TUSB_ROLE_DEVICE) {
+    return false;
+  }
+
+  if (CFG_TUH_DWC2_DMA == 0 && role == TUSB_ROLE_HOST) {
+    return false;
+  }
+
+  // Internal DMA only
+  return dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint16_t dma_cal_epfifo_base(uint8_t rhport) {
+  // Scatter/Gather DMA mode is not yet supported. Buffer DMA only need 1 words per endpoint direction
+  const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport];
+  return dwc2_controller->ep_fifo_size/4 - 2*dwc2_controller->ep_count;
+}
+
+
 #endif