andy/tinyUSB
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Add board support for Dialog DA1469x-dk-pro

Browse Source 
This adds source files that allow to run TinyUSB stack on DA1469x-dk-pro board.
Source files .c .S and .ld are taken from Apache Mynewt repository.
Those files were stripped to allow starting board without Mynewt os.
This commit is contained in:
Jerzy Kasenberg
2020-06-19 14:02:09 +02:00
parent 0635bafe0a
commit 8e143fc962
17 changed files with 2553 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

159
hw/mcu/dialog/da1469x/src/da1469x_clock.c Normal file
View File

@@ -0,0 +1,159 @@
/*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
* distributed with this work for additional information
* regarding copyright ownership. The ASF licenses this file
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
* KIND, either express or implied. See the License for the
* specific language governing permissions and limitations
* under the License.
*/
#include <assert.h>
#include <stdbool.h>
#include <stdint.h>
#include "syscfg/syscfg.h"
#include "mcu/da1469x_hal.h"
#include "mcu/da1469x_clock.h"
static inline bool
da1469x_clock_is_xtal32m_settled(void)
{
return ((*(uint32_t *)0x5001001c & 0xff00) == 0) &&
((*(uint32_t *)0x50010054 & 0x000f) != 0xb);
}
void
da1469x_clock_sys_xtal32m_init(void)
{
uint32_t reg;
int xtalrdy_cnt;
/* Number of lp_clk cycles (~30.5us) */
xtalrdy_cnt = MYNEWT_VAL(MCU_CLOCK_XTAL32M_SETTLE_TIME_US) * 10 / 305;
reg = CRG_XTAL->XTALRDY_CTRL_REG;
reg &= ~(CRG_XTAL_XTALRDY_CTRL_REG_XTALRDY_CLK_SEL_Msk |
CRG_XTAL_XTALRDY_CTRL_REG_XTALRDY_CNT_Msk);
reg |= xtalrdy_cnt;
CRG_XTAL->XTALRDY_CTRL_REG = reg;
}
void
da1469x_clock_sys_xtal32m_enable(void)
{
PDC->PDC_CTRL0_REG = (2 << PDC_PDC_CTRL0_REG_TRIG_SELECT_Pos) |
(15 << PDC_PDC_CTRL0_REG_TRIG_ID_Pos) |
(1 << PDC_PDC_CTRL0_REG_PDC_MASTER_Pos) |
(1 << PDC_PDC_CTRL0_REG_EN_XTAL_Pos);
PDC->PDC_SET_PENDING_REG = 0;
PDC->PDC_ACKNOWLEDGE_REG = 0;
}
void
da1469x_clock_sys_xtal32m_switch(void)
{
if (CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Msk) {
CRG_TOP->CLK_SWITCH2XTAL_REG = CRG_TOP_CLK_SWITCH2XTAL_REG_SWITCH2XTAL_Msk;
} else {
CRG_TOP->CLK_CTRL_REG &= ~CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk;
}
while (!(CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Msk));
}
void
da1469x_clock_sys_xtal32m_wait_to_settle(void)
{
uint32_t primask;
__HAL_DISABLE_INTERRUPTS(primask);
NVIC_ClearPendingIRQ(XTAL32M_RDY_IRQn);
if (!da1469x_clock_is_xtal32m_settled()) {
NVIC_EnableIRQ(XTAL32M_RDY_IRQn);
while (!NVIC_GetPendingIRQ(XTAL32M_RDY_IRQn)) {
__WFI();
}
NVIC_DisableIRQ(XTAL32M_RDY_IRQn);
}
__HAL_ENABLE_INTERRUPTS(primask);
}
void
da1469x_clock_sys_xtal32m_switch_safe(void)
{
da1469x_clock_sys_xtal32m_wait_to_settle();
da1469x_clock_sys_xtal32m_switch();
}
void
da1469x_clock_sys_rc32m_disable(void)
{
CRG_TOP->CLK_RC32M_REG &= ~CRG_TOP_CLK_RC32M_REG_RC32M_ENABLE_Msk;
}
void
da1469x_clock_lp_xtal32k_enable(void)
{
CRG_TOP->CLK_XTAL32K_REG |= CRG_TOP_CLK_XTAL32K_REG_XTAL32K_ENABLE_Msk;
}
void
da1469x_clock_lp_xtal32k_switch(void)
{
CRG_TOP->CLK_CTRL_REG = (CRG_TOP->CLK_CTRL_REG &
~CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk) |
(2 << CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos);
}
void
da1469x_clock_pll_disable(void)
{
while (CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Msk) {
CRG_TOP->CLK_SWITCH2XTAL_REG = CRG_TOP_CLK_SWITCH2XTAL_REG_SWITCH2XTAL_Msk;
}
CRG_XTAL->PLL_SYS_CTRL1_REG &= ~CRG_XTAL_PLL_SYS_CTRL1_REG_PLL_EN_Msk;
}
void
da1469x_clock_pll_wait_to_lock(void)
{
uint32_t primask;
__HAL_DISABLE_INTERRUPTS(primask);
NVIC_ClearPendingIRQ(PLL_LOCK_IRQn);
if (!da1469x_clock_is_pll_locked()) {
NVIC_EnableIRQ(PLL_LOCK_IRQn);
while (!NVIC_GetPendingIRQ(PLL_LOCK_IRQn)) {
__WFI();
}
NVIC_DisableIRQ(PLL_LOCK_IRQn);
}
__HAL_ENABLE_INTERRUPTS(primask);
}
void
da1469x_clock_sys_pll_switch(void)
{
/* CLK_SEL_Msk == 3 means PLL */
CRG_TOP->CLK_CTRL_REG |= CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk;
while (!(CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Msk));
}

478
hw/mcu/dialog/da1469x/src/hal_gpio.c Normal file
View File

@@ -0,0 +1,478 @@
/*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
* distributed with this work for additional information
* regarding copyright ownership. The ASF licenses this file
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
* KIND, either express or implied. See the License for the
* specific language governing permissions and limitations
* under the License.
*/
#include <assert.h>
#include <stddef.h>
#include "syscfg/syscfg.h"
#include "mcu/da1469x_hal.h"
#include <mcu/mcu.h>
#include "hal/hal_gpio.h"
/* GPIO interrupts */
#define HAL_GPIO_MAX_IRQ MYNEWT_VAL(MCU_GPIO_MAX_IRQ)
#define GPIO_REG(name) ((__IO uint32_t *)(GPIO_BASE + offsetof(GPIO_Type, name)))
#define WAKEUP_REG(name) ((__IO uint32_t *)(WAKEUP_BASE + offsetof(WAKEUP_Type, name)))
#define CRG_TOP_REG(name) ((__IO uint32_t *)(CRG_TOP_BASE + offsetof(CRG_TOP_Type, name)))
#ifndef MCU_GPIO_PORT0_PIN_COUNT
#define MCU_GPIO_PORT0_PIN_COUNT 32
#endif
#if (MCU_GPIO_PORT0_PIN_COUNT) == 32
#define GPIO_PORT(pin) (((unsigned)(pin)) >> 5U)
#define GPIO_PORT_PIN(pin) (((unsigned)(pin)) & 31U)
#else
#define GPIO_PORT(pin) (((unsigned)(pin)) < MCU_GPIO_PORT0_PIN_COUNT ? 0 : 1)
#define GPIO_PORT_PIN(pin) ((unsigned)(pin) < MCU_GPIO_PORT0_PIN_COUNT ? \
(pin) : (pin) - MCU_GPIO_PORT0_PIN_COUNT)
#endif
#define GPIO_PIN_BIT(pin) (1 << GPIO_PORT_PIN(pin))
#define GPIO_PIN_DATA_REG_ADDR(pin) (GPIO_REG(P0_DATA_REG) + GPIO_PORT(pin))
#define GPIO_PIN_DATA_REG(pin) *GPIO_PIN_DATA_REG_ADDR(pin)
#define GPIO_PIN_SET_DATA_REG_ADDR(pin) (GPIO_REG(P0_SET_DATA_REG) + GPIO_PORT(pin))
#define GPIO_PIN_SET_DATA_REG(pin) *GPIO_PIN_SET_DATA_REG_ADDR(pin)
#define GPIO_PIN_RESET_DATA_REG_ADDR(pin) (GPIO_REG(P0_RESET_DATA_REG) + GPIO_PORT(pin))
#define GPIO_PIN_RESET_DATA_REG(pin) *GPIO_PIN_RESET_DATA_REG_ADDR(pin)
#define GPIO_PIN_MODE_REG_ADDR(pin) (GPIO_REG(P0_00_MODE_REG) + (pin))
#define GPIO_PIN_MODE_REG(pin) *GPIO_PIN_MODE_REG_ADDR(pin)
#define GPIO_PIN_PADPWR_CTRL_REG_ADDR(pin) (GPIO_REG(P0_PADPWR_CTRL_REG) + GPIO_PORT(pin))
#define GPIO_PIN_PADPWR_CTRL_REG(pin) *GPIO_PIN_PADPWR_CTRL_REG_ADDR(pin)
#define GPIO_PIN_UNLATCH_ADDR(pin) (CRG_TOP_REG(P0_SET_PAD_LATCH_REG) + GPIO_PORT(pin) * 3)
#define GPIO_PIN_LATCH_ADDR(pin) (CRG_TOP_REG(P0_RESET_PAD_LATCH_REG) + GPIO_PORT(pin) * 3)
#define WKUP_CTRL_REG_ADDR (WAKEUP_REG(WKUP_CTRL_REG))
#define WKUP_RESET_IRQ_REG_ADDR (WAKEUP_REG(WKUP_RESET_IRQ_REG))
#define WKUP_SELECT_PX_REG_ADDR(pin) (WAKEUP_REG(WKUP_SELECT_P0_REG) + GPIO_PORT(pin))
#define WKUP_SELECT_PX_REG(pin) *(WKUP_SELECT_PX_REG_ADDR(pin))
#define WKUP_POL_PX_REG_ADDR(pin) (WAKEUP_REG(WKUP_POL_P0_REG) + GPIO_PORT(pin))
#define WKUP_POL_PX_SET_FALLING(pin) do { *(WKUP_POL_PX_REG_ADDR(pin)) |= GPIO_PIN_BIT(pin); } while (0)
#define WKUP_POL_PX_SET_RISING(pin) do { *(WKUP_POL_PX_REG_ADDR(pin)) &= ~GPIO_PIN_BIT(pin); } while (0)
#define WKUP_STAT_PX_REG_ADDR(pin) (WAKEUP_REG(WKUP_STATUS_P0_REG) + GPIO_PORT(pin))
#define WKUP_STAT(pin) ((*(WKUP_STAT_PX_REG_ADDR(pin)) >> GPIO_PORT_PIN(pin)) & 1)
#define WKUP_CLEAR_PX_REG_ADDR(pin) (WAKEUP_REG(WKUP_CLEAR_P0_REG) + GPIO_PORT(pin))
#define WKUP_CLEAR_PX(pin) do { (*(WKUP_CLEAR_PX_REG_ADDR(pin)) = GPIO_PIN_BIT(pin)); } while (0)
#define WKUP_SEL_GPIO_PX_REG_ADDR(pin) (WAKEUP_REG(WKUP_SEL_GPIO_P0_REG) + GPIO_PORT(pin))
#define WKUP_SEL_GPIO_PX_REG(pin) *(WKUP_SEL_GPIO_PX_REG_ADDR(pin))
/* Storage for GPIO callbacks. */
struct hal_gpio_irq {
int pin;
hal_gpio_irq_handler_t func;
void *arg;
};
static struct hal_gpio_irq hal_gpio_irqs[HAL_GPIO_MAX_IRQ];
#if MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM) >= 0
static uint32_t g_mcu_gpio_latch_state[2];
static uint8_t g_mcu_gpio_retained_num;
static struct da1469x_retreg g_mcu_gpio_retained[MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM)];
#endif
/*
* We assume that any latched pin has default configuration, i.e. was either
* not configured or was deinited. Any unlatched pin is considered to be used
* by someone.
*
* By default, all pins are assumed to have default configuration and are
* latched. This allows PD_COM to be disabled (if no other peripheral needs
* it) since we do not need GPIO mux to be active.
*
* Configuration of any pin shall be done as follows, with interrupts disabled:
* 1. call mcu_gpio_unlatch_prepare() to enable PD_COM if needed
* 2. configure pin
* 3. call mcu_gpio_unlatch() to actually unlatch pin
*
* Once pin is restored to default configuration it shall be latched again by
* calling mcu_gpio_latch().
*/
#if MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM) >= 0
static void
mcu_gpio_retained_add_port(uint32_t latch_val, volatile uint32_t *base_reg)
{
struct da1469x_retreg *retreg;
int pin;
retreg = &g_mcu_gpio_retained[g_mcu_gpio_retained_num];
while (latch_val) {
assert(g_mcu_gpio_retained_num < MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM));
pin = __builtin_ctz(latch_val);
latch_val &= ~(1 << pin);
da1469x_retreg_assign(retreg, &base_reg[pin]);
g_mcu_gpio_retained_num++;
retreg++;
}
}
#endif
static void
mcu_gpio_retained_refresh(void)
{
#if MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM) >= 0
g_mcu_gpio_retained_num = 0;
mcu_gpio_retained_add_port(CRG_TOP->P0_PAD_LATCH_REG, &GPIO->P0_00_MODE_REG);
mcu_gpio_retained_add_port(CRG_TOP->P1_PAD_LATCH_REG, &GPIO->P1_00_MODE_REG);
#endif
}
static inline void
mcu_gpio_unlatch_prepare(int pin)
{
__HAL_ASSERT_CRITICAL();
(void)pin;
/* Acquire PD_COM if first pin will be unlatched */
// if ((CRG_TOP->P0_PAD_LATCH_REG | CRG_TOP->P1_PAD_LATCH_REG) == 0) {
// da1469x_pd_acquire(MCU_PD_DOMAIN_COM);
// }
}
static inline void
mcu_gpio_unlatch(int pin)
{
__HAL_ASSERT_CRITICAL();
*GPIO_PIN_UNLATCH_ADDR(pin) = GPIO_PIN_BIT(pin);
mcu_gpio_retained_refresh();
}
static inline void
mcu_gpio_latch(int pin)
{
(void)pin;
// uint32_t primask;
// uint32_t latch_pre;
// uint32_t latch_post;
//
// __HAL_DISABLE_INTERRUPTS(primask);
//
// latch_pre = CRG_TOP->P0_PAD_LATCH_REG | CRG_TOP->P1_PAD_LATCH_REG;
//
// *GPIO_PIN_LATCH_ADDR(pin) = GPIO_PIN_BIT(pin);
// mcu_gpio_retained_refresh();
//
// latch_post = CRG_TOP->P0_PAD_LATCH_REG | CRG_TOP->P1_PAD_LATCH_REG;
//
// /* Release PD_COM if last pin was latched */
// if (latch_pre && !latch_post) {
// da1469x_pd_release(MCU_PD_DOMAIN_COM);
// }
//
// __HAL_ENABLE_INTERRUPTS(primask);
}
int
hal_gpio_init_in(int pin, hal_gpio_pull_t pull)
{
volatile uint32_t *px_xx_mod_reg = GPIO_PIN_MODE_REG_ADDR(pin);
uint32_t regval;
uint32_t primask;
switch (pull) {
case HAL_GPIO_PULL_UP:
regval = MCU_GPIO_FUNC_GPIO | MCU_GPIO_MODE_INPUT_PULLUP;
break;
case HAL_GPIO_PULL_DOWN:
regval = MCU_GPIO_FUNC_GPIO | MCU_GPIO_MODE_INPUT_PULLDOWN;
break;
case HAL_GPIO_PULL_NONE:
regval = MCU_GPIO_FUNC_GPIO | MCU_GPIO_MODE_INPUT;
break;
default:
return -1;
}
__HAL_DISABLE_INTERRUPTS(primask);
mcu_gpio_unlatch_prepare(pin);
*px_xx_mod_reg = regval;
mcu_gpio_unlatch(pin);
__HAL_ENABLE_INTERRUPTS(primask);
return 0;
}
int
hal_gpio_init_out(int pin, int val)
{
uint32_t primask;
__HAL_DISABLE_INTERRUPTS(primask);
mcu_gpio_unlatch_prepare(pin);
GPIO_PIN_MODE_REG(pin) = MCU_GPIO_MODE_OUTPUT;
if (val) {
GPIO_PIN_SET_DATA_REG(pin) = GPIO_PIN_BIT(pin);
} else {
GPIO_PIN_RESET_DATA_REG(pin) = GPIO_PIN_BIT(pin);
}
mcu_gpio_unlatch(pin);
__HAL_ENABLE_INTERRUPTS(primask);
return 0;
}
int
hal_gpio_deinit(int pin)
{
/* Reset mode to default value and latch pin */
GPIO_PIN_MODE_REG(pin) = 0x200;
GPIO_PIN_RESET_DATA_REG(pin) = GPIO_PIN_BIT(pin);
mcu_gpio_latch(pin);
return 0;
}
void
hal_gpio_write(int pin, int val)
{
if (val) {
GPIO_PIN_SET_DATA_REG(pin) = GPIO_PIN_BIT(pin);
} else {
GPIO_PIN_RESET_DATA_REG(pin) = GPIO_PIN_BIT(pin);
}
}
int
hal_gpio_read(int pin)
{
return (GPIO_PIN_DATA_REG(pin) >> GPIO_PORT_PIN(pin)) & 1;
}
int
hal_gpio_toggle(int pin)
{
int new_value = hal_gpio_read(pin) == 0;
hal_gpio_write(pin, new_value);
return new_value;
}
static void
hal_gpio_irq_handler(void)
{
struct hal_gpio_irq *irq;
uint32_t stat;
int i;
*WKUP_RESET_IRQ_REG_ADDR = 1;
NVIC_ClearPendingIRQ(KEY_WKUP_GPIO_IRQn);
for (i = 0; i < HAL_GPIO_MAX_IRQ; i++) {
irq = &hal_gpio_irqs[i];
/* Read latched status value from relevant GPIO port */
stat = WKUP_STAT(irq->pin);
if (irq->func && stat) {
irq->func(irq->arg);
}
WKUP_CLEAR_PX(irq->pin);
}
}
static void
hal_gpio_irq_setup(void)
{
static uint8_t irq_setup;
int sr;
if (!irq_setup) {
__HAL_DISABLE_INTERRUPTS(sr);
irq_setup = 1;
NVIC_ClearPendingIRQ(GPIO_P0_IRQn);
NVIC_ClearPendingIRQ(GPIO_P1_IRQn);
NVIC_SetVector(GPIO_P0_IRQn, (uint32_t)hal_gpio_irq_handler);
NVIC_SetVector(GPIO_P1_IRQn, (uint32_t)hal_gpio_irq_handler);
WAKEUP->WKUP_CTRL_REG = 0;
WAKEUP->WKUP_CLEAR_P0_REG = 0xFFFFFFFF;
WAKEUP->WKUP_CLEAR_P1_REG = 0x007FFFFF;
WAKEUP->WKUP_SELECT_P0_REG = 0;
WAKEUP->WKUP_SELECT_P1_REG = 0;
WAKEUP->WKUP_SEL_GPIO_P0_REG = 0;
WAKEUP->WKUP_SEL_GPIO_P1_REG = 0;
WAKEUP->WKUP_RESET_IRQ_REG = 0;
CRG_TOP->CLK_TMR_REG |= CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Msk;
__HAL_ENABLE_INTERRUPTS(sr);
NVIC_EnableIRQ(GPIO_P0_IRQn);
NVIC_EnableIRQ(GPIO_P1_IRQn);
}
}
static int
hal_gpio_find_empty_slot(void)
{
int i;
for (i = 0; i < HAL_GPIO_MAX_IRQ; i++) {
if (hal_gpio_irqs[i].func == NULL) {
return i;
}
}
return -1;
}
int
hal_gpio_irq_init(int pin, hal_gpio_irq_handler_t handler, void *arg,
hal_gpio_irq_trig_t trig, hal_gpio_pull_t pull)
{
int i;
hal_gpio_irq_setup();
i = hal_gpio_find_empty_slot();
/* If assert failed increase syscfg value MCU_GPIO_MAX_IRQ */
assert(i >= 0);
if (i < 0) {
return -1;
}
hal_gpio_init_in(pin, pull);
switch (trig) {
case HAL_GPIO_TRIG_RISING:
WKUP_POL_PX_SET_RISING(pin);
break;
case HAL_GPIO_TRIG_FALLING:
WKUP_POL_PX_SET_FALLING(pin);
break;
case HAL_GPIO_TRIG_BOTH:
/* Not supported */
default:
return -1;
}
hal_gpio_irqs[i].pin = pin;
hal_gpio_irqs[i].func = handler;
hal_gpio_irqs[i].arg = arg;
return 0;
}
void
hal_gpio_irq_release(int pin)
{
int i;
hal_gpio_irq_disable(pin);
for (i = 0; i < HAL_GPIO_MAX_IRQ; i++) {
if (hal_gpio_irqs[i].pin == pin && hal_gpio_irqs[i].func) {
hal_gpio_irqs[i].pin = -1;
hal_gpio_irqs[i].arg = NULL;
hal_gpio_irqs[i].func = NULL;
}
}
}
void
hal_gpio_irq_enable(int pin)
{
WKUP_SEL_GPIO_PX_REG(pin) |= GPIO_PIN_BIT(pin);
}
void
hal_gpio_irq_disable(int pin)
{
WKUP_SEL_GPIO_PX_REG(pin) &= ~GPIO_PIN_BIT(pin);
WKUP_CLEAR_PX(pin);
}
void
mcu_gpio_set_pin_function(int pin, int mode, mcu_gpio_func func)
{
uint32_t primask;
__HAL_DISABLE_INTERRUPTS(primask);
mcu_gpio_unlatch_prepare(pin);
GPIO_PIN_MODE_REG(pin) = (func & GPIO_P0_00_MODE_REG_PID_Msk) |
(mode & (GPIO_P0_00_MODE_REG_PUPD_Msk | GPIO_P0_00_MODE_REG_PPOD_Msk));
mcu_gpio_unlatch(pin);
__HAL_ENABLE_INTERRUPTS(primask);
}
void
mcu_gpio_enter_sleep(void)
{
#if MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM) >= 0
if (g_mcu_gpio_retained_num == 0) {
return;
}
g_mcu_gpio_latch_state[0] = CRG_TOP->P0_PAD_LATCH_REG;
g_mcu_gpio_latch_state[1] = CRG_TOP->P1_PAD_LATCH_REG;
da1469x_retreg_update(g_mcu_gpio_retained, g_mcu_gpio_retained_num);
CRG_TOP->P0_RESET_PAD_LATCH_REG = CRG_TOP_P0_PAD_LATCH_REG_P0_LATCH_EN_Msk;
CRG_TOP->P1_RESET_PAD_LATCH_REG = CRG_TOP_P1_PAD_LATCH_REG_P1_LATCH_EN_Msk;
da1469x_pd_release(MCU_PD_DOMAIN_COM);
#endif
}
void
mcu_gpio_exit_sleep(void)
{
#if MYNEWT_VAL(MCU_GPIO_RETAINABLE_NUM) >= 0
if (g_mcu_gpio_retained_num == 0) {
return;
}
da1469x_pd_acquire(MCU_PD_DOMAIN_COM);
da1469x_retreg_restore(g_mcu_gpio_retained, g_mcu_gpio_retained_num);
/* Set pins states to their latched values */
GPIO->P0_DATA_REG = GPIO->P0_DATA_REG;
GPIO->P1_DATA_REG = GPIO->P1_DATA_REG;
CRG_TOP->P0_PAD_LATCH_REG = g_mcu_gpio_latch_state[0];
CRG_TOP->P1_PAD_LATCH_REG = g_mcu_gpio_latch_state[1];
#endif
}

136
hw/mcu/dialog/da1469x/src/hal_system.c Normal file
View File

@@ -0,0 +1,136 @@
/*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
* distributed with this work for additional information
* regarding copyright ownership. The ASF licenses this file
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
* KIND, either express or implied. See the License for the
* specific language governing permissions and limitations
* under the License.
*/
#include <assert.h>
#include "syscfg/syscfg.h"
#include "mcu/da1469x_clock.h"
#include "mcu/da1469x_lpclk.h"
#include "mcu/da1469x_pd.h"
#include "mcu/da1469x_pdc.h"
#include "mcu/da1469x_prail.h"
#include "hal/hal_system.h"
#include "os/os_cputime.h"
#if !MYNEWT_VAL(BOOT_LOADER)
static enum hal_reset_reason g_hal_reset_reason;
#endif
void
hal_system_init(void)
{
#if MYNEWT_VAL(MCU_DCDC_ENABLE)
da1469x_prail_dcdc_enable();
#endif
/*
* RESET_STAT_REG has to be cleared to allow HW set bits during next reset
* so we should read it now and keep result for application to check at any
* time. This does not happen for bootloader since reading reset reason in
* bootloader would prevent application from reading it.
*/
#if !MYNEWT_VAL(BOOT_LOADER)
uint32_t reg;
reg = CRG_TOP->RESET_STAT_REG;
CRG_TOP->RESET_STAT_REG = 0;
if (reg & CRG_TOP_RESET_STAT_REG_PORESET_STAT_Msk) {
g_hal_reset_reason = HAL_RESET_POR;
} else if (reg & CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Msk) {
g_hal_reset_reason = HAL_RESET_WATCHDOG;
} else if (reg & CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Msk) {
g_hal_reset_reason = HAL_RESET_SOFT;
} else if (reg & CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Msk) {
g_hal_reset_reason = HAL_RESET_PIN;
} else {
g_hal_reset_reason = 0;
}
#endif
}
void
hal_system_reset(void)
{
#if MYNEWT_VAL(HAL_SYSTEM_RESET_CB)
hal_system_reset_cb();
#endif
while (1) {
HAL_DEBUG_BREAK();
CRG_TOP->SYS_CTRL_REG = 0x20;
NVIC_SystemReset();
}
}
int
hal_debugger_connected(void)
{
return CRG_TOP->SYS_STAT_REG & CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Msk;
}
void
hal_system_clock_start(void)
{
/* Reset clock dividers to 0 */
CRG_TOP->CLK_AMBA_REG &= ~(CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk | CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk);
/* PD_TIM is already started in SystemInit */
da1469x_clock_sys_xtal32m_init();
da1469x_clock_sys_xtal32m_enable();
#if MYNEWT_VAL(MCU_PLL_ENABLE)
da1469x_clock_sys_pll_enable();
#endif
#if MYNEWT_VAL_CHOICE(MCU_SYSCLK_SOURCE, PLL96)
da1469x_clock_pll_wait_to_lock();
da1469x_clock_sys_pll_switch();
#endif
#if MYNEWT_VAL_CHOICE(MCU_SYSCLK_SOURCE, XTAL32M)
/* Switch to XTAL32M and disable RC32M */
da1469x_clock_sys_xtal32m_switch_safe();
#endif
da1469x_clock_sys_rc32m_disable();
#if MYNEWT_VAL_CHOICE(MCU_LPCLK_SOURCE, RCX)
/* Switch to RCX and calibrate it */
da1469x_clock_lp_rcx_enable();
da1469x_clock_lp_rcx_switch();
da1469x_clock_lp_rcx_calibrate();
da1469x_lpclk_enabled();
#else
/*
* We cannot switch lp_clk to XTAL32K here since it needs some time to
* settle, so we just disable RCX (we don't need it) and then we'll handle
* switch to XTAL32K from sysinit since we need os_cputime for this.
*/
da1469x_clock_lp_rcx_disable();
#endif
}
enum hal_reset_reason
hal_reset_cause(void)
{
#if MYNEWT_VAL(BOOT_LOADER)
return 0;
#else
return g_hal_reset_reason;
#endif
}

177
hw/mcu/dialog/da1469x/src/hal_system_start.c Normal file
View File

@@ -0,0 +1,177 @@
/*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
* distributed with this work for additional information
* regarding copyright ownership. The ASF licenses this file
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
* KIND, either express or implied. See the License for the
* specific language governing permissions and limitations
* under the License.
*/
#include <assert.h>
#include <stdint.h>
#include "mcu/mcu.h"
#include "mcu/da1469x_hal.h"
#include <flash_map/flash_map.h>
#include <mcu/da1469x_clock.h>
#if MCUBOOT_MYNEWT
#include "bootutil/bootutil.h"
#include "bootutil/image.h"
#include "bootutil/bootutil_log.h"
#include "mcu/da1469x_dma.h"
#include "mcu/da1469x_otp.h"
#endif
#if MYNEWT_VAL(BOOT_CUSTOM_START) && MCUBOOT_MYNEWT
sec_text_ram_core
#endif
void __attribute__((naked))
hal_system_start(void *img_start)
{
uint32_t img_data_addr;
uint32_t *img_data;
img_data_addr = MCU_MEM_QSPIF_M_START_ADDRESS + (uint32_t)img_start;
assert(img_data_addr < MCU_MEM_QSPIF_M_END_ADDRESS);
img_data = (uint32_t *)img_data_addr;
asm volatile (".syntax unified \n"
/* 1st word is stack pointer */
" msr msp, %0 \n"
/* 2nd word is a reset handler (image entry) */
" bx %1 \n"
: /* no output */
: "r" (img_data[0]), "r" (img_data[1]));
}
void
hal_system_restart(void *img_start)
{
uint32_t primask __attribute__((unused));
int i;
/*
* Disable interrupts, and leave them disabled.
* They get re-enabled when system starts coming back again.
*/
__HAL_DISABLE_INTERRUPTS(primask);
for (i = 0; i < sizeof(NVIC->ICER) / sizeof(NVIC->ICER[0]); i++) {
NVIC->ICER[i] = 0xffffffff;
}
hal_system_start(img_start);
}
#if MYNEWT_VAL(BOOT_CUSTOM_START) && MCUBOOT_MYNEWT
#define IMAGE_TLV_AES_NONCE 0x50
#define IMAGE_TLV_SECRET_ID 0x60
sec_text_ram_core void
boot_custom_start(uintptr_t flash_base, struct boot_rsp *rsp)
{
int rc;
struct image_tlv_iter it;
const struct flash_area *fap;
uint32_t off;
uint16_t len;
uint16_t type;
uint8_t buf[8];
uint8_t key;
uint32_t nonce[2];
bool has_aes_nonce;
bool has_secret_id;
DMA_Type *dma_regs = DMA;
uint32_t jump_offset = rsp->br_image_off + rsp->br_hdr->ih_hdr_size;
BOOT_LOG_INF("Custom initialization");
/* skip to booting if we are running nonsecure mode */
if (!(CRG_TOP->SECURE_BOOT_REG & 0x1)) {
hal_system_start((void *)(flash_base + jump_offset));
}
rc = flash_area_open(flash_area_id_from_image_slot(0), &fap);
assert(rc == 0);
rc = bootutil_tlv_iter_begin(&it, rsp->br_hdr, fap, IMAGE_TLV_ANY, true);
assert(rc == 0);
has_aes_nonce = has_secret_id = false;
while (true) {
rc = bootutil_tlv_iter_next(&it, &off, &len, &type);
assert(rc >= 0);
if (rc > 0) {
break;
}
if (type == IMAGE_TLV_AES_NONCE) {
assert(len == 8);
rc = flash_area_read(fap, off, buf, len);
assert(rc == 0);
nonce[0] = __builtin_bswap32(*(uint32_t *)buf);
nonce[1] = __builtin_bswap32(*(uint32_t *)(buf + 4));
has_aes_nonce = true;
} else if (type == IMAGE_TLV_SECRET_ID) {
assert(len == 4);
rc = flash_area_read(fap, off, buf, len);
assert(rc == 0);
key = buf[0];
has_secret_id = true;
}
}
assert(has_aes_nonce && has_secret_id && key <= 7);
/* enable OTP clock and set in read mode */
da1469x_clock_amba_enable(CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Msk);
da1469x_otp_set_mode(OTPC_MODE_READ);
/* disable decrypt on the fly and program start and end addresses */
QSPIC->QSPIC_CTR_CTRL_REG = 0;
QSPIC->QSPIC_CTR_SADDR_REG = jump_offset;
QSPIC->QSPIC_CTR_EADDR_REG = QSPIC->QSPIC_CTR_SADDR_REG +
rsp->br_hdr->ih_img_size - 1;
/* securely DMA hardware key from secret storage to QSPI decrypt engine */
dma_regs->DMA_REQ_MUX_REG |= 0xf000;
dma_regs->DMA7_LEN_REG = 8;
dma_regs->DMA7_A_START_REG = MCU_OTPM_BASE + OTP_SEGMENT_QSPI_FW_KEYS +
(32 * key);
dma_regs->DMA7_B_START_REG = (uint32_t)&QSPIC->QSPIC_CTR_KEY_0_3_REG;
dma_regs->DMA7_CTRL_REG = DMA_DMA7_CTRL_REG_AINC_Msk |
DMA_DMA7_CTRL_REG_BINC_Msk |
(MCU_DMA_BUS_WIDTH_4B << DMA_DMA7_CTRL_REG_BW_Pos) |
DMA_DMA7_CTRL_REG_DMA_ON_Msk;
while (dma_regs->DMA7_IDX_REG != 8);
/* program NONCE */
QSPIC->QSPIC_CTR_NONCE_0_3_REG = nonce[0];
QSPIC->QSPIC_CTR_NONCE_4_7_REG = nonce[1];
/* turn back on decrypt on the fly */
QSPIC->QSPIC_CTR_CTRL_REG = 1;
/* set OTP to standby and turn off clock */
da1469x_otp_set_mode(OTPC_MODE_STBY);
da1469x_clock_amba_disable(CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Msk);
hal_system_start((void *)(flash_base + jump_offset));
}
#endif

61
hw/mcu/dialog/da1469x/src/system_da1469x.c Normal file
View File

@@ -0,0 +1,61 @@
/*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
* distributed with this work for additional information
* regarding copyright ownership. The ASF licenses this file
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
* KIND, either express or implied. See the License for the
* specific language governing permissions and limitations
* under the License.
*/
#include "mcu/mcu.h"
#include <mcu/da1469x_clock.h>
extern uint8_t __StackLimit;
uint32_t SystemCoreClock = 32000000;
void
SystemInit(void)
{
/* Enable FPU when using hard-float */
#if (__FPU_USED == 1)
SCB->CPACR |= (3UL << 20) | (3UL << 22);
__DSB();
__ISB();
#endif
/* Freez watchdog */
GPREG->SET_FREEZE_REG |= GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Msk;
/* Initialize power domains (disable radio only) */
CRG_TOP->PMU_CTRL_REG = CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Msk;
CRG_TOP->P0_SET_PAD_LATCH_REG = CRG_TOP_P0_PAD_LATCH_REG_P0_LATCH_EN_Msk;
CRG_TOP->P1_SET_PAD_LATCH_REG = CRG_TOP_P1_PAD_LATCH_REG_P1_LATCH_EN_Msk;
/* Reset clock dividers to 0 */
CRG_TOP->CLK_AMBA_REG &= ~(CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk | CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk);
/* PD_TIM is already started in SystemInit */
da1469x_clock_sys_xtal32m_init();
da1469x_clock_sys_xtal32m_enable();
da1469x_clock_sys_pll_enable();
da1469x_clock_pll_wait_to_lock();
/* Switch to XTAL32M and disable RC32M */
da1469x_clock_sys_xtal32m_switch_safe();
da1469x_clock_sys_rc32m_disable();
}
void _init(void)
{
}