Merge branch 'master' into nxp_k64
This commit is contained in:
@@ -53,6 +53,8 @@
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#define U32_TO_U8S_LE(_u32) TU_U32_BYTE0(_u32), TU_U32_BYTE1(_u32), TU_U32_BYTE2(_u32), TU_U32_BYTE3(_u32)
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#define TU_BIT(n) (1UL << (n))
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// Generate a mask with bit from high (31) to low (0) set, e.g TU_GENMASK(3, 0) = 0b1111
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#define TU_GENMASK(h, l) ( (UINT32_MAX << (l)) & (UINT32_MAX >> (31 - (h))) )
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//--------------------------------------------------------------------+
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@@ -99,10 +101,9 @@ TU_ATTR_WEAK extern void* tusb_app_phys_to_virt(void *phys_addr);
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#define tu_varclr(_var) tu_memclr(_var, sizeof(*(_var)))
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// This is a backport of memset_s from c11
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TU_ATTR_ALWAYS_INLINE static inline int tu_memset_s(void *dest, size_t destsz, int ch, size_t count)
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{
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TU_ATTR_ALWAYS_INLINE static inline int tu_memset_s(void *dest, size_t destsz, int ch, size_t count) {
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// TODO may check if desst and src is not NULL
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if (count > destsz) {
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if ( count > destsz ) {
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return -1;
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}
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memset(dest, ch, count);
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@@ -110,10 +111,9 @@ TU_ATTR_ALWAYS_INLINE static inline int tu_memset_s(void *dest, size_t destsz, i
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}
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// This is a backport of memcpy_s from c11
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TU_ATTR_ALWAYS_INLINE static inline int tu_memcpy_s(void *dest, size_t destsz, const void * src, size_t count )
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{
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TU_ATTR_ALWAYS_INLINE static inline int tu_memcpy_s(void *dest, size_t destsz, const void *src, size_t count) {
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// TODO may check if desst and src is not NULL
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if (count > destsz) {
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if ( count > destsz ) {
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return -1;
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}
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memcpy(dest, src, count);
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@@ -159,16 +159,20 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_max16 (uint16_t x, uint16_t y) {
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TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_max32 (uint32_t x, uint32_t y) { return (x > y) ? x : y; }
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//------------- Align -------------//
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TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align(uint32_t value, uint32_t alignment)
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{
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TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align(uint32_t value, uint32_t alignment) {
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return value & ((uint32_t) ~(alignment-1));
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}
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TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align4 (uint32_t value) { return (value & 0xFFFFFFFCUL); }
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TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align8 (uint32_t value) { return (value & 0xFFFFFFF8UL); }
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TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align16 (uint32_t value) { return (value & 0xFFFFFFF0UL); }
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TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align32 (uint32_t value) { return (value & 0xFFFFFFE0UL); }
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TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align4k (uint32_t value) { return (value & 0xFFFFF000UL); }
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TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_offset4k(uint32_t value) { return (value & 0xFFFUL); }
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TU_ATTR_ALWAYS_INLINE static inline bool tu_is_aligned32(uint32_t value) { return (value & 0x1FUL) == 0; }
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TU_ATTR_ALWAYS_INLINE static inline bool tu_is_aligned64(uint64_t value) { return (value & 0x3FUL) == 0; }
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//------------- Mathematics -------------//
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TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_div_ceil(uint32_t v, uint32_t d) { return (v + d -1)/d; }
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@@ -260,11 +264,21 @@ TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void* mem, uint16_
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#else
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// MCU that could access unaligned memory natively
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TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32 (const void* mem) { return *((uint32_t const *) mem); }
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TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16 (const void* mem) { return *((uint16_t const *) mem); }
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TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32(const void *mem) {
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return *((uint32_t const *) mem);
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}
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TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write32 (void* mem, uint32_t value ) { *((uint32_t*) mem) = value; }
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TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16 (void* mem, uint16_t value ) { *((uint16_t*) mem) = value; }
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TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16(const void *mem) {
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return *((uint16_t const *) mem);
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}
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TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write32(void *mem, uint32_t value) {
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*((uint32_t *) mem) = value;
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}
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TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void *mem, uint16_t value) {
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*((uint16_t *) mem) = value;
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}
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#endif
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@@ -539,7 +539,7 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu
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// Advance index
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f->wr_idx = advance_index(f->depth, wr_idx, n);
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TU_LOG(TU_FIFO_DBG, "\tnew_wr = %u\n", f->wr_idx);
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TU_LOG(TU_FIFO_DBG, "\tnew_wr = %u\r\n", f->wr_idx);
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}
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_ff_unlock(f->mutex_wr);
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@@ -34,10 +34,16 @@
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//------------- Unaligned Memory Access -------------//
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// ARMv7+ (M3-M7, M23-M33) can access unaligned memory
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#if (defined(__ARM_ARCH) && (__ARM_ARCH >= 7))
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#define TUP_ARCH_STRICT_ALIGN 0
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#ifdef __ARM_ARCH
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// ARM Architecture set __ARM_FEATURE_UNALIGNED to 1 for mcu supports unaligned access
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#if defined(__ARM_FEATURE_UNALIGNED) && __ARM_FEATURE_UNALIGNED == 1
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#define TUP_ARCH_STRICT_ALIGN 0
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#else
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#define TUP_ARCH_STRICT_ALIGN 1
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#endif
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#else
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// TODO default to strict align for others
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// Should investigate other architecture such as risv, xtensa, mips for optimal setting
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#define TUP_ARCH_STRICT_ALIGN 1
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#endif
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@@ -52,6 +58,7 @@
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// NXP
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//--------------------------------------------------------------------+
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#if TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX)
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#define TUP_USBIP_IP3511
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#define TUP_DCD_ENDPOINT_MAX 5
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#elif TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
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@@ -60,14 +67,17 @@
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#define TUP_OHCI_RHPORTS 2
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#elif TU_CHECK_MCU(OPT_MCU_LPC51UXX)
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#define TUP_USBIP_IP3511
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#define TUP_DCD_ENDPOINT_MAX 5
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#elif TU_CHECK_MCU(OPT_MCU_LPC54XXX)
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#elif TU_CHECK_MCU(OPT_MCU_LPC54)
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// TODO USB0 has 5, USB1 has 6
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#define TUP_USBIP_IP3511
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#define TUP_DCD_ENDPOINT_MAX 6
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#elif TU_CHECK_MCU(OPT_MCU_LPC55XX)
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#elif TU_CHECK_MCU(OPT_MCU_LPC55)
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// TODO USB0 has 5, USB1 has 6
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#define TUP_USBIP_IP3511
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#define TUP_DCD_ENDPOINT_MAX 6
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#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
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@@ -327,6 +337,7 @@
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// Renesas
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//--------------------------------------------------------------------+
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#elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N, OPT_MCU_RAXXX)
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#define TUP_USBIP_RUSB2
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#define TUP_DCD_ENDPOINT_MAX 10
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//--------------------------------------------------------------------+
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