clean all IAR ending warning

demos/bsp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_cgu.c

@@ -696,11 +696,11 @@ uint32_t CGU_SetPLL0audio(void){
     LPC_CGU->PLL0AUDIO_MDIV = (0 << 28)  /* SELR */
         | (40 << 22)   /* SELI */
         | (31 << 17)   /* SELP */
-        | 11372;       /* MDEC */  
+        | 11372;       /* MDEC */
     /* set ndec, pdec register */
     LPC_CGU->PLL0AUDIO_NP_DIV = (22 << 12)       /* ndec */
-        | (10);               /* pdec */  
-    
+        | (10);               /* pdec */
+
     /* set fraction divider register. [21:15] = m, [14:0] = fractional value */
     LPC_CGU->PLL0AUDIO_FRAC = (86 << 15) | 0x1B7;
     LPC_CGU->PLL0AUDIO_CTRL = (6 << 24)   /* source = XTAL OSC 12 MHz */
@@ -708,8 +708,8 @@ uint32_t CGU_SetPLL0audio(void){
                       | _BIT(4);   /* CLKEN */
 #endif
     /* wait for lock */
-    while (!(LPC_CGU->PLL0AUDIO_STAT & 1)); 
-     
+    while (!(LPC_CGU->PLL0AUDIO_STAT & 1));
+
 	return CGU_ERROR_SUCCESS;
 }
 

demos/bsp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_i2c.c

@@ -552,7 +552,7 @@ end_stage:
 				I2C_IntCmd(I2Cx, FALSE);
 				// Send stop
 				I2C_Stop(I2Cx);
-				
+
 				I2C_MasterComplete[tmp] = TRUE;
 			}
 			break;

demos/bsp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_scu.c

@@ -40,7 +40,7 @@
 #include "lpc43xx_scu.h"
 
 /* Pin modes
-*  ========= 
+*  =========
 *  The EPUN and EPD bits in the SFS registers allow the selection of weak on-chip
 *  pull-up or pull-down resistors with a typical value of 50 kOhm for each pin or the
 *  selection of the repeater mode.
@@ -53,16 +53,16 @@
 *  typically be used to prevent a pin from floating (and potentially using significant power if it
 *  floats to an indeterminate state) if it is temporarily not driven.
 *  Repeater mode is enabled when both pull-up and pull-down are enabled.
-*  
+*
 *  To be able to receive a digital signal, the input buffer must be enabled through bit EZI in
 *  the pin configuration registers. By default, the input buffer is disabled.
 *  For pads that support both a digital and an analog function, the input buffer must be
 *  disabled before enabling the analog function.
-*  
+*
 *  All digital pins support a programmable glitch filter (bit ZIF), which can be switched on or
 *  off. By default, the glitch filter is on. The glitch filter should be disabled for
 *  clocking signals with frequencies higher than 30 MHz.
-*  
+*
 *  Normal-drive and high-speed pins support a programmable slew rate (bit EHS) to select
 *  between lower noise and low speed or higher noise and high speed . The typical
 *  frequencies supported are 50 MHz/80 MHz for normal-drive pins and 75 MHz/180 MHz for

demos/bsp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/system_LPC43xx.c

@@ -69,7 +69,7 @@ void SystemInit (void)
         fpuEnable();
 #endif
 #endif
-        
+
 #if !defined(CORE_M0)
 // Set up Cortex_M3 or M4 VTOR register to point to vector table
 // This code uses a toolchain defined symbol to locate the vector table