add support for native SAMD HCD
This commit is contained in:
Deadman
767
src/portable/microchip/samd/hcd_samd.c
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767
src/portable/microchip/samd/hcd_samd.c
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@@ -0,0 +1,767 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2024 ChrisDeadman
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#include "tusb_option.h"
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#if CFG_TUH_ENABLED && \
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!(defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421) && \
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(CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \
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CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \
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CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21)
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#include "host/hcd.h"
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#include "sam.h"
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/*------------------------------------------------------------------*/
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/* MACRO TYPEDEF CONSTANT ENUM
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*------------------------------------------------------------------*/
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#define USB_HOST_PTYPE_DIS 0x0
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#define USB_HOST_PTYPE_CTRL 0x1
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#define USB_HOST_PTYPE_ISO 0x2
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#define USB_HOST_PTYPE_BULK 0x3
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#define USB_HOST_PTYPE_INT 0x4
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#define USB_HOST_PTYPE_EXT 0x5
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#define USB_HOST_PCFG_PTOKEN_SETUP 0x0
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#define USB_HOST_PCFG_PTOKEN_IN 0x1
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#define USB_HOST_PCFG_PTOKEN_OUT 0x2
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#define USB_PCKSIZE_ENUM(size) \
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((size) >= 1024 ? 7 \
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: (size) >= 1023 ? 7 \
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: (size) > 256 ? 6 \
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: (size) > 128 ? 5 \
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: (size) > 64 ? 4 \
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: (size) > 32 ? 3 \
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: (size) > 16 ? 2 \
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: (size) > 8 ? 1 \
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: 0)
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// Uncomment to use fake frame number.
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// Low-Speed devices stall FNUM during enumeration :/
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// #define HCD_SAMD_FAKE_FNUM
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typedef struct {
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uint8_t dev_addr;
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uint8_t ep_addr;
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uint16_t max_packet_size;
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uint16_t xfer_length;
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uint16_t xfer_remaining;
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} usb_pipe_status_t;
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CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN static volatile UsbHostDescriptor usb_pipe_table[USB_PIPE_NUM];
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CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN static volatile usb_pipe_status_t usb_pipe_status_table[USB_PIPE_NUM];
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CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN static volatile uint32_t fake_fnum;
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static uint8_t samd_configure_pipe(uint8_t dev_addr, uint8_t ep_addr)
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{
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uint8_t pipe;
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uint8_t token;
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volatile usb_pipe_status_t* pipe_status;
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bool same_addr = false;
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bool same_ep_addr = false;
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// evaluate pipe token
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token = (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) ? USB_HOST_PCFG_PTOKEN_IN
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: tu_edpt_number(ep_addr) == 0 ? USB_HOST_PCFG_PTOKEN_SETUP
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: USB_HOST_PCFG_PTOKEN_OUT;
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TU_LOG3("samd_configure_pipe(token=%02X, dev_addr=%02X, ep_addr=%02X)=", token, dev_addr, ep_addr);
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// find already allocated pipe
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for (pipe = 0; pipe < USB_PIPE_NUM; pipe++) {
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pipe_status = &usb_pipe_status_table[pipe];
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same_addr = (pipe_status->dev_addr == dev_addr);
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same_ep_addr = (tu_edpt_number(pipe_status->ep_addr) == tu_edpt_number(ep_addr));
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if (same_ep_addr && (same_addr || (tu_edpt_number(ep_addr) == 0))) {
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break;
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}
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}
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// allocate from pool of free pipes
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if (pipe >= USB_PIPE_NUM) {
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for (pipe = 0; pipe < USB_PIPE_NUM; pipe++) {
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pipe_status = &usb_pipe_status_table[pipe];
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// found a free pipe
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if (pipe_status->dev_addr >= UINT8_MAX) {
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break;
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}
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}
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}
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// no pipe available :(
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if (pipe >= USB_PIPE_NUM) {
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TU_LOG3("ERR_NO_PIPE\r\n");
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return pipe;
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}
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TU_LOG3("%d\r\n", pipe);
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// no transfer should be in progress
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TU_ASSERT(((USB->HOST.HostPipe[pipe].PCFG.bit.PTYPE == USB_HOST_PTYPE_DIS) ||
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USB->HOST.HostPipe[pipe].PSTATUS.bit.PFREEZE == 1),
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USB_PIPE_NUM);
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// update addr and ep_addr
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pipe_status->dev_addr = dev_addr;
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pipe_status->ep_addr = ep_addr;
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usb_pipe_table[pipe].HostDescBank[0].CTRL_PIPE.bit.PDADDR = dev_addr;
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usb_pipe_table[pipe].HostDescBank[0].CTRL_PIPE.bit.PEPNUM = tu_edpt_number(ep_addr);
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// token specific configuration
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USB->HOST.HostPipe[pipe].PCFG.bit.PTOKEN = token;
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USB->HOST.HostPipe[pipe].PINTENCLR.reg = USB_HOST_PINTENCLR_MASK;
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if (token == USB_HOST_PCFG_PTOKEN_SETUP) {
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USB->HOST.HostPipe[pipe].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_DTGL;
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USB->HOST.HostPipe[pipe].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_BK0RDY;
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USB->HOST.HostPipe[pipe].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP;
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USB->HOST.HostPipe[pipe].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
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USB->HOST.HostPipe[pipe].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL;
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USB->HOST.HostPipe[pipe].PINTENSET.reg = USB_HOST_PINTENSET_PERR;
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} else if (token == USB_HOST_PCFG_PTOKEN_IN) {
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USB->HOST.HostPipe[pipe].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
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USB->HOST.HostPipe[pipe].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT_Msk;
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USB->HOST.HostPipe[pipe].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
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USB->HOST.HostPipe[pipe].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL;
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USB->HOST.HostPipe[pipe].PINTENSET.reg = USB_HOST_PINTENSET_PERR;
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} else {
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USB->HOST.HostPipe[pipe].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_BK0RDY;
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USB->HOST.HostPipe[pipe].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT_Msk;
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USB->HOST.HostPipe[pipe].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
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USB->HOST.HostPipe[pipe].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL;
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USB->HOST.HostPipe[pipe].PINTENSET.reg = USB_HOST_PINTENSET_PERR;
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}
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return pipe;
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}
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static void samd_free_pipe(uint8_t pipe)
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{
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volatile usb_pipe_status_t* pipe_status = &usb_pipe_status_table[pipe];
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pipe_status->dev_addr = UINT8_MAX;
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pipe_status->ep_addr = UINT8_MAX;
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pipe_status->max_packet_size = 0;
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pipe_status->xfer_length = 0;
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pipe_status->xfer_remaining = 0;
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USB->HOST.HostPipe[pipe].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE;
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USB->HOST.HostPipe[pipe].PCFG.reg &= ~USB_HOST_PCFG_PTYPE_Msk;
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USB->HOST.HostPipe[pipe].PINTENCLR.reg = USB_HOST_PINTENCLR_MASK;
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memset((uint8_t*) &usb_pipe_table[pipe], 0, sizeof(usb_pipe_table[pipe]));
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}
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static void samd_free_all_pipes(void)
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{
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for (uint8_t pipe = 0; pipe < USB_PIPE_NUM; pipe++) {
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samd_free_pipe(pipe);
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}
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}
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static bool samd_on_xfer(uint8_t pipe, xfer_result_t xfer_result)
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{
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uint16_t xfer_delta;
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bool xfer_complete;
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volatile usb_pipe_status_t* pipe_status = &usb_pipe_status_table[pipe];
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// freeze the pipe
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USB->HOST.HostPipe[pipe].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE;
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// get number of transferred bytes
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if (xfer_result == XFER_RESULT_SUCCESS) {
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xfer_delta = usb_pipe_table[pipe].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT;
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} else {
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xfer_delta = 0;
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}
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TU_LOG3(
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"samd_on_xfer(%d, result=%d, xdelta=%d, rem=%d)\r\n", xfer_result, pipe, xfer_delta, pipe_status->xfer_remaining);
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// update pipe status
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if (xfer_delta > pipe_status->xfer_remaining) {
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xfer_delta = pipe_status->xfer_remaining;
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}
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pipe_status->xfer_remaining -= xfer_delta;
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pipe_status->xfer_length += xfer_delta;
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// last packet handling
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if (xfer_delta < pipe_status->max_packet_size) {
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pipe_status->xfer_remaining = 0;
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}
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// transfer complete
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xfer_complete = (xfer_result != XFER_RESULT_SUCCESS) || (pipe_status->xfer_remaining == 0);
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if (xfer_complete) {
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return true;
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}
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// continue receiving
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if (tu_edpt_dir(pipe_status->ep_addr) == TUSB_DIR_IN) {
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usb_pipe_table[pipe].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
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USB->HOST.HostPipe[pipe].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_BK0RDY;
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}
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// continue sending
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else {
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usb_pipe_table[pipe].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT =
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(pipe_status->xfer_remaining < pipe_status->max_packet_size) ? pipe_status->xfer_remaining
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: pipe_status->max_packet_size;
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USB->HOST.HostPipe[pipe].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
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}
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// advance packet buffer
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usb_pipe_table[pipe].HostDescBank[0].ADDR.reg += xfer_delta;
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// start next transfer
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USB->HOST.HostPipe[pipe].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_PFREEZE;
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return false;
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}
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//--------------------------------------------------------------------+
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// Controller API
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//--------------------------------------------------------------------+
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// Interrupt Handler
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void hcd_int_handler(uint8_t rhport, bool in_isr)
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{
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(void) rhport;
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uint16_t int_flags;
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uint8_t pint_flags;
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xfer_result_t xfer_result;
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volatile usb_pipe_status_t* pipe_status;
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//
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// Check INTFLAG
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//
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int_flags = USB->HOST.INTFLAG.reg;
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if (int_flags & USB_HOST_INTFLAG_HSOF) {
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USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF;
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}
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if (int_flags & USB_HOST_INTFLAG_RST) {
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TU_LOG2("USB_HOST_INTFLAG_RST\r\n");
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USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST;
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}
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if (int_flags & USB_HOST_INTFLAG_WAKEUP) {
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TU_LOG3("USB_HOST_INTFLAG_WAKEUP\r\n");
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USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP;
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}
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if (int_flags & USB_HOST_INTFLAG_DNRSM) {
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TU_LOG3("USB_HOST_INTFLAG_DNRSM\r\n");
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USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM;
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}
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if (int_flags & USB_HOST_INTFLAG_UPRSM) {
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TU_LOG3("USB_HOST_INTFLAG_UPRSM\r\n");
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USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM;
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}
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if (int_flags & USB_HOST_INTFLAG_RAMACER) {
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TU_LOG1("USB_HOST_INTFLAG_RAMACER\r\n");
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USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER;
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}
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if (int_flags & USB_HOST_INTFLAG_DCONN) {
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USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN;
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hcd_event_device_attach(rhport, in_isr);
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}
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if (int_flags & USB_HOST_INTFLAG_DDISC) {
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USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC;
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hcd_event_device_remove(rhport, in_isr);
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}
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// handle pipe interrupts
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for (uint8_t pipe = 0; pipe < USB_PIPE_NUM; pipe++) {
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// get pipe handle
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pipe_status = &usb_pipe_status_table[pipe];
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if (pipe_status->dev_addr >= UINT8_MAX) {
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continue;
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}
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//
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// Check PINTFLAG
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//
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pint_flags = USB->HOST.HostPipe[pipe].PINTFLAG.reg;
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xfer_result = XFER_RESULT_INVALID;
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if (pint_flags & USB_HOST_PINTFLAG_TRCPT0) {
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USB->HOST.HostPipe[pipe].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0;
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xfer_result = XFER_RESULT_SUCCESS;
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}
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if (pint_flags & USB_HOST_PINTFLAG_TRCPT1) {
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USB->HOST.HostPipe[pipe].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1;
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xfer_result = XFER_RESULT_SUCCESS;
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}
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if (pint_flags & USB_HOST_PINTFLAG_TXSTP) {
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USB->HOST.HostPipe[pipe].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP;
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xfer_result = XFER_RESULT_SUCCESS;
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}
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if (pint_flags & USB_HOST_PINTFLAG_STALL) {
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TU_LOG2("USB_HOST_PINTFLAG_STALL\r\n");
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USB->HOST.HostPipe[pipe].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL;
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xfer_result = XFER_RESULT_STALLED;
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}
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if (pint_flags & USB_HOST_PINTFLAG_TRFAIL) {
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USB->HOST.HostPipe[pipe].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL;
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if (usb_pipe_table[pipe].HostDescBank[0].STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) {
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TU_LOG1("USB_HOST_STATUS_BK_ERRORFLOW\r\n");
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xfer_result = XFER_RESULT_FAILED;
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} else if (usb_pipe_table[pipe].HostDescBank[0].STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) {
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TU_LOG1("USB_HOST_STATUS_BK_CRCERR\r\n");
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xfer_result = XFER_RESULT_FAILED;
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} else {
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// SAMD Quirk #1:
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// Likes to report TRFAIL for no apparent reason -> ignore
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}
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}
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if (pint_flags & USB_HOST_PINTFLAG_PERR) {
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USB->HOST.HostPipe[pipe].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR;
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// Handled by STATUS_PIPE checks below
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}
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//
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// Check STATUS_PIPE
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//
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if (usb_pipe_table[pipe].HostDescBank[0].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) {
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TU_LOG1("USB_HOST_STATUS_PIPE_DTGLER\r\n");
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usb_pipe_table[pipe].HostDescBank[0].STATUS_PIPE.reg &= ~USB_HOST_STATUS_PIPE_DTGLER;
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xfer_result = XFER_RESULT_FAILED;
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}
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if (usb_pipe_table[pipe].HostDescBank[0].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) {
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TU_LOG1("USB_HOST_STATUS_PIPE_DAPIDER\r\n");
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usb_pipe_table[pipe].HostDescBank[0].STATUS_PIPE.reg &= ~USB_HOST_STATUS_PIPE_DAPIDER;
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xfer_result = XFER_RESULT_FAILED;
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}
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if (usb_pipe_table[pipe].HostDescBank[0].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) {
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TU_LOG1("USB_HOST_STATUS_PIPE_PIDER\r\n");
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usb_pipe_table[pipe].HostDescBank[0].STATUS_PIPE.reg &= ~USB_HOST_STATUS_PIPE_PIDER;
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xfer_result = XFER_RESULT_FAILED;
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}
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if (usb_pipe_table[pipe].HostDescBank[0].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) {
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TU_LOG1("USB_HOST_STATUS_PIPE_CRC16ER\r\n");
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usb_pipe_table[pipe].HostDescBank[0].STATUS_PIPE.reg &= ~USB_HOST_STATUS_PIPE_CRC16ER;
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xfer_result = XFER_RESULT_FAILED;
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}
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if (usb_pipe_table[pipe].HostDescBank[0].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) {
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usb_pipe_table[pipe].HostDescBank[0].STATUS_PIPE.reg &= ~USB_HOST_STATUS_PIPE_TOUTER;
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if ((USB->HOST.HostPipe[pipe].PCFG.bit.PTYPE == USB_HOST_PTYPE_INT) &&
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(tu_edpt_dir(pipe_status->ep_addr) == TUSB_DIR_IN)) {
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// ignore timeouts from INT pipes
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} else {
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if (xfer_result == XFER_RESULT_INVALID) {
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xfer_result = XFER_RESULT_TIMEOUT;
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}
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}
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}
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// prevent PERR from too high error counts, that is handled by TinyUSB anyways
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usb_pipe_table[pipe].HostDescBank[0].STATUS_PIPE.bit.ERCNT = 0;
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||||
// no updates
|
||||
if (xfer_result == XFER_RESULT_INVALID) {
|
||||
continue;
|
||||
}
|
||||
|
||||
// continue / complete transfer
|
||||
if (samd_on_xfer(pipe, xfer_result)) {
|
||||
hcd_event_xfer_complete(pipe_status->dev_addr, pipe_status->ep_addr, pipe_status->xfer_length, xfer_result, true);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Initialize controller to host mode
|
||||
bool hcd_init(uint8_t rhport)
|
||||
{
|
||||
TU_ASSERT(rhport == 0);
|
||||
|
||||
fake_fnum = 0;
|
||||
|
||||
// reset to get in a clean state.
|
||||
USB->HOST.CTRLA.bit.SWRST = 1;
|
||||
while (USB->HOST.SYNCBUSY.bit.SWRST == 0)
|
||||
;
|
||||
while (USB->HOST.SYNCBUSY.bit.SWRST == 1)
|
||||
;
|
||||
|
||||
// load pad calibration
|
||||
USB->HOST.PADCAL.bit.TRANSP = (*((uint32_t*) USB_FUSES_TRANSP_ADDR) & USB_FUSES_TRANSP_Msk) >> USB_FUSES_TRANSP_Pos;
|
||||
USB->HOST.PADCAL.bit.TRANSN = (*((uint32_t*) USB_FUSES_TRANSN_ADDR) & USB_FUSES_TRANSN_Msk) >> USB_FUSES_TRANSN_Pos;
|
||||
USB->HOST.PADCAL.bit.TRIM = (*((uint32_t*) USB_FUSES_TRIM_ADDR) & USB_FUSES_TRIM_Msk) >> USB_FUSES_TRIM_Pos;
|
||||
|
||||
USB->HOST.QOSCTRL.bit.CQOS = 3; // High Quality
|
||||
USB->HOST.QOSCTRL.bit.DQOS = 3; // High Quality
|
||||
|
||||
// configure host-mode
|
||||
samd_free_all_pipes(); // initializes pipe handles and usb_pipe_table
|
||||
USB->HOST.DESCADD.reg = (uint32_t) (&usb_pipe_table[0]);
|
||||
USB->HOST.CTRLB.reg = USB_HOST_CTRLB_SPDCONF_NORMAL | USB_HOST_CTRLB_VBUSOK;
|
||||
USB->HOST.CTRLA.reg = USB_CTRLA_MODE_HOST | USB_CTRLA_ENABLE | USB_CTRLA_RUNSTDBY;
|
||||
while (USB->HOST.SYNCBUSY.bit.ENABLE == 1)
|
||||
;
|
||||
|
||||
// enable basic USB interrupts
|
||||
USB->HOST.INTFLAG.reg |= USB->HOST.INTFLAG.reg; // clear pending
|
||||
USB->HOST.INTENCLR.reg = USB_HOST_INTENCLR_MASK;
|
||||
USB->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN;
|
||||
USB->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC;
|
||||
USB->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP;
|
||||
USB->HOST.INTENSET.reg = USB_HOST_INTENSET_RST;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
#if CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X
|
||||
|
||||
// Enable USB interrupt
|
||||
void hcd_int_enable(uint8_t rhport)
|
||||
{
|
||||
(void) rhport;
|
||||
NVIC_EnableIRQ(USB_0_IRQn);
|
||||
NVIC_EnableIRQ(USB_1_IRQn);
|
||||
NVIC_EnableIRQ(USB_2_IRQn);
|
||||
NVIC_EnableIRQ(USB_3_IRQn);
|
||||
}
|
||||
|
||||
// Disable USB interrupt
|
||||
void hcd_int_disable(uint8_t rhport)
|
||||
{
|
||||
(void) rhport;
|
||||
NVIC_DisableIRQ(USB_3_IRQn);
|
||||
NVIC_DisableIRQ(USB_2_IRQn);
|
||||
NVIC_DisableIRQ(USB_1_IRQn);
|
||||
NVIC_DisableIRQ(USB_0_IRQn);
|
||||
}
|
||||
|
||||
#elif CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \
|
||||
CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21
|
||||
|
||||
// Enable USB interrupt
|
||||
void hcd_int_enable(uint8_t rhport)
|
||||
{
|
||||
(void) rhport;
|
||||
NVIC_EnableIRQ(USB_IRQn);
|
||||
}
|
||||
|
||||
// Disable USB interrupt
|
||||
void hcd_int_disable(uint8_t rhport)
|
||||
{
|
||||
(void) rhport;
|
||||
NVIC_DisableIRQ(USB_IRQn);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#error "No implementation available for hcd_int_enable / hcd_int_disable"
|
||||
|
||||
#endif
|
||||
|
||||
// Get frame number (1ms)
|
||||
uint32_t hcd_frame_number(uint8_t rhport)
|
||||
{
|
||||
(void) rhport;
|
||||
|
||||
// SAMD Quirk #2:
|
||||
// FNUM is stalled before enumeration of Low-Speed devices.
|
||||
// internal frame counter can be used as workaround (not very accurate)
|
||||
#ifdef HCD_SAMD_FAKE_FNUM
|
||||
uint8_t start, current, prev;
|
||||
uint8_t loop_count = (USB->HOST.STATUS.bit.SPEED == TUSB_SPEED_HIGH) ? 8 : 1;
|
||||
for (uint8_t i = 0; i < loop_count; i++) {
|
||||
start = USB->HOST.FLENHIGH.reg;
|
||||
current = start;
|
||||
// wait until wrap-around
|
||||
prev = current;
|
||||
while (current <= start) {
|
||||
current = USB->HOST.FLENHIGH.reg;
|
||||
if (current > prev)
|
||||
break;
|
||||
prev = current;
|
||||
}
|
||||
// wait until start is reached again
|
||||
prev = current;
|
||||
while (current > start) {
|
||||
current = USB->HOST.FLENHIGH.reg;
|
||||
if (current > prev)
|
||||
break;
|
||||
prev = current;
|
||||
}
|
||||
}
|
||||
fake_fnum += 1;
|
||||
return fake_fnum;
|
||||
#else
|
||||
return USB->HOST.FNUM.bit.FNUM;
|
||||
#endif // HCD_SAMD_FAKE_FNUM
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Port API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
// Get the current connect status of roothub port
|
||||
bool hcd_port_connect_status(uint8_t rhport)
|
||||
{
|
||||
TU_ASSERT(rhport == 0);
|
||||
return USB->HOST.STATUS.bit.LINESTATE != 0;
|
||||
}
|
||||
|
||||
// Reset USB bus on the port. Return immediately, bus reset sequence may not be
|
||||
// complete. Some port would require hcd_port_reset_end() to be invoked after 10ms to
|
||||
// complete the reset sequence.
|
||||
void hcd_port_reset(uint8_t rhport)
|
||||
{
|
||||
hcd_int_disable(rhport);
|
||||
samd_free_all_pipes();
|
||||
USB->HOST.INTFLAG.reg |= USB->HOST.INTFLAG.reg; // clear pending
|
||||
USB->HOST.CTRLB.bit.BUSRESET = 1;
|
||||
fake_fnum = 0;
|
||||
}
|
||||
|
||||
// Complete bus reset sequence, may be required by some controllers
|
||||
void hcd_port_reset_end(uint8_t rhport)
|
||||
{
|
||||
while (USB->HOST.INTFLAG.bit.RST == 0)
|
||||
;
|
||||
USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST;
|
||||
USB->HOST.CTRLB.bit.SOFE = 1;
|
||||
hcd_int_enable(rhport);
|
||||
}
|
||||
|
||||
// Get port link speed
|
||||
tusb_speed_t hcd_port_speed_get(uint8_t rhport)
|
||||
{
|
||||
(void) rhport;
|
||||
|
||||
switch (USB->HOST.STATUS.bit.SPEED) {
|
||||
case 0:
|
||||
return TUSB_SPEED_FULL;
|
||||
case 1:
|
||||
return TUSB_SPEED_LOW;
|
||||
case 2:
|
||||
return TUSB_SPEED_HIGH;
|
||||
default:
|
||||
return TUSB_SPEED_INVALID;
|
||||
}
|
||||
}
|
||||
|
||||
// HCD closes all opened endpoints belong to this device
|
||||
void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
|
||||
{
|
||||
(void) rhport;
|
||||
|
||||
for (uint8_t pipe = 0; pipe < USB_PIPE_NUM; pipe++) {
|
||||
volatile usb_pipe_status_t* pipe_status = &usb_pipe_status_table[pipe];
|
||||
if (pipe_status->dev_addr == dev_addr) {
|
||||
samd_free_pipe(pipe);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Endpoints API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
// Open an endpoint
|
||||
bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const* ep_desc)
|
||||
{
|
||||
TU_ASSERT(rhport == 0);
|
||||
|
||||
uint8_t pipe;
|
||||
volatile usb_pipe_status_t* pipe_status;
|
||||
const uint8_t ep_addr = ep_desc->bEndpointAddress;
|
||||
const uint8_t bmAttributes = (ep_desc->bmAttributes.xfer) |
|
||||
((ep_desc->bmAttributes.sync) << 2) |
|
||||
((ep_desc->bmAttributes.usage) << 4);
|
||||
|
||||
// configure the pipe
|
||||
pipe = samd_configure_pipe(dev_addr, ep_addr);
|
||||
if (pipe >= USB_PIPE_NUM) {
|
||||
return false;
|
||||
}
|
||||
|
||||
// initial configuration
|
||||
pipe_status = &usb_pipe_status_table[pipe];
|
||||
USB->HOST.HostPipe[pipe].PCFG.reg &= ~USB_HOST_PCFG_PTYPE_Msk;
|
||||
USB->HOST.HostPipe[pipe].PCFG.bit.PTYPE = bmAttributes + 1;
|
||||
USB->HOST.HostPipe[pipe].BINTERVAL.reg = ep_desc->bInterval;
|
||||
USB->HOST.HostPipe[pipe].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_DTGL;
|
||||
USB->HOST.HostPipe[pipe].PINTENCLR.reg = USB_HOST_PINTENCLR_MASK;
|
||||
pipe_status->max_packet_size = ep_desc->wMaxPacketSize;
|
||||
usb_pipe_table[pipe].HostDescBank[0].PCKSIZE.bit.SIZE = USB_PCKSIZE_ENUM(pipe_status->max_packet_size);
|
||||
usb_pipe_table[pipe].HostDescBank[0].PCKSIZE.bit.AUTO_ZLP = 0;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
// Submit a special transfer to send 8-byte Setup Packet, when complete
|
||||
// hcd_event_xfer_complete() must be invoked
|
||||
bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
|
||||
{
|
||||
TU_ASSERT(rhport == 0);
|
||||
|
||||
uint8_t pipe;
|
||||
volatile usb_pipe_status_t* pipe_status;
|
||||
|
||||
// configure the pipe
|
||||
pipe = samd_configure_pipe(dev_addr, 0);
|
||||
if (pipe >= USB_PIPE_NUM) {
|
||||
return false;
|
||||
}
|
||||
|
||||
// prepare transfer
|
||||
pipe_status = &usb_pipe_status_table[pipe];
|
||||
usb_pipe_table[pipe].HostDescBank[0].ADDR.reg = (uint32_t) setup_packet;
|
||||
pipe_status->xfer_remaining = 8;
|
||||
pipe_status->xfer_length = 0;
|
||||
usb_pipe_table[pipe].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT = 8;
|
||||
usb_pipe_table[pipe].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
|
||||
USB->HOST.HostPipe[pipe].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
|
||||
|
||||
// clear pending interrupts
|
||||
USB->HOST.HostPipe[pipe].PINTFLAG.reg |= USB->HOST.HostPipe[pipe].PINTFLAG.reg;
|
||||
|
||||
// begin transfer
|
||||
USB->HOST.HostPipe[pipe].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_PFREEZE;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
|
||||
bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t* buffer, uint16_t buflen)
|
||||
{
|
||||
TU_ASSERT(rhport == 0);
|
||||
|
||||
uint8_t pipe;
|
||||
volatile usb_pipe_status_t* pipe_status;
|
||||
|
||||
// configure the pipe
|
||||
pipe = samd_configure_pipe(dev_addr, ep_addr);
|
||||
if (pipe >= USB_PIPE_NUM) {
|
||||
return false;
|
||||
}
|
||||
|
||||
// prepare transfer
|
||||
pipe_status = &usb_pipe_status_table[pipe];
|
||||
usb_pipe_table[pipe].HostDescBank[0].ADDR.reg = (uint32_t) buffer;
|
||||
pipe_status->xfer_remaining = buflen;
|
||||
pipe_status->xfer_length = 0;
|
||||
// receive data
|
||||
if (tu_edpt_dir(pipe_status->ep_addr) == TUSB_DIR_IN) {
|
||||
usb_pipe_table[pipe].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
|
||||
usb_pipe_table[pipe].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = pipe_status->max_packet_size;
|
||||
USB->HOST.HostPipe[pipe].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_BK0RDY;
|
||||
}
|
||||
// send data
|
||||
else {
|
||||
usb_pipe_table[pipe].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT =
|
||||
(pipe_status->xfer_remaining < pipe_status->max_packet_size) ? pipe_status->xfer_remaining
|
||||
: pipe_status->max_packet_size;
|
||||
usb_pipe_table[pipe].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
|
||||
USB->HOST.HostPipe[pipe].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
|
||||
}
|
||||
|
||||
// clear pending interrupts
|
||||
USB->HOST.HostPipe[pipe].PINTFLAG.reg |= USB->HOST.HostPipe[pipe].PINTFLAG.reg;
|
||||
|
||||
// begin transfer
|
||||
USB->HOST.HostPipe[pipe].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_PFREEZE;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
// Abort a queued transfer. Note: it can only abort transfer that has not been
|
||||
// started Return true if a queued transfer is aborted, false if there is no transfer
|
||||
// to abort
|
||||
bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr)
|
||||
{
|
||||
TU_ASSERT(rhport == 0);
|
||||
|
||||
uint8_t pipe;
|
||||
volatile usb_pipe_status_t* pipe_status;
|
||||
|
||||
TU_LOG3("hcd_edpt_abort_xfer(dev_addr=%02X, ep_addr=%02X)=", dev_addr, ep_addr);
|
||||
|
||||
// find the pipe
|
||||
for (pipe = 0; pipe < USB_PIPE_NUM; pipe++) {
|
||||
pipe_status = &usb_pipe_status_table[pipe];
|
||||
if ((pipe_status->dev_addr == dev_addr) && (pipe_status->ep_addr == ep_addr)) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// pipe not found
|
||||
if (pipe >= USB_PIPE_NUM) {
|
||||
TU_LOG3("ERR_NO_PIPE\r\n");
|
||||
return false;
|
||||
}
|
||||
TU_LOG3("%d\r\n", pipe);
|
||||
|
||||
// no transfer in progress
|
||||
if (USB->HOST.HostPipe[pipe].PSTATUS.bit.PFREEZE == 1) {
|
||||
return false;
|
||||
}
|
||||
|
||||
// abort the transfer
|
||||
USB->HOST.HostPipe[pipe].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE;
|
||||
pipe_status = &usb_pipe_status_table[pipe];
|
||||
pipe_status->xfer_length = 0;
|
||||
pipe_status->xfer_remaining = 0;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
// clear stall, data toggle is also reset to DATA0
|
||||
bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr)
|
||||
{
|
||||
TU_ASSERT(rhport == 0);
|
||||
|
||||
uint8_t pipe;
|
||||
volatile usb_pipe_status_t* pipe_status;
|
||||
|
||||
TU_LOG3("hcd_edpt_clear_stall(dev_addr=%02X, ep_addr=%02X)=", dev_addr, ep_addr);
|
||||
|
||||
// find the pipe
|
||||
for (pipe = 0; pipe < USB_PIPE_NUM; pipe++) {
|
||||
pipe_status = &usb_pipe_status_table[pipe];
|
||||
if ((pipe_status->dev_addr == dev_addr) && (pipe_status->ep_addr == ep_addr)) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// pipe not found
|
||||
if (pipe >= USB_PIPE_NUM) {
|
||||
TU_LOG3("ERR_NO_PIPE\r\n");
|
||||
return false;
|
||||
}
|
||||
TU_LOG3("%d\r\n", pipe);
|
||||
|
||||
// clear pending interrupts
|
||||
USB->HOST.HostPipe[pipe].PINTFLAG.reg |= USB->HOST.HostPipe[pipe].PINTFLAG.reg;
|
||||
|
||||
// clear stalled state
|
||||
USB->HOST.HostPipe[pipe].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE;
|
||||
USB->HOST.HostPipe[pipe].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_DTGL;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user