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Merge branch 'master' into fork/HiFiPhile/stm32_cache

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This commit is contained in:
hathach
2025-07-03 17:07:52 +07:00
parent ea02e929b4 9d872d529f
commit 970c8b744e
107 changed files with 3261 additions and 1893 deletions
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8
hw/bsp/board.c
View File

@@ -60,13 +60,11 @@ int sys_read(int fhdl, char *buf, size_t count) {
int rd = (int) SEGGER_RTT_Read(0, buf, count);
return (rd > 0) ? rd : -1;
}
#endif
#elif defined(LOGGER_SWO)
#define ITM_BASE 0xE0000000
#define ITM_STIM0 (*((volatile uint8_t*)(ITM_BASE + 0)))
#define ITM_TER *((volatile uint32_t*)(ITM_BASE + 0xE00))
#define ITM_TCR *((volatile uint32_t*)(ITM_BASE + 0xE80))
@@ -150,6 +148,9 @@ int board_getchar(void) {
return (sys_read(0, &c, 1) > 0) ? (int) c : (-1);
}
void board_putchar(int c) {
sys_write(0, (const char*)&c, 1);
}
uint32_t tusb_time_millis_api(void) {
return board_millis();
@@ -158,7 +159,7 @@ uint32_t tusb_time_millis_api(void) {
//--------------------------------------------------------------------
// FreeRTOS hooks
//--------------------------------------------------------------------
#if CFG_TUSB_OS == OPT_OS_FREERTOS && !TUSB_MCU_VENDOR_ESPRESSIF
#if CFG_TUSB_OS == OPT_OS_FREERTOS && !defined(ESP_PLATFORM)
#include "FreeRTOS.h"
#include "task.h"
@@ -240,5 +241,4 @@ void vApplicationSetupTimerInterrupt(void) {
}
#endif
#endif

3
hw/bsp/board_api.h
View File

@@ -41,7 +41,7 @@ extern "C" {
#if CFG_TUSB_OS == OPT_OS_ZEPHYR
#include <zephyr/kernel.h>
#elif CFG_TUSB_OS == OPT_OS_FREERTOS
#if TUSB_MCU_VENDOR_ESPRESSIF
#ifdef ESP_PLATFORM
// ESP-IDF need "freertos/" prefix in include path.
// CFG_TUSB_OS_INC_PATH should be defined accordingly.
#include "freertos/FreeRTOS.h"
@@ -195,6 +195,7 @@ static inline void board_delay(uint32_t ms) {
// stdio getchar() is blocking, this is non-blocking version
int board_getchar(void);
void board_putchar(int c);
#ifdef __cplusplus
}

1
hw/bsp/brtmm90x/family.mk
View File

@@ -13,7 +13,6 @@ else
# The submodule BRTSG-FOSS/ft90x-sdk contains header files and source
# code for the Bridgetek SDK. This can be used instead of the prebuilt
# library.
DEPS_SUBMODULES += hw/mcu/bridgetek/ft9xx/ft90x-sdk
# The SDK can be used to load specific files from the Bridgetek SDK.
FT9XX_SDK = hw/mcu/bridgetek/ft9xx/ft90x-sdk/Source
INC += "$(TOP)/$(FT9XX_SDK)/include"

1
hw/bsp/ch32f20x/family.mk
View File

@@ -1,6 +1,5 @@
# Submodules
CH32F20X_SDK = hw/mcu/wch/ch32f20x
DEPS_SUBMODULES += $(CH32F20X_SDK)
# WCH-SDK paths
CH32F20X_SDK_SRC = $(CH32F20X_SDK)/EVT/EXAM/SRC

4
hw/bsp/espressif/boards/family.c
View File

@@ -156,6 +156,10 @@ int board_getchar(void) {
return getchar();
}
void board_putchar(int c) {
putchar(c);
}
//--------------------------------------------------------------------
// PHY Init
//--------------------------------------------------------------------

2
hw/bsp/espressif/family.cmake
View File

@@ -1,5 +1,3 @@
cmake_minimum_required(VERSION 3.5)
# Apply board specific content i.e IDF_TARGET must be set before project.cmake is included
include("${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake")
string(TOUPPER ${IDF_TARGET} FAMILY_MCUS)

34
hw/bsp/espressif/family.mk
View File

@@ -1,34 +0,0 @@
#DEPS_SUBMODULES +=
UF2_FAMILY_ID_esp32s2 = 0xbfdd4eee
UF2_FAMILY_ID_esp32s3 = 0xc47e5767
BOARD_CMAKE := $(file < $(TOP)/$(BOARD_PATH)/board.cmake)
ifneq ($(findstring esp32s2,$(BOARD_CMAKE)),)
IDF_TARGET = esp32s2
else
ifneq ($(findstring esp32s3,$(BOARD_CMAKE)),)
IDF_TARGET = esp32s3
endif
endif
.PHONY: all clean flash bootloader-flash app-flash erase monitor dfu-flash dfu
all:
idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) build
build: all
fullclean:
if test -f sdkconfig; then $(RM) -f sdkconfig ; fi
if test -d $(BUILD); then $(RM) -rf $(BUILD) ; fi
idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) $@
clean flash bootloader-flash app-flash erase monitor dfu-flash dfu size size-components size-files:
idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) $@
uf2: $(BUILD)/$(PROJECT).uf2
$(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).bin
@echo CREATE $@
$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID_$(IDF_TARGET)) -b 0x0 -c -o $@ $^

2
hw/bsp/family_support.cmake
View File

@@ -221,6 +221,8 @@ function(family_configure_common TARGET RTOS)
target_include_directories(${TARGET} PUBLIC ${TOP}/lib/SEGGER_RTT/RTT)
# target_compile_definitions(${TARGET} PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL)
endif ()
else ()
target_compile_definitions(${TARGET} PUBLIC LOGGER_UART)
endif ()
if (CMAKE_C_COMPILER_ID STREQUAL "GNU" OR CMAKE_C_COMPILER_ID STREQUAL "Clang")

1
hw/bsp/imxrt/family.mk
View File

@@ -1,6 +1,5 @@
UF2_FAMILY_ID = 0x4fb2d5bd
SDK_DIR = hw/mcu/nxp/mcux-sdk
DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
include $(TOP)/$(BOARD_PATH)/board.mk

1
hw/bsp/kinetis_k/family.mk
View File

@@ -1,5 +1,4 @@
SDK_DIR = hw/mcu/nxp/mcux-sdk
DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
MCU_DIR = $(SDK_DIR)/devices/${MCU_VARIANT}
include $(TOP)/$(BOARD_PATH)/board.mk

1
hw/bsp/kinetis_kl/family.mk
View File

@@ -1,5 +1,4 @@
SDK_DIR = hw/mcu/nxp/mcux-sdk
DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
MCU_DIR = $(SDK_DIR)/devices/$(MCU)
include $(TOP)/$(BOARD_PATH)/board.mk

2
hw/bsp/lpc13/boards/lpcxpresso1347/board.mk
View File

@@ -1,5 +1,3 @@
DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
CFLAGS += \
-DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))'

2
hw/bsp/lpc13/family.mk
View File

@@ -1,5 +1,3 @@
DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
MCU_DIR = hw/mcu/nxp/lpcopen/lpc13xx/lpc_chip_13xx
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m3

2
hw/bsp/lpc15/family.mk
View File

@@ -1,5 +1,3 @@
DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m3

2
hw/bsp/lpc17/family.mk
View File

@@ -1,5 +1,3 @@
DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m3

1
hw/bsp/lpc18/family.mk
View File

@@ -1,4 +1,3 @@
DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
MCU_DIR = hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx
include $(TOP)/$(BOARD_PATH)/board.mk

2
hw/bsp/lpc40/family.mk
View File

@@ -1,5 +1,3 @@
DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
MCU_DIR = hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m4

1
hw/bsp/lpc43/family.mk
View File

@@ -1,4 +1,3 @@
DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
SDK_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
include ${TOP}/${BOARD_PATH}/board.mk

1
hw/bsp/lpc54/family.mk
View File

@@ -1,5 +1,4 @@
SDK_DIR = hw/mcu/nxp/mcux-sdk
DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m4

1
hw/bsp/lpc55/family.mk
View File

@@ -1,6 +1,5 @@
UF2_FAMILY_ID = 0x2abc77ec
SDK_DIR = hw/mcu/nxp/mcux-sdk
DEPS_SUBMODULES += lib/CMSIS_5 lib/sct_neopixel $(SDK_DIR)
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m33

2
hw/bsp/mcx/family.mk
View File

@@ -1,8 +1,6 @@
UF2_FAMILY_ID = 0x2abc77ec
SDK_DIR = hw/mcu/nxp/mcux-sdk
DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
include $(TOP)/$(BOARD_PATH)/board.mk
# Default to Highspeed PORT1

48
hw/bsp/msp430/family.cmake
View File

@@ -11,36 +11,37 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/msp430_${T
set(FAMILY_MCUS MSP430x5xx CACHE INTERNAL "")
#------------------------------------
# BOARD_TARGET
#------------------------------------
# only need to be built ONCE for all examples
function(add_board_target BOARD_TARGET)
if (NOT TARGET ${BOARD_TARGET})
add_library(${BOARD_TARGET} INTERFACE)
target_compile_definitions(${BOARD_TARGET} INTERFACE
CFG_TUD_ENDPOINT0_SIZE=8
CFG_EXAMPLE_VIDEO_READONLY
CFG_EXAMPLE_MSC_READONLY
)
target_include_directories(${BOARD_TARGET} INTERFACE
${CMAKE_CURRENT_FUNCTION_LIST_DIR}
${SDK_DIR}
)
if (TARGET ${BOARD_TARGET})
return()
endif ()
update_board(${BOARD_TARGET})
add_library(${BOARD_TARGET} INTERFACE)
target_compile_definitions(${BOARD_TARGET} INTERFACE
CFG_TUD_ENDPOINT0_SIZE=8
CFG_EXAMPLE_VIDEO_READONLY
CFG_EXAMPLE_MSC_READONLY
)
target_include_directories(${BOARD_TARGET} INTERFACE
${CMAKE_CURRENT_FUNCTION_LIST_DIR}
${SDK_DIR}
)
if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
target_link_options(${BOARD_TARGET} INTERFACE
"LINKER:--script=${LD_FILE_GNU}"
-L${SDK_DIR}
)
elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
target_link_options(${BOARD_TARGET} INTERFACE
"LINKER:--config=${LD_FILE_IAR}"
)
endif ()
update_board(${BOARD_TARGET})
if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
target_link_options(${BOARD_TARGET} INTERFACE
"LINKER:--script=${LD_FILE_GNU}"
-L${SDK_DIR}
)
elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
target_link_options(${BOARD_TARGET} INTERFACE
"LINKER:--config=${LD_FILE_IAR}"
)
endif ()
endfunction()
@@ -75,7 +76,6 @@ function(family_configure_example TARGET RTOS)
)
target_link_libraries(${TARGET} PUBLIC board_${BOARD})
# Flashing
family_add_bin_hex(${TARGET})
family_flash_msp430flasher(${TARGET})

1
hw/bsp/msp430/family.mk
View File

@@ -1,5 +1,4 @@
CROSS_COMPILE = msp430-elf-
DEPS_SUBMODULES += hw/mcu/ti
SKIP_NANOLIB = 1
SDK_DIR = hw/mcu/ti/msp430/msp430-gcc-support-files/include

2
hw/bsp/nutiny_nuc121s/board.mk
View File

@@ -1,5 +1,3 @@
DEPS_SUBMODULES += hw/mcu/nuvoton
CFLAGS += \
-flto \
-mthumb \

2
hw/bsp/nutiny_nuc125s/board.mk
View File

@@ -1,5 +1,3 @@
DEPS_SUBMODULES += hw/mcu/nuvoton
CFLAGS += \
-flto \
-mthumb \

2
hw/bsp/nutiny_nuc126v/board.mk
View File

@@ -1,5 +1,3 @@
DEPS_SUBMODULES += hw/mcu/nuvoton
CFLAGS += \
-flto \
-mthumb \

2
hw/bsp/nutiny_sdk_nuc120/board.mk
View File

@@ -1,5 +1,3 @@
DEPS_SUBMODULES += hw/mcu/nuvoton
CFLAGS += \
-flto \
-mthumb \

2
hw/bsp/nutiny_sdk_nuc505/board.mk
View File

@@ -1,5 +1,3 @@
DEPS_SUBMODULES += hw/mcu/nuvoton
CFLAGS += \
-flto \
-mthumb \

6
hw/bsp/rp2040/family.c
View File

@@ -254,7 +254,7 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) {
int board_uart_read(uint8_t *buf, int len) {
#ifdef UART_DEV
int count = 0;
while ( (count < len) && uart_is_readable(uart_inst) ) {
while ((count < len) && uart_is_readable(uart_inst)) {
buf[count] = uart_getc(uart_inst);
count++;
}
@@ -282,6 +282,10 @@ int board_getchar(void) {
return getchar_timeout_us(0);
}
void board_putchar(int c) {
stdio_putchar(c);
}
//--------------------------------------------------------------------+
// USB Interrupt Handler
// rp2040 implementation will install appropriate handler when initializing

18
hw/bsp/rp2040/family.mk
View File

@@ -1,18 +0,0 @@
JLINK_DEVICE = rp2040_m0_0
PYOCD_TARGET = rp2040
DEPS_SUBMODULES += hw/mcu/raspberry_pi/Pico-PIO-USB
ifeq ($(DEBUG), 1)
CMAKE_DEFSYM += -DCMAKE_BUILD_TYPE=Debug
endif
$(BUILD):
cmake -S . -B $(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) -DPICO_BUILD_DOCS=0 $(CMAKE_DEFSYM)
all: $(BUILD)
$(MAKE) -C $(BUILD)
flash: flash-pyocd
flash-uf2:
@$(CP) $(BUILD)/$(PROJECT).uf2 /media/$(USER)/RPI-RP2

2
hw/bsp/rx/family.mk
View File

@@ -1,5 +1,3 @@
DEPS_SUBMODULES += hw/mcu/renesas/rx
# Cross Compiler for RX
CROSS_COMPILE = rx-elf-

1
hw/bsp/same70_qmtech/board.mk
View File

@@ -1,4 +1,3 @@
DEPS_SUBMODULES += hw/mcu/microchip
ASF_DIR = hw/mcu/microchip/same70
CFLAGS += \

1
hw/bsp/same70_xplained/board.mk
View File

@@ -1,4 +1,3 @@
DEPS_SUBMODULES += hw/mcu/microchip
ASF_DIR = hw/mcu/microchip/same70
CFLAGS += \

3
hw/bsp/sltb009a/board.mk
View File

@@ -16,9 +16,6 @@ CFLAGS += \
SILABS_FAMILY = efm32gg12b
SILABS_CMSIS = hw/mcu/silabs/cmsis-dfp-$(SILABS_FAMILY)/Device/SiliconLabs/$(shell echo $(SILABS_FAMILY) | tr a-z A-Z)
DEPS_SUBMODULES += hw/mcu/silabs/cmsis-dfp-$(SILABS_FAMILY)
DEPS_SUBMODULES += lib/CMSIS_5
LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
# All source paths should be relative to the top level.

2
hw/bsp/spresense/board.mk
View File

@@ -1,5 +1,3 @@
DEPS_SUBMODULES += hw/mcu/sony/cxd56/spresense-exported-sdk
# Platforms are: Linux, Darwin, MSYS, CYGWIN
PLATFORM := $(firstword $(subst _, ,$(shell uname -s 2>/dev/null)))

2
hw/bsp/stm32c0/family.mk
View File

@@ -1,6 +1,4 @@
ST_FAMILY = c0
DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver

2
hw/bsp/stm32f0/family.mk
View File

@@ -1,7 +1,5 @@
UF2_FAMILY_ID = 0x647824b6
ST_FAMILY = f0
DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver

2
hw/bsp/stm32f1/family.mk
View File

@@ -1,6 +1,4 @@
ST_FAMILY = f1
DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_${ST_FAMILY} hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver
ST_CMSIS = hw/mcu/st/cmsis_device_${ST_FAMILY}
ST_HAL_DRIVER = hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver

5
hw/bsp/stm32f2/family.mk
View File

@@ -2,11 +2,6 @@ ST_FAMILY = f2
ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
DEPS_SUBMODULES += \
lib/CMSIS_5 \
$(ST_CMSIS) \
$(ST_HAL_DRIVER)
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m3

1
hw/bsp/stm32f7/family.mk
View File

@@ -1,6 +1,5 @@
UF2_FAMILY_ID = 0x53b80f00
ST_FAMILY = f7
DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver

1
hw/bsp/stm32g0/family.mk
View File

@@ -1,5 +1,4 @@
ST_FAMILY = g0
DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver

1
hw/bsp/stm32l4/family.mk
View File

@@ -1,5 +1,4 @@
ST_FAMILY = l4
DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver

1
hw/bsp/stm32u5/family.mk
View File

@@ -1,5 +1,4 @@
ST_FAMILY = u5
DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver

2
hw/bsp/xmc4000/family.mk
View File

@@ -1,8 +1,6 @@
UF2_FAMILY_ID = 0x00
SDK_DIR = hw/mcu/infineon/mtb-xmclib-cat3
DEPS_SUBMODULES += ${SDK_DIR}
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m4