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Merge pull request #2963 from HiFiPhile/stm32_cache

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Add DWC2 cache maintenance routines for STM32
This commit is contained in:
Ha Thach
2025-07-07 22:02:30 +07:00
committed by GitHub
parent a2ee6da299 3eb0451879
commit 9990e4bf0c
14 changed files with 269 additions and 84 deletions
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8
src/class/audio/audio_device.c
View File

@@ -109,14 +109,14 @@
// Put swap buffer in USB section only if necessary
#if USE_LINEAR_BUFFER
#define IN_SW_BUF_MEM_ATTR TU_ATTR_ALIGNED(4)
#define IN_SW_BUF_MEM_ATTR
#else
#define IN_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN
#define IN_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION
#endif
#if USE_LINEAR_BUFFER
#define OUT_SW_BUF_MEM_ATTR TU_ATTR_ALIGNED(4)
#define OUT_SW_BUF_MEM_ATTR
#else
#define OUT_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN
#define OUT_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION
#endif
// EP IN software buffers and mutexes

28
src/common/tusb_mcu.h
View File

@@ -117,9 +117,9 @@
#define TUP_RHPORT_HIGHSPEED 1
#if __CORTEX_M == 7
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
#endif
#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K)
@@ -220,12 +220,25 @@
#define TUP_RHPORT_HIGHSPEED 1 // Port0: FS, Port1: HS
#endif
// Enable dcache if DMA is enabled
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
#elif TU_CHECK_MCU(OPT_MCU_STM32H7)
#include "stm32h7xx.h"
#define TUP_USBIP_DWC2
#define TUP_USBIP_DWC2_STM32
#define TUP_DCD_ENDPOINT_MAX 9
#if __CORTEX_M == 7
// Enable dcache if DMA is enabled
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
#endif
#elif TU_CHECK_MCU(OPT_MCU_STM32H5)
#define TUP_USBIP_FSDEV
#define TUP_USBIP_FSDEV_STM32
@@ -322,6 +335,11 @@
// MCU with on-chip HS Phy
#define TUP_RHPORT_HIGHSPEED 1
// Enable dcache if DMA is enabled
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
//--------------------------------------------------------------------+
// Sony
//--------------------------------------------------------------------+
@@ -392,8 +410,8 @@
#define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUH_DWC2_DMA_ENABLE
// Enable dcache if DMA is enabled
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 64
#elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2)

8
src/common/tusb_types.h
View File

@@ -43,14 +43,14 @@
#define TUD_EPBUF_DEF(_name, _size) \
union { \
CFG_TUD_MEM_ALIGN uint8_t _name[_size]; \
uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(_size)]; \
TU_ATTR_ALIGNED(CFG_TUD_MEM_DCACHE_ENABLE ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(_size)]; \
}
// Declare an endpoint buffer with a type
#define TUD_EPBUF_TYPE_DEF(_type, _name) \
union { \
CFG_TUD_MEM_ALIGN _type _name; \
uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
TU_ATTR_ALIGNED(CFG_TUD_MEM_DCACHE_ENABLE ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
}
//------------- Host DCache declaration -------------//
@@ -61,14 +61,14 @@
#define TUH_EPBUF_DEF(_name, _size) \
union { \
CFG_TUH_MEM_ALIGN uint8_t _name[_size]; \
uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(_size)]; \
TU_ATTR_ALIGNED(CFG_TUH_MEM_DCACHE_ENABLE ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(_size)]; \
}
// Declare an endpoint buffer with a type
#define TUH_EPBUF_TYPE_DEF(_type, _name) \
union { \
CFG_TUH_MEM_ALIGN _type _name; \
uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
TU_ATTR_ALIGNED(CFG_TUH_MEM_DCACHE_ENABLE ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
}

71
src/portable/synopsys/dwc2/dwc2_stm32.h
View File

@@ -279,6 +279,77 @@ static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
}
}
//------------- DCache -------------//
#if CFG_TUD_MEM_DCACHE_ENABLE || CFG_TUH_MEM_DCACHE_ENABLE
typedef struct {
uintptr_t start;
uintptr_t end;
} mem_region_t;
// Can be used to define additional uncached regions
#ifndef CFG_DWC2_MEM_UNCACHED_REGIONS
#define CFG_DWC2_MEM_UNCACHED_REGIONS
#endif
static mem_region_t uncached_regions[] = {
// DTCM (although USB DMA can't transfer to/from DTCM)
#if CFG_TUSB_MCU == OPT_MCU_STM32H7
{.start = 0x20000000, .end = 0x2001FFFF},
#elif CFG_TUSB_MCU == OPT_MCU_STM32H7RS
// DTCM (although USB DMA can't transfer to/from DTCM)
{.start = 0x20000000, .end = 0x2002FFFF},
#elif CFG_TUSB_MCU == OPT_MCU_STM32F7
// DTCM
{.start = 0x20000000, .end = 0x2000FFFF},
#else
#error "Cache maintenance is not supported yet"
#endif
CFG_DWC2_MEM_UNCACHED_REGIONS
};
TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_t size) {
if (size & (CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT-1)) {
size = (size & ~(CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT-1)) + CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT;
}
return size;
}
TU_ATTR_ALWAYS_INLINE static inline bool is_cache_mem(uintptr_t addr) {
for (unsigned int i = 0; i < TU_ARRAY_SIZE(uncached_regions); i++) {
if (uncached_regions[i].start <= addr && addr <= uncached_regions[i].end) { return false; }
}
return true;
}
TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_clean(void const* addr, uint32_t data_size) {
const uintptr_t addr32 = (uintptr_t) addr;
if (is_cache_mem(addr32)) {
data_size = round_up_to_cache_line_size(data_size);
SCB_CleanDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size);
}
return true;
}
TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_invalidate(void const* addr, uint32_t data_size) {
const uintptr_t addr32 = (uintptr_t) addr;
if (is_cache_mem(addr32)) {
data_size = round_up_to_cache_line_size(data_size);
SCB_InvalidateDCache_by_Addr((void*) addr32, (int32_t) data_size);
}
return true;
}
TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
const uintptr_t addr32 = (uintptr_t) addr;
if (is_cache_mem(addr32)) {
data_size = round_up_to_cache_line_size(data_size);
SCB_CleanInvalidateDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size);
}
return true;
}
#endif
#ifdef __cplusplus
}
#endif

4
src/tusb_option.h
View File

@@ -420,7 +420,7 @@
#ifndef CFG_TUSB_MEM_DCACHE_LINE_SIZE
#ifndef CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 1
#endif
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT
@@ -428,7 +428,7 @@
// OS selection
#ifndef CFG_TUSB_OS
#define CFG_TUSB_OS OPT_OS_NONE
#define CFG_TUSB_OS OPT_OS_NONE
#endif
#ifndef CFG_TUSB_OS_INC_PATH