Merge pull request #2963 from HiFiPhile/stm32_cache
Add DWC2 cache maintenance routines for STM32
This commit is contained in:
@@ -78,6 +78,10 @@ void OTG_HS_IRQHandler(void) {
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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void board_init(void) {
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void board_init(void) {
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SCB_EnableICache();
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HAL_Init();
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board_clock_init();
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board_clock_init();
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// Enable All GPIOs clocks
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// Enable All GPIOs clocks
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@@ -98,6 +98,10 @@ static void trace_etm_init(void) {
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#endif
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#endif
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void board_init(void) {
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void board_init(void) {
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SCB_EnableICache();
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HAL_Init();
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// Implemented in board.h
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// Implemented in board.h
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SystemClock_Config();
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SystemClock_Config();
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@@ -1,9 +1,7 @@
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set(MCU_VARIANT stm32h7s3xx)
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set(MCU_VARIANT stm32h7s3xx)
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set(JLINK_DEVICE stm32h7s3xx)
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set(JLINK_DEVICE stm32h7s3xx)
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set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/stm32h7s3xx_flash.ld)
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set(LD_FILE_Clang ${LD_FILE_GNU})
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set(LD_FILE_Clang ${LD_FILE_GNU})
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set(LD_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/stm32h7s3xx_flash.icf)
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function(update_board TARGET)
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function(update_board TARGET)
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target_compile_definitions(${TARGET} PUBLIC
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target_compile_definitions(${TARGET} PUBLIC
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@@ -7,10 +7,6 @@ JLINK_DEVICE = stm32h7s3xx
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# flash target using on-board stlink
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# flash target using on-board stlink
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flash: flash-stlink
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flash: flash-stlink
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# Linker
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LD_FILE_GCC = $(BOARD_PATH)/stm32h7s3xx_flash.ld
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LD_FILE_IAR = $(BOARD_PATH)/stm32h7s3xx_flash.icf
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SRC_C += \
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SRC_C += \
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$(ST_TCPP0203)/tcpp0203.c \
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$(ST_TCPP0203)/tcpp0203.c \
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$(ST_TCPP0203)/tcpp0203_reg.c \
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$(ST_TCPP0203)/tcpp0203_reg.c \
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@@ -1,55 +0,0 @@
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/*###ICF### Section handled by ICF editor, don't touch! ****/
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/*-Editor annotation file-*/
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/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
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/*-Specials-*/
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define symbol __ICFEDIT_intvec_start__ = 0x08000000;
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/*-Memory Regions-*/
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define symbol NONCACHEABLEBUFFER_size = 0x4000;
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define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
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define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF;
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define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
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define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF - NONCACHEABLEBUFFER_size;
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define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1;
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define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
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/*-Sizes-*/
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define symbol __ICFEDIT_size_cstack__ = 0x800;
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define symbol __ICFEDIT_size_heap__ = 0x200;
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/**** End of ICF editor section. ###ICF###*/
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define symbol __region_ITCM_start__ = 0x00000000;
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define symbol __region_ITCM_end__ = 0x0000FFFF;
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define symbol __region_DTCM_start__ = 0x20000000;
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define symbol __region_DTCM_end__ = 0x2000FFFF;
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define symbol __region_SRAMAHB_start__ = 0x30000000;
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define symbol __region_SRAMAHB_end__ = 0x30007FFF;
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define symbol __region_BKPSRAM_start__ = 0x38800000;
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define symbol __region_BKPSRAM_end__ = 0x38800FFF;
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export symbol NONCACHEABLEBUFFER_start;
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export symbol NONCACHEABLEBUFFER_size;
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export symbol __ICFEDIT_region_ROM_start__;
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export symbol __ICFEDIT_region_ROM_end__;
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define memory mem with size = 4G;
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define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
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define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
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define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
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define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
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define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
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define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
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define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
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define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
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define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
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initialize by copy { readwrite };
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do not initialize { section .noinit };
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place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
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place in ROM_region { readonly };
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place in RAM_region { readwrite };
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place in NONCACHEABLE_region { section noncacheable_buffer };
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place in DTCM_region { block CSTACK, block HEAP };
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@@ -123,10 +123,159 @@ void log_swo_init(void)
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#define log_swo_init()
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#define log_swo_init()
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#endif
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#endif
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static void MPU_AdjustRegionAddressSize(uint32_t Address, uint32_t Size, MPU_Region_InitTypeDef* pInit);
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static void MPU_Config(void)
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{
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MPU_Region_InitTypeDef MPU_InitStruct = {0};
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uint32_t index = MPU_REGION_NUMBER0;
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uint32_t address;
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uint32_t size;
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/* Disable the MPU */
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HAL_MPU_Disable();
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/* Initialize the background region */
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MPU_InitStruct.Enable = MPU_REGION_ENABLE;
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MPU_InitStruct.Number = index;
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MPU_InitStruct.BaseAddress = 0x0;
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MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
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MPU_InitStruct.SubRegionDisable = 0x87;
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MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
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MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
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MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
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MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
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MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
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MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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index++;
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/* Initialize the non cacheable region */
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#if defined ( __ICCARM__ )
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/* get the region attribute form the icf file */
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extern uint32_t NONCACHEABLEBUFFER_start;
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extern uint32_t NONCACHEABLEBUFFER_size;
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address = (uint32_t)&NONCACHEABLEBUFFER_start;
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size = (uint32_t)&NONCACHEABLEBUFFER_size;
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#elif defined (__CC_ARM) || defined(__ARMCC_VERSION)
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extern uint32_t Image$$RW_NONCACHEABLEBUFFER$$Base;
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extern uint32_t Image$$RW_NONCACHEABLEBUFFER$$Length;
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extern uint32_t Image$$RW_NONCACHEABLEBUFFER$$ZI$$Length;
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address = (uint32_t)&Image$$RW_NONCACHEABLEBUFFER$$Base;
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size = (uint32_t)&Image$$RW_NONCACHEABLEBUFFER$$Length + (uint32_t)&Image$$RW_NONCACHEABLEBUFFER$$ZI$$Length;
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#elif defined ( __GNUC__ )
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extern int __NONCACHEABLEBUFFER_BEGIN;
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extern int __NONCACHEABLEBUFFER_END;
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address = (uint32_t)&__NONCACHEABLEBUFFER_BEGIN;
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size = (uint32_t)&__NONCACHEABLEBUFFER_END - (uint32_t)&__NONCACHEABLEBUFFER_BEGIN;
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#else
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#error "Compiler toolchain is unsupported"
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#endif
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if (size != 0)
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{
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/* Configure the MPU attributes as Normal Non Cacheable */
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MPU_InitStruct.Enable = MPU_REGION_ENABLE;
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MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
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MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
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MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
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MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
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MPU_InitStruct.Number = index;
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MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
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MPU_InitStruct.SubRegionDisable = 0x00;
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MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
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MPU_AdjustRegionAddressSize(address, size, &MPU_InitStruct);
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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index++;
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}
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/* Initialize the region corresponding to the execution area
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(external or internal flash or external or internal RAM
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depending on scatter file definition) */
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#if defined ( __ICCARM__ )
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extern uint32_t __ICFEDIT_region_ROM_start__;
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extern uint32_t __ICFEDIT_region_ROM_end__;
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address = (uint32_t)&__ICFEDIT_region_ROM_start__;
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size = (uint32_t)&__ICFEDIT_region_ROM_end__ - (uint32_t)&__ICFEDIT_region_ROM_start__ + 1;
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#elif defined (__CC_ARM) || defined(__ARMCC_VERSION)
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extern uint32_t Image$$ER_ROM$$Base;
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extern uint32_t Image$$ER_ROM$$Limit;
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address = (uint32_t)&Image$$ER_ROM$$Base;
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size = (uint32_t)&Image$$ER_ROM$$Limit-(uint32_t)&Image$$ER_ROM$$Base;
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#elif defined ( __GNUC__ )
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extern uint32_t __FLASH_BEGIN;
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extern uint32_t __FLASH_SIZE;
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address = (uint32_t)&__FLASH_BEGIN;
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size = (uint32_t)&__FLASH_SIZE;
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#else
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#error "Compiler toolchain is unsupported"
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#endif
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MPU_InitStruct.Enable = MPU_REGION_ENABLE;
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MPU_InitStruct.Number = index;
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MPU_InitStruct.SubRegionDisable = 0u;
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MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
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MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
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MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
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MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
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MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
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MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
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MPU_AdjustRegionAddressSize(address, size, &MPU_InitStruct);
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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index++;
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/* Reset unused MPU regions */
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for(; index < __MPU_REGIONCOUNT ; index++)
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{
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/* All unused regions disabled */
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MPU_InitStruct.Enable = MPU_REGION_DISABLE;
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MPU_InitStruct.Number = index;
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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}
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/* Enable the MPU */
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HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
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}
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/**
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* @brief This function adjusts the MPU region Address and Size within an MPU configuration.
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* @param Address memory address
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* @param Size memory size
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* @param pInit pointer to an MPU initialization structure
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* @retval None
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*/
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static void MPU_AdjustRegionAddressSize(uint32_t Address, uint32_t Size, MPU_Region_InitTypeDef* pInit)
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{
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/* Compute the MPU region size */
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pInit->Size = ((31 - __CLZ(Size)) - 1);
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if (Size > (1u << (pInit->Size + 1)))
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{
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pInit->Size++;
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}
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uint32_t Modulo = Address % (1 << (pInit->Size - 1));
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if (0 != Modulo)
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{
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/* Align address with MPU region size considering there is no need to increase the size */
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pInit->BaseAddress = Address - Modulo;
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}
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else
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{
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pInit->BaseAddress = Address;
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}
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}
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void board_init(void) {
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void board_init(void) {
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HAL_Init();
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HAL_Init();
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MPU_Config();
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SCB_EnableICache();
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SCB_EnableDCache();
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HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
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HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
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// Implemented in board.h
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// Implemented in board.h
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SystemClock_Config();
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SystemClock_Config();
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@@ -54,7 +54,7 @@ function(add_board_target BOARD_TARGET)
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set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
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set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
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if(NOT DEFINED LD_FILE_GNU)
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if(NOT DEFINED LD_FILE_GNU)
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set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash.ld)
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set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${MCU_VARIANT}_flash.ld)
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endif()
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endif()
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set(LD_FILE_Clang ${LD_FILE_GNU})
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set(LD_FILE_Clang ${LD_FILE_GNU})
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if(NOT DEFINED LD_FILE_IAR)
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if(NOT DEFINED LD_FILE_IAR)
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@@ -87,8 +87,8 @@ function(add_board_target BOARD_TARGET)
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BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
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BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
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BOARD_TUH_RHPORT=${RHPORT_HOST}
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BOARD_TUH_RHPORT=${RHPORT_HOST}
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BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
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BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
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SEGGER_RTT_SECTION="noncacheable_buffer"
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SEGGER_RTT_SECTION=\"noncacheable_buffer\"
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BUFFER_SIZE_UP=0x3000
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BUFFER_SIZE_UP=0x300
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)
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)
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update_board(${BOARD_TARGET})
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update_board(${BOARD_TARGET})
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@@ -43,8 +43,8 @@ CFLAGS += \
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-DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \
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-DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \
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-DBOARD_TUH_RHPORT=${RHPORT_HOST} \
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-DBOARD_TUH_RHPORT=${RHPORT_HOST} \
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-DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \
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-DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \
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-DSEGGER_RTT_SECTION=\"noncacheable_buffer\" \
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-DSEGGER_RTT_SECTION="noncacheable_buffer" \
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-DBUFFER_SIZE_UP=0x3000 \
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-DBUFFER_SIZE_UP=0x300 \
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# GCC Flags
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# GCC Flags
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CFLAGS_GCC += \
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CFLAGS_GCC += \
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@@ -91,5 +91,5 @@ SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s
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SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
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SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
|
||||||
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# Linker
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# Linker
|
||||||
LD_FILE_GCC ?= $(ST_CMSIS)/Source/Templates/gcc/linker/$(MCU_VARIANT)_flash.ld
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LD_FILE_GCC ?= $(FAMILY_PATH)/linker/$(MCU_VARIANT)_flash.ld
|
||||||
LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf
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LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf
|
||||||
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@@ -43,7 +43,7 @@ __FLASH_SIZE = 0x00010000;
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|||||||
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|
||||||
__RAM_BEGIN = 0x24000000;
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__RAM_BEGIN = 0x24000000;
|
||||||
__RAM_SIZE = 0x4FC00;
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__RAM_SIZE = 0x4FC00;
|
||||||
__RAM_NONCACHEABLEBUFFER_SIZE = 0x4000;
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__RAM_NONCACHEABLEBUFFER_SIZE = 0x400;
|
||||||
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|
||||||
/* Memories definition */
|
/* Memories definition */
|
||||||
MEMORY
|
MEMORY
|
||||||
@@ -182,7 +182,7 @@ SECTIONS
|
|||||||
{
|
{
|
||||||
__NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */
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__NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */
|
||||||
KEEP(*(noncacheable_buffer))
|
KEEP(*(noncacheable_buffer))
|
||||||
__NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */
|
__NONCACHEABLEBUFFER_END = .; /* create symbol for end of section */
|
||||||
} > RAM_NONCACHEABLEBUFFER
|
} > RAM_NONCACHEABLEBUFFER
|
||||||
|
|
||||||
/* User_heap_stack section, used to check that there is enough "DTCM" Ram type memory left */
|
/* User_heap_stack section, used to check that there is enough "DTCM" Ram type memory left */
|
@@ -109,14 +109,14 @@
|
|||||||
|
|
||||||
// Put swap buffer in USB section only if necessary
|
// Put swap buffer in USB section only if necessary
|
||||||
#if USE_LINEAR_BUFFER
|
#if USE_LINEAR_BUFFER
|
||||||
#define IN_SW_BUF_MEM_ATTR TU_ATTR_ALIGNED(4)
|
#define IN_SW_BUF_MEM_ATTR
|
||||||
#else
|
#else
|
||||||
#define IN_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN
|
#define IN_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION
|
||||||
#endif
|
#endif
|
||||||
#if USE_LINEAR_BUFFER
|
#if USE_LINEAR_BUFFER
|
||||||
#define OUT_SW_BUF_MEM_ATTR TU_ATTR_ALIGNED(4)
|
#define OUT_SW_BUF_MEM_ATTR
|
||||||
#else
|
#else
|
||||||
#define OUT_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN
|
#define OUT_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
// EP IN software buffers and mutexes
|
// EP IN software buffers and mutexes
|
||||||
|
@@ -117,9 +117,9 @@
|
|||||||
#define TUP_RHPORT_HIGHSPEED 1
|
#define TUP_RHPORT_HIGHSPEED 1
|
||||||
|
|
||||||
#if __CORTEX_M == 7
|
#if __CORTEX_M == 7
|
||||||
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1
|
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1
|
||||||
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1
|
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1
|
||||||
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32
|
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K)
|
#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K)
|
||||||
@@ -220,12 +220,25 @@
|
|||||||
#define TUP_RHPORT_HIGHSPEED 1 // Port0: FS, Port1: HS
|
#define TUP_RHPORT_HIGHSPEED 1 // Port0: FS, Port1: HS
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
// Enable dcache if DMA is enabled
|
||||||
|
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE
|
||||||
|
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE
|
||||||
|
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
|
||||||
|
|
||||||
#elif TU_CHECK_MCU(OPT_MCU_STM32H7)
|
#elif TU_CHECK_MCU(OPT_MCU_STM32H7)
|
||||||
|
#include "stm32h7xx.h"
|
||||||
#define TUP_USBIP_DWC2
|
#define TUP_USBIP_DWC2
|
||||||
#define TUP_USBIP_DWC2_STM32
|
#define TUP_USBIP_DWC2_STM32
|
||||||
|
|
||||||
#define TUP_DCD_ENDPOINT_MAX 9
|
#define TUP_DCD_ENDPOINT_MAX 9
|
||||||
|
|
||||||
|
#if __CORTEX_M == 7
|
||||||
|
// Enable dcache if DMA is enabled
|
||||||
|
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE
|
||||||
|
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE
|
||||||
|
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
|
||||||
|
#endif
|
||||||
|
|
||||||
#elif TU_CHECK_MCU(OPT_MCU_STM32H5)
|
#elif TU_CHECK_MCU(OPT_MCU_STM32H5)
|
||||||
#define TUP_USBIP_FSDEV
|
#define TUP_USBIP_FSDEV
|
||||||
#define TUP_USBIP_FSDEV_STM32
|
#define TUP_USBIP_FSDEV_STM32
|
||||||
@@ -322,6 +335,11 @@
|
|||||||
// MCU with on-chip HS Phy
|
// MCU with on-chip HS Phy
|
||||||
#define TUP_RHPORT_HIGHSPEED 1
|
#define TUP_RHPORT_HIGHSPEED 1
|
||||||
|
|
||||||
|
// Enable dcache if DMA is enabled
|
||||||
|
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE
|
||||||
|
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE
|
||||||
|
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
// Sony
|
// Sony
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
@@ -392,8 +410,8 @@
|
|||||||
#define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUH_DWC2_DMA_ENABLE
|
#define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUH_DWC2_DMA_ENABLE
|
||||||
|
|
||||||
// Enable dcache if DMA is enabled
|
// Enable dcache if DMA is enabled
|
||||||
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE
|
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE
|
||||||
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE
|
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE
|
||||||
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 64
|
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 64
|
||||||
|
|
||||||
#elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2)
|
#elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2)
|
||||||
|
@@ -43,14 +43,14 @@
|
|||||||
#define TUD_EPBUF_DEF(_name, _size) \
|
#define TUD_EPBUF_DEF(_name, _size) \
|
||||||
union { \
|
union { \
|
||||||
CFG_TUD_MEM_ALIGN uint8_t _name[_size]; \
|
CFG_TUD_MEM_ALIGN uint8_t _name[_size]; \
|
||||||
uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(_size)]; \
|
TU_ATTR_ALIGNED(CFG_TUD_MEM_DCACHE_ENABLE ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(_size)]; \
|
||||||
}
|
}
|
||||||
|
|
||||||
// Declare an endpoint buffer with a type
|
// Declare an endpoint buffer with a type
|
||||||
#define TUD_EPBUF_TYPE_DEF(_type, _name) \
|
#define TUD_EPBUF_TYPE_DEF(_type, _name) \
|
||||||
union { \
|
union { \
|
||||||
CFG_TUD_MEM_ALIGN _type _name; \
|
CFG_TUD_MEM_ALIGN _type _name; \
|
||||||
uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
|
TU_ATTR_ALIGNED(CFG_TUD_MEM_DCACHE_ENABLE ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
|
||||||
}
|
}
|
||||||
|
|
||||||
//------------- Host DCache declaration -------------//
|
//------------- Host DCache declaration -------------//
|
||||||
@@ -61,14 +61,14 @@
|
|||||||
#define TUH_EPBUF_DEF(_name, _size) \
|
#define TUH_EPBUF_DEF(_name, _size) \
|
||||||
union { \
|
union { \
|
||||||
CFG_TUH_MEM_ALIGN uint8_t _name[_size]; \
|
CFG_TUH_MEM_ALIGN uint8_t _name[_size]; \
|
||||||
uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(_size)]; \
|
TU_ATTR_ALIGNED(CFG_TUH_MEM_DCACHE_ENABLE ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(_size)]; \
|
||||||
}
|
}
|
||||||
|
|
||||||
// Declare an endpoint buffer with a type
|
// Declare an endpoint buffer with a type
|
||||||
#define TUH_EPBUF_TYPE_DEF(_type, _name) \
|
#define TUH_EPBUF_TYPE_DEF(_type, _name) \
|
||||||
union { \
|
union { \
|
||||||
CFG_TUH_MEM_ALIGN _type _name; \
|
CFG_TUH_MEM_ALIGN _type _name; \
|
||||||
uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
|
TU_ATTR_ALIGNED(CFG_TUH_MEM_DCACHE_ENABLE ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
@@ -279,6 +279,77 @@ static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
//------------- DCache -------------//
|
||||||
|
#if CFG_TUD_MEM_DCACHE_ENABLE || CFG_TUH_MEM_DCACHE_ENABLE
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
uintptr_t start;
|
||||||
|
uintptr_t end;
|
||||||
|
} mem_region_t;
|
||||||
|
|
||||||
|
// Can be used to define additional uncached regions
|
||||||
|
#ifndef CFG_DWC2_MEM_UNCACHED_REGIONS
|
||||||
|
#define CFG_DWC2_MEM_UNCACHED_REGIONS
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static mem_region_t uncached_regions[] = {
|
||||||
|
// DTCM (although USB DMA can't transfer to/from DTCM)
|
||||||
|
#if CFG_TUSB_MCU == OPT_MCU_STM32H7
|
||||||
|
{.start = 0x20000000, .end = 0x2001FFFF},
|
||||||
|
#elif CFG_TUSB_MCU == OPT_MCU_STM32H7RS
|
||||||
|
// DTCM (although USB DMA can't transfer to/from DTCM)
|
||||||
|
{.start = 0x20000000, .end = 0x2002FFFF},
|
||||||
|
#elif CFG_TUSB_MCU == OPT_MCU_STM32F7
|
||||||
|
// DTCM
|
||||||
|
{.start = 0x20000000, .end = 0x2000FFFF},
|
||||||
|
#else
|
||||||
|
#error "Cache maintenance is not supported yet"
|
||||||
|
#endif
|
||||||
|
CFG_DWC2_MEM_UNCACHED_REGIONS
|
||||||
|
};
|
||||||
|
|
||||||
|
TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_t size) {
|
||||||
|
if (size & (CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT-1)) {
|
||||||
|
size = (size & ~(CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT-1)) + CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT;
|
||||||
|
}
|
||||||
|
return size;
|
||||||
|
}
|
||||||
|
|
||||||
|
TU_ATTR_ALWAYS_INLINE static inline bool is_cache_mem(uintptr_t addr) {
|
||||||
|
for (unsigned int i = 0; i < TU_ARRAY_SIZE(uncached_regions); i++) {
|
||||||
|
if (uncached_regions[i].start <= addr && addr <= uncached_regions[i].end) { return false; }
|
||||||
|
}
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_clean(void const* addr, uint32_t data_size) {
|
||||||
|
const uintptr_t addr32 = (uintptr_t) addr;
|
||||||
|
if (is_cache_mem(addr32)) {
|
||||||
|
data_size = round_up_to_cache_line_size(data_size);
|
||||||
|
SCB_CleanDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size);
|
||||||
|
}
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_invalidate(void const* addr, uint32_t data_size) {
|
||||||
|
const uintptr_t addr32 = (uintptr_t) addr;
|
||||||
|
if (is_cache_mem(addr32)) {
|
||||||
|
data_size = round_up_to_cache_line_size(data_size);
|
||||||
|
SCB_InvalidateDCache_by_Addr((void*) addr32, (int32_t) data_size);
|
||||||
|
}
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
|
||||||
|
const uintptr_t addr32 = (uintptr_t) addr;
|
||||||
|
if (is_cache_mem(addr32)) {
|
||||||
|
data_size = round_up_to_cache_line_size(data_size);
|
||||||
|
SCB_CleanInvalidateDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size);
|
||||||
|
}
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
@@ -420,7 +420,7 @@
|
|||||||
|
|
||||||
#ifndef CFG_TUSB_MEM_DCACHE_LINE_SIZE
|
#ifndef CFG_TUSB_MEM_DCACHE_LINE_SIZE
|
||||||
#ifndef CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT
|
#ifndef CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT
|
||||||
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
|
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 1
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT
|
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT
|
||||||
@@ -428,7 +428,7 @@
|
|||||||
|
|
||||||
// OS selection
|
// OS selection
|
||||||
#ifndef CFG_TUSB_OS
|
#ifndef CFG_TUSB_OS
|
||||||
#define CFG_TUSB_OS OPT_OS_NONE
|
#define CFG_TUSB_OS OPT_OS_NONE
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifndef CFG_TUSB_OS_INC_PATH
|
#ifndef CFG_TUSB_OS_INC_PATH
|
||||||
|
Reference in New Issue
Block a user