andy/tinyUSB
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Merge pull request #2963 from HiFiPhile/stm32_cache

Browse Source 
Add DWC2 cache maintenance routines for STM32
This commit is contained in:
Ha Thach
2025-07-07 22:02:30 +07:00
committed by GitHub
parent a2ee6da299 3eb0451879
commit 9990e4bf0c
14 changed files with 269 additions and 84 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
hw/bsp/stm32f7/family.c
View File

@@ -78,6 +78,10 @@ void OTG_HS_IRQHandler(void) {
//--------------------------------------------------------------------+
void board_init(void) {
SCB_EnableICache();
HAL_Init();
board_clock_init();
// Enable All GPIOs clocks

4
hw/bsp/stm32h7/family.c
View File

@@ -98,6 +98,10 @@ static void trace_etm_init(void) {
#endif
void board_init(void) {
SCB_EnableICache();
HAL_Init();
// Implemented in board.h
SystemClock_Config();

2
hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake
View File

@@ -1,9 +1,7 @@
set(MCU_VARIANT stm32h7s3xx)
set(JLINK_DEVICE stm32h7s3xx)
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/stm32h7s3xx_flash.ld)
set(LD_FILE_Clang ${LD_FILE_GNU})
set(LD_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/stm32h7s3xx_flash.icf)
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC

4
hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.mk
View File

@@ -7,10 +7,6 @@ JLINK_DEVICE = stm32h7s3xx
# flash target using on-board stlink
flash: flash-stlink
# Linker
LD_FILE_GCC = $(BOARD_PATH)/stm32h7s3xx_flash.ld
LD_FILE_IAR = $(BOARD_PATH)/stm32h7s3xx_flash.icf
SRC_C += \
$(ST_TCPP0203)/tcpp0203.c \
$(ST_TCPP0203)/tcpp0203_reg.c \

55
hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/stm32h7s3xx_flash.icf
View File

@@ -1,55 +0,0 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol NONCACHEABLEBUFFER_size = 0x4000;
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF - NONCACHEABLEBUFFER_size;
define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1;
define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x800;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define symbol __region_ITCM_start__ = 0x00000000;
define symbol __region_ITCM_end__ = 0x0000FFFF;
define symbol __region_DTCM_start__ = 0x20000000;
define symbol __region_DTCM_end__ = 0x2000FFFF;
define symbol __region_SRAMAHB_start__ = 0x30000000;
define symbol __region_SRAMAHB_end__ = 0x30007FFF;
define symbol __region_BKPSRAM_start__ = 0x38800000;
define symbol __region_BKPSRAM_end__ = 0x38800FFF;
export symbol NONCACHEABLEBUFFER_start;
export symbol NONCACHEABLEBUFFER_size;
export symbol __ICFEDIT_region_ROM_start__;
export symbol __ICFEDIT_region_ROM_end__;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite };
place in NONCACHEABLE_region { section noncacheable_buffer };
place in DTCM_region { block CSTACK, block HEAP };

149
hw/bsp/stm32h7rs/family.c
View File

@@ -123,10 +123,159 @@ void log_swo_init(void)
#define log_swo_init()
#endif
static void MPU_AdjustRegionAddressSize(uint32_t Address, uint32_t Size, MPU_Region_InitTypeDef* pInit);
static void MPU_Config(void)
{
MPU_Region_InitTypeDef MPU_InitStruct = {0};
uint32_t index = MPU_REGION_NUMBER0;
uint32_t address;
uint32_t size;
/* Disable the MPU */
HAL_MPU_Disable();
/* Initialize the background region */
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.Number = index;
MPU_InitStruct.BaseAddress = 0x0;
MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
MPU_InitStruct.SubRegionDisable = 0x87;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
index++;
/* Initialize the non cacheable region */
#if defined ( __ICCARM__ )
/* get the region attribute form the icf file */
extern uint32_t NONCACHEABLEBUFFER_start;
extern uint32_t NONCACHEABLEBUFFER_size;
address = (uint32_t)&NONCACHEABLEBUFFER_start;
size = (uint32_t)&NONCACHEABLEBUFFER_size;
#elif defined (__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$RW_NONCACHEABLEBUFFER$$Base;
extern uint32_t Image$$RW_NONCACHEABLEBUFFER$$Length;
extern uint32_t Image$$RW_NONCACHEABLEBUFFER$$ZI$$Length;
address = (uint32_t)&Image$$RW_NONCACHEABLEBUFFER$$Base;
size = (uint32_t)&Image$$RW_NONCACHEABLEBUFFER$$Length + (uint32_t)&Image$$RW_NONCACHEABLEBUFFER$$ZI$$Length;
#elif defined ( __GNUC__ )
extern int __NONCACHEABLEBUFFER_BEGIN;
extern int __NONCACHEABLEBUFFER_END;
address = (uint32_t)&__NONCACHEABLEBUFFER_BEGIN;
size = (uint32_t)&__NONCACHEABLEBUFFER_END - (uint32_t)&__NONCACHEABLEBUFFER_BEGIN;
#else
#error "Compiler toolchain is unsupported"
#endif
if (size != 0)
{
/* Configure the MPU attributes as Normal Non Cacheable */
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
MPU_InitStruct.Number = index;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
MPU_InitStruct.SubRegionDisable = 0x00;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
MPU_AdjustRegionAddressSize(address, size, &MPU_InitStruct);
HAL_MPU_ConfigRegion(&MPU_InitStruct);
index++;
}
/* Initialize the region corresponding to the execution area
(external or internal flash or external or internal RAM
depending on scatter file definition) */
#if defined ( __ICCARM__ )
extern uint32_t __ICFEDIT_region_ROM_start__;
extern uint32_t __ICFEDIT_region_ROM_end__;
address = (uint32_t)&__ICFEDIT_region_ROM_start__;
size = (uint32_t)&__ICFEDIT_region_ROM_end__ - (uint32_t)&__ICFEDIT_region_ROM_start__ + 1;
#elif defined (__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$ER_ROM$$Base;
extern uint32_t Image$$ER_ROM$$Limit;
address = (uint32_t)&Image$$ER_ROM$$Base;
size = (uint32_t)&Image$$ER_ROM$$Limit-(uint32_t)&Image$$ER_ROM$$Base;
#elif defined ( __GNUC__ )
extern uint32_t __FLASH_BEGIN;
extern uint32_t __FLASH_SIZE;
address = (uint32_t)&__FLASH_BEGIN;
size = (uint32_t)&__FLASH_SIZE;
#else
#error "Compiler toolchain is unsupported"
#endif
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.Number = index;
MPU_InitStruct.SubRegionDisable = 0u;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
MPU_AdjustRegionAddressSize(address, size, &MPU_InitStruct);
HAL_MPU_ConfigRegion(&MPU_InitStruct);
index++;
/* Reset unused MPU regions */
for(; index < __MPU_REGIONCOUNT ; index++)
{
/* All unused regions disabled */
MPU_InitStruct.Enable = MPU_REGION_DISABLE;
MPU_InitStruct.Number = index;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
}
/* Enable the MPU */
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
}
/**
* @brief This function adjusts the MPU region Address and Size within an MPU configuration.
* @param Address memory address
* @param Size memory size
* @param pInit pointer to an MPU initialization structure
* @retval None
*/
static void MPU_AdjustRegionAddressSize(uint32_t Address, uint32_t Size, MPU_Region_InitTypeDef* pInit)
{
/* Compute the MPU region size */
pInit->Size = ((31 - __CLZ(Size)) - 1);
if (Size > (1u << (pInit->Size + 1)))
{
pInit->Size++;
}
uint32_t Modulo = Address % (1 << (pInit->Size - 1));
if (0 != Modulo)
{
/* Align address with MPU region size considering there is no need to increase the size */
pInit->BaseAddress = Address - Modulo;
}
else
{
pInit->BaseAddress = Address;
}
}
void board_init(void) {
HAL_Init();
MPU_Config();
SCB_EnableICache();
SCB_EnableDCache();
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
// Implemented in board.h
SystemClock_Config();

6
hw/bsp/stm32h7rs/family.cmake
View File

@@ -54,7 +54,7 @@ function(add_board_target BOARD_TARGET)
set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
if(NOT DEFINED LD_FILE_GNU)
set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash.ld)
set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${MCU_VARIANT}_flash.ld)
endif()
set(LD_FILE_Clang ${LD_FILE_GNU})
if(NOT DEFINED LD_FILE_IAR)
@@ -87,8 +87,8 @@ function(add_board_target BOARD_TARGET)
BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
BOARD_TUH_RHPORT=${RHPORT_HOST}
BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
SEGGER_RTT_SECTION="noncacheable_buffer"
BUFFER_SIZE_UP=0x3000
SEGGER_RTT_SECTION=\"noncacheable_buffer\"
BUFFER_SIZE_UP=0x300
)
update_board(${BOARD_TARGET})

6
hw/bsp/stm32h7rs/family.mk
View File

@@ -43,8 +43,8 @@ CFLAGS += \
-DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \
-DBOARD_TUH_RHPORT=${RHPORT_HOST} \
-DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \
-DSEGGER_RTT_SECTION=\"noncacheable_buffer\" \
-DBUFFER_SIZE_UP=0x3000 \
-DSEGGER_RTT_SECTION="noncacheable_buffer" \
-DBUFFER_SIZE_UP=0x300 \
# GCC Flags
CFLAGS_GCC += \
@@ -91,5 +91,5 @@ SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s
SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
# Linker
LD_FILE_GCC ?= $(ST_CMSIS)/Source/Templates/gcc/linker/$(MCU_VARIANT)_flash.ld
LD_FILE_GCC ?= $(FAMILY_PATH)/linker/$(MCU_VARIANT)_flash.ld
LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf

4
hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/stm32h7s3xx_flash.ld → hw/bsp/stm32h7rs/linker/stm32h7s3xx_flash.ld
View File

@@ -43,7 +43,7 @@ __FLASH_SIZE = 0x00010000;
__RAM_BEGIN = 0x24000000;
__RAM_SIZE = 0x4FC00;
__RAM_NONCACHEABLEBUFFER_SIZE = 0x4000;
__RAM_NONCACHEABLEBUFFER_SIZE = 0x400;
/* Memories definition */
MEMORY
@@ -182,7 +182,7 @@ SECTIONS
{
__NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */
KEEP(*(noncacheable_buffer))
__NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */
__NONCACHEABLEBUFFER_END = .; /* create symbol for end of section */
} > RAM_NONCACHEABLEBUFFER
/* User_heap_stack section, used to check that there is enough "DTCM" Ram type memory left */

8
src/class/audio/audio_device.c
View File

@@ -109,14 +109,14 @@
// Put swap buffer in USB section only if necessary
#if USE_LINEAR_BUFFER
#define IN_SW_BUF_MEM_ATTR TU_ATTR_ALIGNED(4)
#define IN_SW_BUF_MEM_ATTR
#else
#define IN_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN
#define IN_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION
#endif
#if USE_LINEAR_BUFFER
#define OUT_SW_BUF_MEM_ATTR TU_ATTR_ALIGNED(4)
#define OUT_SW_BUF_MEM_ATTR
#else
#define OUT_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN
#define OUT_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION
#endif
// EP IN software buffers and mutexes

28
src/common/tusb_mcu.h
View File

@@ -117,9 +117,9 @@
#define TUP_RHPORT_HIGHSPEED 1
#if __CORTEX_M == 7
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
#endif
#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K)
@@ -220,12 +220,25 @@
#define TUP_RHPORT_HIGHSPEED 1 // Port0: FS, Port1: HS
#endif
// Enable dcache if DMA is enabled
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
#elif TU_CHECK_MCU(OPT_MCU_STM32H7)
#include "stm32h7xx.h"
#define TUP_USBIP_DWC2
#define TUP_USBIP_DWC2_STM32
#define TUP_DCD_ENDPOINT_MAX 9
#if __CORTEX_M == 7
// Enable dcache if DMA is enabled
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
#endif
#elif TU_CHECK_MCU(OPT_MCU_STM32H5)
#define TUP_USBIP_FSDEV
#define TUP_USBIP_FSDEV_STM32
@@ -322,6 +335,11 @@
// MCU with on-chip HS Phy
#define TUP_RHPORT_HIGHSPEED 1
// Enable dcache if DMA is enabled
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
//--------------------------------------------------------------------+
// Sony
//--------------------------------------------------------------------+
@@ -392,8 +410,8 @@
#define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUH_DWC2_DMA_ENABLE
// Enable dcache if DMA is enabled
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 64
#elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2)

8
src/common/tusb_types.h
View File

@@ -43,14 +43,14 @@
#define TUD_EPBUF_DEF(_name, _size) \
union { \
CFG_TUD_MEM_ALIGN uint8_t _name[_size]; \
uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(_size)]; \
TU_ATTR_ALIGNED(CFG_TUD_MEM_DCACHE_ENABLE ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(_size)]; \
}
// Declare an endpoint buffer with a type
#define TUD_EPBUF_TYPE_DEF(_type, _name) \
union { \
CFG_TUD_MEM_ALIGN _type _name; \
uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
TU_ATTR_ALIGNED(CFG_TUD_MEM_DCACHE_ENABLE ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
}
//------------- Host DCache declaration -------------//
@@ -61,14 +61,14 @@
#define TUH_EPBUF_DEF(_name, _size) \
union { \
CFG_TUH_MEM_ALIGN uint8_t _name[_size]; \
uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(_size)]; \
TU_ATTR_ALIGNED(CFG_TUH_MEM_DCACHE_ENABLE ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(_size)]; \
}
// Declare an endpoint buffer with a type
#define TUH_EPBUF_TYPE_DEF(_type, _name) \
union { \
CFG_TUH_MEM_ALIGN _type _name; \
uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
TU_ATTR_ALIGNED(CFG_TUH_MEM_DCACHE_ENABLE ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
}

71
src/portable/synopsys/dwc2/dwc2_stm32.h
View File

@@ -279,6 +279,77 @@ static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
}
}
//------------- DCache -------------//
#if CFG_TUD_MEM_DCACHE_ENABLE || CFG_TUH_MEM_DCACHE_ENABLE
typedef struct {
uintptr_t start;
uintptr_t end;
} mem_region_t;
// Can be used to define additional uncached regions
#ifndef CFG_DWC2_MEM_UNCACHED_REGIONS
#define CFG_DWC2_MEM_UNCACHED_REGIONS
#endif
static mem_region_t uncached_regions[] = {
// DTCM (although USB DMA can't transfer to/from DTCM)
#if CFG_TUSB_MCU == OPT_MCU_STM32H7
{.start = 0x20000000, .end = 0x2001FFFF},
#elif CFG_TUSB_MCU == OPT_MCU_STM32H7RS
// DTCM (although USB DMA can't transfer to/from DTCM)
{.start = 0x20000000, .end = 0x2002FFFF},
#elif CFG_TUSB_MCU == OPT_MCU_STM32F7
// DTCM
{.start = 0x20000000, .end = 0x2000FFFF},
#else
#error "Cache maintenance is not supported yet"
#endif
CFG_DWC2_MEM_UNCACHED_REGIONS
};
TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_t size) {
if (size & (CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT-1)) {
size = (size & ~(CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT-1)) + CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT;
}
return size;
}
TU_ATTR_ALWAYS_INLINE static inline bool is_cache_mem(uintptr_t addr) {
for (unsigned int i = 0; i < TU_ARRAY_SIZE(uncached_regions); i++) {
if (uncached_regions[i].start <= addr && addr <= uncached_regions[i].end) { return false; }
}
return true;
}
TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_clean(void const* addr, uint32_t data_size) {
const uintptr_t addr32 = (uintptr_t) addr;
if (is_cache_mem(addr32)) {
data_size = round_up_to_cache_line_size(data_size);
SCB_CleanDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size);
}
return true;
}
TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_invalidate(void const* addr, uint32_t data_size) {
const uintptr_t addr32 = (uintptr_t) addr;
if (is_cache_mem(addr32)) {
data_size = round_up_to_cache_line_size(data_size);
SCB_InvalidateDCache_by_Addr((void*) addr32, (int32_t) data_size);
}
return true;
}
TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
const uintptr_t addr32 = (uintptr_t) addr;
if (is_cache_mem(addr32)) {
data_size = round_up_to_cache_line_size(data_size);
SCB_CleanInvalidateDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size);
}
return true;
}
#endif
#ifdef __cplusplus
}
#endif

4
src/tusb_option.h
View File

@@ -420,7 +420,7 @@
#ifndef CFG_TUSB_MEM_DCACHE_LINE_SIZE
#ifndef CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 1
#endif
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT
@@ -428,7 +428,7 @@
// OS selection
#ifndef CFG_TUSB_OS
#define CFG_TUSB_OS OPT_OS_NONE
#define CFG_TUSB_OS OPT_OS_NONE
#endif
#ifndef CFG_TUSB_OS_INC_PATH