Merge pull request #3140 from james-advatek/stm32n657nucleo
Add STM32N657 Nucleo Board support
This commit is contained in:
Ha Thach
1
.github/workflows/ci_set_matrix.py
vendored
1
.github/workflows/ci_set_matrix.py
vendored
@@ -42,6 +42,7 @@ family_list = {
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"stm32g0 stm32g4 stm32h5": ["arm-gcc", "arm-clang", "arm-iar"],
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"stm32h7 stm32h7rs": ["arm-gcc", "arm-clang", "arm-iar"],
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"stm32l0 stm32l4": ["arm-gcc", "arm-clang", "arm-iar"],
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"stm32n6": ["arm-gcc"],
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"stm32u5 stm32wb": ["arm-gcc", "arm-clang", "arm-iar"],
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"xmc4000": ["arm-gcc"],
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"-bespressif_s2_devkitc": ["esp-idf"],
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20
README.rst
20
README.rst
@@ -183,15 +183,13 @@ Supported CPUs
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+--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
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| Sony | CXD56 | ✔ | ✖ | ✔ | cxd56 | |
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+--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
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| ST STM32 | F0 | ✔ | ✖ | ✖ | stm32_fsdev | |
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| ST STM32 | F0, F3, L0, L1, L5, WBx5 | ✔ | ✖ | ✖ | stm32_fsdev | |
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| +----+------------------------+--------+------+-----------+------------------------+-------------------+
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| | F1 | 102, 103 | ✔ | ✖ | ✖ | stm32_fsdev | |
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| | +------------------------+--------+------+-----------+------------------------+-------------------+
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| | | 105, 107 | ✔ | ✔ | ✖ | dwc2 | |
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| +----+------------------------+--------+------+-----------+------------------------+-------------------+
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| | F2, F4, F7, H7 | ✔ | ✔ | ✔ | dwc2 | |
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| +-----------------------------+--------+------+-----------+------------------------+-------------------+
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| | F3 | ✔ | ✖ | ✖ | stm32_fsdev | |
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| | F2, F4, F7, H7, H7RS | ✔ | ✔ | ✔ | dwc2 | |
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| +-----------------------------+--------+------+-----------+------------------------+-------------------+
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| | C0, G0, H5 | ✔ | | ✖ | stm32_fsdev | |
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| +-----------------------------+--------+------+-----------+------------------------+-------------------+
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@@ -201,25 +199,19 @@ Supported CPUs
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| +----+------------------------+--------+------+-----------+------------------------+-------------------+
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| | L4 | 4x2, 4x3 | ✔ | ✖ | ✖ | stm32_fsdev | |
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| | +------------------------+--------+------+-----------+------------------------+-------------------+
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| | | 4x5, 4x6 | ✔ | ✔ | ✖ | dwc2 | |
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| | | 4x5, 4x6, 4+ | ✔ | ✔ | ✖ | dwc2 | |
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| +----+------------------------+--------+------+-----------+------------------------+-------------------+
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| | L4+ | ✔ | ✔ | ✖ | dwc2 | |
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| +-----------------------------+--------+------+-----------+------------------------+-------------------+
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| | L5 | ✔ | ✖ | ✖ | stm32_fsdev | |
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| | N6 | ✔ | ✔ | ✔ | dwc2 | |
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| +----+------------------------+--------+------+-----------+------------------------+-------------------+
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| | U5 | 535, 545 | ✔ | | ✖ | stm32_fsdev | |
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| | +------------------------+--------+------+-----------+------------------------+-------------------+
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| | | 575, 585 | ✔ | ✔ | ✖ | dwc2 | |
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| | +------------------------+--------+------+-----------+------------------------+-------------------+
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| | | 59x,5Ax,5Fx,5Gx | ✔ | ✔ | ✔ | dwc2 | |
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| +----+------------------------+--------+------+-----------+------------------------+-------------------+
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| | WBx5 | ✔ | ✖ | ✖ | stm32_fsdev | |
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+--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
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+--------------+----+------------------------+--------+------+-----------+------------------------+-------------------+
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| TI | MSP430 | ✔ | ✖ | ✖ | msp430x5xx | |
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| +-----------------------------+--------+------+-----------+------------------------+-------------------+
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| | MSP432E4 | ✔ | | ✖ | musb | |
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| +-----------------------------+--------+------+-----------+------------------------+-------------------+
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| | TM4C123 | ✔ | | ✖ | musb | |
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| | MSP432E4, TM4C123 | ✔ | | ✖ | musb | |
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+--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
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| ValentyUSB | eptri | ✔ | ✖ | ✖ | eptri | |
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+--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
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@@ -7,25 +7,25 @@ It is responsible for getting the MCU started and the USB peripheral clocked wit
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- One LED : for status
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- One Button : to get input from user
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- One UART : optional for device, but required for host examples
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- One UART : needed for logging with LOGGER=uart, maybe required for host/dual examples
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Following boards are supported
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Analog Devices
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--------------
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============= ================ ======== =========================================================================================================================== ======
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Board Name Family URL Note
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============= ================ ======== =========================================================================================================================== ======
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max32650evkit MAX32650 EVKIT max32650 https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650-evkit.html#eb-overview
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max32650fthr MAX32650 Feather max32650 https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650fthr.html
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max32651evkit MAX32651 EVKIT max32650 https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32651-evkit.html
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max32666evkit MAX32666 EVKIT max32666 https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666evkit.html
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max32666fthr MAX32666 Feather max32666 https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666fthr.html
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apard32690 APARD32690-SL max32690 https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/ad-apard32690-sl.html
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max32690evkit MAX32690 EVKIT max32690 https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32690evkit.html
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max78002evkit MAX78002 EVKIT max78002 https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78002evkit.html
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============= ================ ======== =========================================================================================================================== ======
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============= ================ ======== ================================================================================================================= ======
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Board Name Family URL Note
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============= ================ ======== ================================================================================================================= ======
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apard32690 APARD32690-SL maxim https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/ad-apard32690-sl.html
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max32650evkit MAX32650 EVKIT maxim https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650-evkit.html
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max32650fthr MAX32650 Feather maxim https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650fthr.html
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max32651evkit MAX32651 EVKIT maxim https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32651-evkit.html
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max32666evkit MAX32666 EVKIT maxim https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666evkit.html
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max32666fthr MAX32666 Feather maxim https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666fthr.html
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max32690evkit MAX32690 EVKIT maxim https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32690evkit.html
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max78002evkit MAX78002 EVKIT maxim https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78002evkit.html
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============= ================ ======== ================================================================================================================= ======
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Bridgetek
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---------
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@@ -43,6 +43,7 @@ Espressif
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Board Name Family URL Note
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========================= ============================== ========= ======================================================================================================== ======
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adafruit_feather_esp32_v2 Adafruit Feather ESP32 v2 espressif https://www.adafruit.com/product/5400
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adafruit_feather_esp32c6 Adafruit Feather EPS32-C6 espressif https://www.adafruit.com/product/5933
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adafruit_feather_esp32s2 Adafruit Feather ESP32S2 espressif https://www.adafruit.com/product/5000
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adafruit_feather_esp32s3 Adafruit Feather ESP32S3 espressif https://www.adafruit.com/product/5323
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adafruit_magtag_29gray Adafruit MagTag 2.9" Grayscale espressif https://www.adafruit.com/product/4800
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@@ -191,13 +192,19 @@ pca10100 Nordic nRF52833 DK nrf ht
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Raspberry Pi
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------------
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================= ================= ============== ========================================================== ======
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Board Name Family URL Note
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================= ================= ============== ========================================================== ======
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raspberrypi_zero Raspberry Pi Zero broadcom_32bit https://www.raspberrypi.org/products/raspberry-pi-zero/
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raspberrypi_cm4 Raspberry CM4 broadcom_64bit https://www.raspberrypi.org/products/compute-module-4
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raspberrypi_zero2 Raspberry Zero2 broadcom_64bit https://www.raspberrypi.org/products/raspberry-pi-zero-2-w
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================= ================= ============== ========================================================== ======
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================================ ============================================ ============== ========================================================== ======
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Board Name Family URL Note
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================================ ============================================ ============== ========================================================== ======
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raspberrypi_zero Raspberry Pi Zero broadcom_32bit https://www.raspberrypi.org/products/raspberry-pi-zero/
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raspberrypi_cm4 Raspberry CM4 broadcom_64bit https://www.raspberrypi.org/products/compute-module-4
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raspberrypi_zero2 Raspberry Zero2 broadcom_64bit https://www.raspberrypi.org/products/raspberry-pi-zero-2-w
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adafruit_feather_rp2040_usb_host Adafruit Feather RP2040 with USB Type A Host rp2040 https://www.adafruit.com/product/5723
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adafruit_fruit_jam Adafruit Fruit Jam - Mini RP2350 rp2040 https://www.adafruit.com/product/6200
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adafruit_metro_rp2350 Adafruit Metro RP2350 rp2040 https://www.adafruit.com/product/6003
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raspberry_pi_pico Pico rp2040 https://www.raspberrypi.com/products/raspberry-pi-pico/
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raspberry_pi_pico2 Pico2 rp2040 https://www.raspberrypi.com/products/raspberry-pi-pico-2/
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raspberry_pi_pico_w Pico rp2040 https://www.raspberrypi.com/products/raspberry-pi-pico/
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================================ ============================================ ============== ========================================================== ======
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Renesas
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-------
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@@ -220,63 +227,64 @@ uno_r4 Arduino UNO R4 ra https://store-usa.arduino
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STMicroelectronics
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------------------
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=================== ================================= ======== ================================================================= ======
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Board Name Family URL Note
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=================== ================================= ======== ================================================================= ======
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stm32c071nucleo STM32C071 Nucleo stm32c0 https://www.st.com/en/evaluation-tools/nucleo-g071rb.html
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stm32f070rbnucleo STM32 F070 Nucleo stm32f0 https://www.st.com/en/evaluation-tools/nucleo-f070rb.html
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stm32f072disco STM32 F072 Discovery stm32f0 https://www.st.com/en/evaluation-tools/32f072bdiscovery.html
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stm32f072eval STM32 F072 Eval stm32f0 https://www.st.com/en/evaluation-tools/stm32072b-eval.html
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stm32f103_bluepill STM32 F103 Bluepill stm32f1 https://stm32-base.org/boards/STM32F103C8T6-Blue-Pill
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stm32f103_mini_2 STM32 F103 Mini v2 stm32f1 https://stm32-base.org/boards/STM32F103RCT6-STM32-Mini-V2.0
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stm32f103ze_iar IAR STM32 F103ze starter kit stm32f1 n/a
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stm32f207nucleo STM32 F207 Nucleo stm32f2 https://www.st.com/en/evaluation-tools/nucleo-f207zg.html
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stm32f303disco STM32 F303 Discovery stm32f3 https://www.st.com/en/evaluation-tools/stm32f3discovery.html
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feather_stm32f405 Adafruit Feather STM32F405 stm32f4 https://www.adafruit.com/product/4382
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pyboardv11 Pyboard v1.1 stm32f4 https://www.adafruit.com/product/2390
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stm32f401blackpill STM32 F401 Blackpill stm32f4 https://stm32-base.org/boards/STM32F401CCU6-WeAct-Black-Pill-V1.2
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stm32f407blackvet STM32 F407 Blackvet stm32f4 https://stm32-base.org/boards/STM32F407VET6-STM32-F4VE-V2.0
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stm32f407disco STM32 F407 Discovery stm32f4 https://www.st.com/en/evaluation-tools/stm32f4discovery.html
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stm32f411blackpill STM32 F411 Blackpill stm32f4 https://stm32-base.org/boards/STM32F411CEU6-WeAct-Black-Pill-V2.0
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stm32f411disco STM32 F411 Discovery stm32f4 https://www.st.com/en/evaluation-tools/32f411ediscovery.html
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stm32f412disco STM32 F412 Discovery stm32f4 https://www.st.com/en/evaluation-tools/32f412gdiscovery.html
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stm32f412nucleo STM32 F412 Nucleo stm32f4 https://www.st.com/en/evaluation-tools/nucleo-f412zg.html
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stm32f439nucleo STM32 F439 Nucleo stm32f4 https://www.st.com/en/evaluation-tools/nucleo-f439zi.html
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stlinkv3mini Stlink-v3 mini stm32f7 https://www.st.com/en/development-tools/stlink-v3mini.html
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stm32f723disco STM32 F723 Discovery stm32f7 https://www.st.com/en/evaluation-tools/32f723ediscovery.html
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stm32f746disco STM32 F746 Discovery stm32f7 https://www.st.com/en/evaluation-tools/32f746gdiscovery.html
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stm32f746nucleo STM32 F746 Nucleo stm32f7 https://www.st.com/en/evaluation-tools/nucleo-f746zg.html
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stm32f767nucleo STM32 F767 Nucleo stm32f7 https://www.st.com/en/evaluation-tools/nucleo-f767zi.html
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stm32f769disco STM32 F769 Discovery stm32f7 https://www.st.com/en/evaluation-tools/32f769idiscovery.html
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stm32g0b1nucleo STM32 G0B1 Nucleo stm32g0 https://www.st.com/en/evaluation-tools/nucleo-g0b1re.html
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b_g474e_dpow1 STM32 B-G474E-DPOW1 Discovery kit stm32g4 https://www.st.com/en/evaluation-tools/b-g474e-dpow1.html
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stm32g474nucleo STM32 G474 Nucleo stm32g4 https://www.st.com/en/evaluation-tools/nucleo-g474re.html
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stm32g491nucleo STM32 G491 Nucleo stm32g4 https://www.st.com/en/evaluation-tools/nucleo-g491re.html
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stm32h503nucleo STM32 H503 Nucleo stm32h5 https://www.st.com/en/evaluation-tools/nucleo-h503rb.html
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stm32h563nucleo STM32 H563 Nucleo stm32h5 https://www.st.com/en/evaluation-tools/nucleo-h563zi.html
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stm32h573i_dk STM32 H573i Discovery stm32h5 https://www.st.com/en/evaluation-tools/stm32h573i-dk.html
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daisyseed Daisy Seed stm32h7 https://electro-smith.com/products/daisy-seed
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stm32h723nucleo STM32 H723 Nucleo stm32h7 https://www.st.com/en/evaluation-tools/nucleo-h723zg.html
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stm32h743eval STM32 H743 Eval stm32h7 https://www.st.com/en/evaluation-tools/stm32h743i-eval.html
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stm32h743nucleo STM32 H743 Nucleo stm32h7 https://www.st.com/en/evaluation-tools/nucleo-h743zi.html
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stm32h745disco STM32 H745 Discovery stm32h7 https://www.st.com/en/evaluation-tools/stm32h745i-disco.html
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stm32h750_weact STM32 H750 WeAct stm32h7 https://www.adafruit.com/product/5032
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stm32h750bdk STM32 H750b Discovery Kit stm32h7 https://www.st.com/en/evaluation-tools/stm32h750b-dk.html
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stm32h7s3nucleo STM32 H7S3 Nucleo stm32h7rs https://www.st.com/en/evaluation-tools/nucleo-h7s3l8.html
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waveshare_openh743i Waveshare Open H743i stm32h7 https://www.waveshare.com/openh743i-c-standard.htm
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stm32l052dap52 STM32 L052 DAP stm32l0 n/a
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stm32l0538disco STM32 L0538 Discovery stm32l0 https://www.st.com/en/evaluation-tools/32l0538discovery.html
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stm32l412nucleo STM32 L412 Nucleo stm32l4 https://www.st.com/en/evaluation-tools/nucleo-l412kb.html
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stm32l476disco STM32 L476 Disco stm32l4 https://www.st.com/en/evaluation-tools/32l476gdiscovery.html
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stm32l4p5nucleo STM32 L4P5 Nucleo stm32l4 https://www.st.com/en/evaluation-tools/nucleo-l4p5zg.html
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stm32l4r5nucleo STM32 L4R5 Nucleo stm32l4 https://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html
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b_u585i_iot2a STM32 B-U585i IOT2A Discovery kit stm32u5 https://www.st.com/en/evaluation-tools/b-u585i-iot02a.html
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stm32u545nucleo STM32 U545 Nucleo stm32u5 https://www.st.com/en/evaluation-tools/nucleo-u545re-q.html
|
||||
stm32u575eval STM32 U575 Eval stm32u5 https://www.st.com/en/evaluation-tools/stm32u575i-ev.html
|
||||
stm32u575nucleo STM32 U575 Nucleo stm32u5 https://www.st.com/en/evaluation-tools/nucleo-u575zi-q.html
|
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stm32u5a5nucleo STM32 U5a5 Nucleo stm32u5 https://www.st.com/en/evaluation-tools/nucleo-u5a5zj-q.html
|
||||
stm32wb55nucleo STM32 P-NUCLEO-WB55 stm32wb https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html
|
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=================== ================================= ======== ================================================================= ======
|
||||
=================== ================================= ========= ================================================================= ======
|
||||
Board Name Family URL Note
|
||||
=================== ================================= ========= ================================================================= ======
|
||||
stm32c071nucleo STM32C071 Nucleo stm32c0 https://www.st.com/en/evaluation-tools/nucleo-g071rb.html
|
||||
stm32f070rbnucleo STM32 F070 Nucleo stm32f0 https://www.st.com/en/evaluation-tools/nucleo-f070rb.html
|
||||
stm32f072disco STM32 F072 Discovery stm32f0 https://www.st.com/en/evaluation-tools/32f072bdiscovery.html
|
||||
stm32f072eval STM32 F072 Eval stm32f0 https://www.st.com/en/evaluation-tools/stm32072b-eval.html
|
||||
stm32f103_bluepill STM32 F103 Bluepill stm32f1 https://stm32-base.org/boards/STM32F103C8T6-Blue-Pill
|
||||
stm32f103_mini_2 STM32 F103 Mini v2 stm32f1 https://stm32-base.org/boards/STM32F103RCT6-STM32-Mini-V2.0
|
||||
stm32f103ze_iar IAR STM32 F103ze starter kit stm32f1 n/a
|
||||
stm32f207nucleo STM32 F207 Nucleo stm32f2 https://www.st.com/en/evaluation-tools/nucleo-f207zg.html
|
||||
stm32f303disco STM32 F303 Discovery stm32f3 https://www.st.com/en/evaluation-tools/stm32f3discovery.html
|
||||
feather_stm32f405 Adafruit Feather STM32F405 stm32f4 https://www.adafruit.com/product/4382
|
||||
pyboardv11 Pyboard v1.1 stm32f4 https://www.adafruit.com/product/2390
|
||||
stm32f401blackpill STM32 F401 Blackpill stm32f4 https://stm32-base.org/boards/STM32F401CCU6-WeAct-Black-Pill-V1.2
|
||||
stm32f407blackvet STM32 F407 Blackvet stm32f4 https://stm32-base.org/boards/STM32F407VET6-STM32-F4VE-V2.0
|
||||
stm32f407disco STM32 F407 Discovery stm32f4 https://www.st.com/en/evaluation-tools/stm32f4discovery.html
|
||||
stm32f411blackpill STM32 F411 Blackpill stm32f4 https://stm32-base.org/boards/STM32F411CEU6-WeAct-Black-Pill-V2.0
|
||||
stm32f411disco STM32 F411 Discovery stm32f4 https://www.st.com/en/evaluation-tools/32f411ediscovery.html
|
||||
stm32f412disco STM32 F412 Discovery stm32f4 https://www.st.com/en/evaluation-tools/32f412gdiscovery.html
|
||||
stm32f412nucleo STM32 F412 Nucleo stm32f4 https://www.st.com/en/evaluation-tools/nucleo-f412zg.html
|
||||
stm32f439nucleo STM32 F439 Nucleo stm32f4 https://www.st.com/en/evaluation-tools/nucleo-f439zi.html
|
||||
stlinkv3mini Stlink-v3 mini stm32f7 https://www.st.com/en/development-tools/stlink-v3mini.html
|
||||
stm32f723disco STM32 F723 Discovery stm32f7 https://www.st.com/en/evaluation-tools/32f723ediscovery.html
|
||||
stm32f746disco STM32 F746 Discovery stm32f7 https://www.st.com/en/evaluation-tools/32f746gdiscovery.html
|
||||
stm32f746nucleo STM32 F746 Nucleo stm32f7 https://www.st.com/en/evaluation-tools/nucleo-f746zg.html
|
||||
stm32f767nucleo STM32 F767 Nucleo stm32f7 https://www.st.com/en/evaluation-tools/nucleo-f767zi.html
|
||||
stm32f769disco STM32 F769 Discovery stm32f7 https://www.st.com/en/evaluation-tools/32f769idiscovery.html
|
||||
stm32g0b1nucleo STM32 G0B1 Nucleo stm32g0 https://www.st.com/en/evaluation-tools/nucleo-g0b1re.html
|
||||
b_g474e_dpow1 STM32 B-G474E-DPOW1 Discovery kit stm32g4 https://www.st.com/en/evaluation-tools/b-g474e-dpow1.html
|
||||
stm32g474nucleo STM32 G474 Nucleo stm32g4 https://www.st.com/en/evaluation-tools/nucleo-g474re.html
|
||||
stm32g491nucleo STM32 G491 Nucleo stm32g4 https://www.st.com/en/evaluation-tools/nucleo-g491re.html
|
||||
stm32h503nucleo STM32 H503 Nucleo stm32h5 https://www.st.com/en/evaluation-tools/nucleo-h503rb.html
|
||||
stm32h563nucleo STM32 H563 Nucleo stm32h5 https://www.st.com/en/evaluation-tools/nucleo-h563zi.html
|
||||
stm32h573i_dk STM32 H573i Discovery stm32h5 https://www.st.com/en/evaluation-tools/stm32h573i-dk.html
|
||||
daisyseed Daisy Seed stm32h7 https://electro-smith.com/products/daisy-seed
|
||||
stm32h723nucleo STM32 H723 Nucleo stm32h7 https://www.st.com/en/evaluation-tools/nucleo-h723zg.html
|
||||
stm32h743eval STM32 H743 Eval stm32h7 https://www.st.com/en/evaluation-tools/stm32h743i-eval.html
|
||||
stm32h743nucleo STM32 H743 Nucleo stm32h7 https://www.st.com/en/evaluation-tools/nucleo-h743zi.html
|
||||
stm32h745disco STM32 H745 Discovery stm32h7 https://www.st.com/en/evaluation-tools/stm32h745i-disco.html
|
||||
stm32h750_weact STM32 H750 WeAct stm32h7 https://www.adafruit.com/product/5032
|
||||
stm32h750bdk STM32 H750b Discovery Kit stm32h7 https://www.st.com/en/evaluation-tools/stm32h750b-dk.html
|
||||
waveshare_openh743i Waveshare Open H743i stm32h7 https://www.waveshare.com/openh743i-c-standard.htm
|
||||
stm32h7s3nucleo STM32 H7S3L8 Nucleo stm32h7rs https://www.st.com/en/evaluation-tools/nucleo-h7s3l8.html
|
||||
stm32l052dap52 STM32 L052 DAP stm32l0 n/a
|
||||
stm32l0538disco STM32 L0538 Discovery stm32l0 https://www.st.com/en/evaluation-tools/32l0538discovery.html
|
||||
stm32l412nucleo STM32 L412 Nucleo stm32l4 https://www.st.com/en/evaluation-tools/nucleo-l412kb.html
|
||||
stm32l476disco STM32 L476 Disco stm32l4 https://www.st.com/en/evaluation-tools/32l476gdiscovery.html
|
||||
stm32l4p5nucleo STM32 L4P5 Nucleo stm32l4 https://www.st.com/en/evaluation-tools/nucleo-l4p5zg.html
|
||||
stm32l4r5nucleo STM32 L4R5 Nucleo stm32l4 https://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html
|
||||
stm32n657nucleo STM32 N657X0-Q Nucleo stm32n6 https://www.st.com/en/evaluation-tools/nucleo-n657x0-q.html
|
||||
b_u585i_iot2a STM32 B-U585i IOT2A Discovery kit stm32u5 https://www.st.com/en/evaluation-tools/b-u585i-iot02a.html
|
||||
stm32u545nucleo STM32 U545 Nucleo stm32u5 https://www.st.com/en/evaluation-tools/nucleo-u545re-q.html
|
||||
stm32u575eval STM32 U575 Eval stm32u5 https://www.st.com/en/evaluation-tools/stm32u575i-ev.html
|
||||
stm32u575nucleo STM32 U575 Nucleo stm32u5 https://www.st.com/en/evaluation-tools/nucleo-u575zi-q.html
|
||||
stm32u5a5nucleo STM32 U5a5 Nucleo stm32u5 https://www.st.com/en/evaluation-tools/nucleo-u5a5zj-q.html
|
||||
stm32wb55nucleo STM32 P-NUCLEO-WB55 stm32wb https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html
|
||||
=================== ================================= ========= ================================================================= ======
|
||||
|
||||
Sunxi
|
||||
-----
|
||||
|
||||
@@ -4,11 +4,11 @@ Dependencies
|
||||
|
||||
MCU low-level peripheral driver and external libraries for building TinyUSB examples
|
||||
|
||||
======================================== ============================================================== ======================================== ====================================================================================================================================================================================================================================================================================================================================
|
||||
======================================== ================================================================ ======================================== ======================================================================================================================================================================================================================================================================================================================================================
|
||||
Local Path Repo Commit Required by
|
||||
======================================== ============================================================== ======================================== ====================================================================================================================================================================================================================================================================================================================================
|
||||
======================================== ================================================================ ======================================== ======================================================================================================================================================================================================================================================================================================================================================
|
||||
hw/mcu/allwinner https://github.com/hathach/allwinner_driver.git 8e5e89e8e132c0fd90e72d5422e5d3d68232b756 fc100s
|
||||
hw/mcu/analog/max32 https://github.com/analogdevicesinc/msdk.git b20b398d3e5e2007594e54a74ba3d2a2e50ddd75 max32650 max32666 max32690 max78002
|
||||
hw/mcu/analog/msdk https://github.com/analogdevicesinc/msdk.git b20b398d3e5e2007594e54a74ba3d2a2e50ddd75 maxim
|
||||
hw/mcu/bridgetek/ft9xx/ft90x-sdk https://github.com/BRTSG-FOSS/ft90x-sdk.git 91060164afe239fcb394122e8bf9eb24d3194eb1 brtmm90x
|
||||
hw/mcu/broadcom https://github.com/adafruit/broadcom-peripherals.git 08370086080759ed54ac1136d62d2ad24c6fa267 broadcom_32bit broadcom_64bit
|
||||
hw/mcu/gd/nuclei-sdk https://github.com/Nuclei-Software/nuclei-sdk.git 7eb7bfa9ea4fbeacfafe1d5f77d5a0e6ed3922e7 gd32vf103
|
||||
@@ -18,8 +18,8 @@ hw/mcu/mindmotion/mm32sdk https://github.com/hathach/mm32sdk.git
|
||||
hw/mcu/nordic/nrfx https://github.com/NordicSemiconductor/nrfx.git 7c47cc0a56ce44658e6da2458e86cd8783ccc4a2 nrf
|
||||
hw/mcu/nuvoton https://github.com/majbthrd/nuc_driver.git 2204191ec76283371419fbcec207da02e1bc22fa nuc
|
||||
hw/mcu/nxp/lpcopen https://github.com/hathach/nxp_lpcopen.git b41cf930e65c734d8ec6de04f1d57d46787c76ae lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43
|
||||
hw/mcu/nxp/mcux-sdk https://github.com/hathach/mcux-sdk.git 144f1eb7ea8c06512e12f12b27383601c0272410 kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt
|
||||
hw/mcu/raspberry_pi/Pico-PIO-USB https://github.com/sekigon-gonnoc/Pico-PIO-USB.git fe9133fc513b82cc3dc62c67cb51f2339cf29ef7 rp2040
|
||||
hw/mcu/nxp/mcux-sdk https://github.com/nxp-mcuxpresso/mcux-sdk a1bdae309a14ec95a4f64a96d3315a4f89c397c6 kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt
|
||||
hw/mcu/raspberry_pi/Pico-PIO-USB https://github.com/sekigon-gonnoc/Pico-PIO-USB.git 3c1eec341a5232640e4c00628b889b641af34b28 rp2040
|
||||
hw/mcu/renesas/fsp https://github.com/renesas/fsp.git edcc97d684b6f716728a60d7a6fea049d9870bd6 ra
|
||||
hw/mcu/renesas/rx https://github.com/kkitayam/rx_device.git 706b4e0cf485605c32351e2f90f5698267996023 rx
|
||||
hw/mcu/silabs/cmsis-dfp-efm32gg12b https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b.git f1c31b7887669cb230b3ea63f9b56769078960bc efm32
|
||||
@@ -40,8 +40,9 @@ hw/mcu/st/cmsis_device_l0 https://github.com/STMicroelectronics/
|
||||
hw/mcu/st/cmsis_device_l1 https://github.com/STMicroelectronics/cmsis_device_l1.git 7f16ec0a1c4c063f84160b4cc6bf88ad554a823e stm32l1
|
||||
hw/mcu/st/cmsis_device_l4 https://github.com/STMicroelectronics/cmsis_device_l4.git 6ca7312fa6a5a460b5a5a63d66da527fdd8359a6 stm32l4
|
||||
hw/mcu/st/cmsis_device_l5 https://github.com/STMicroelectronics/cmsis_device_l5.git d922865fc0326a102c26211c44b8e42f52c1e53d stm32l5
|
||||
hw/mcu/st/cmsis_device_n6 https://github.com/STMicroelectronics/cmsis-device-n6.git f818b00f775444e8d19ef6cad822534c345e054f stm32n6
|
||||
hw/mcu/st/cmsis_device_u5 https://github.com/STMicroelectronics/cmsis_device_u5.git 5ad9797c54ec3e55eff770fc9b3cd4a1aefc1309 stm32u5
|
||||
hw/mcu/st/cmsis_device_wb https://github.com/STMicroelectronics/cmsis_device_wb.git 9c5d1920dd9fabbe2548e10561d63db829bb744f stm32wb
|
||||
hw/mcu/st/cmsis_device_wb https://github.com/STMicroelectronics/cmsis_device_wb.git d6a7fa2e7de084f5e5e47f2ab88b022fe9b50e5a stm32wb
|
||||
hw/mcu/st/stm32-mfxstm32l152 https://github.com/STMicroelectronics/stm32-mfxstm32l152.git 7f4389efee9c6a655b55e5df3fceef5586b35f9b stm32h7
|
||||
hw/mcu/st/stm32c0xx_hal_driver https://github.com/STMicroelectronics/stm32c0xx_hal_driver.git 41253e2f1d7ae4a4d0c379cf63f5bcf71fcf8eb3 stm32c0
|
||||
hw/mcu/st/stm32f0xx_hal_driver https://github.com/STMicroelectronics/stm32f0xx_hal_driver.git 0e95cd88657030f640a11e690a8a5186c7712ea5 stm32f0
|
||||
@@ -53,12 +54,13 @@ hw/mcu/st/stm32f7xx_hal_driver https://github.com/STMicroelectronics/
|
||||
hw/mcu/st/stm32g0xx_hal_driver https://github.com/STMicroelectronics/stm32g0xx_hal_driver.git e911b12c7f67084d7f6b76157a4c0d4e2ec3779c stm32g0
|
||||
hw/mcu/st/stm32g4xx_hal_driver https://github.com/STMicroelectronics/stm32g4xx_hal_driver.git 8b4518417706d42eef5c14e56a650005abf478a8 stm32g4
|
||||
hw/mcu/st/stm32h5xx_hal_driver https://github.com/STMicroelectronics/stm32h5xx_hal_driver.git 2cf77de584196d619cec1b4586c3b9e2820a254e stm32h5
|
||||
hw/mcu/st/stm32h7rsxx_hal_driver https://github.com/STMicroelectronics/stm32h7rsxx-hal-driver.git 7ca2e07ca21bc66b53654e845b4c85c884343b60 stm32h7rs
|
||||
hw/mcu/st/stm32h7xx_hal_driver https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git d8461b980b59b1625207d8c4f2ce0a9c2a7a3b04 stm32h7
|
||||
hw/mcu/st/stm32h7rsxx_hal_driver https://github.com/STMicroelectronics/stm32h7rsxx_hal_driver.git 7ca2e07ca21bc66b53654e845b4c85c884343b60 stm32h7rs
|
||||
hw/mcu/st/stm32l0xx_hal_driver https://github.com/STMicroelectronics/stm32l0xx_hal_driver.git fbdacaf6f8c82a4e1eb9bd74ba650b491e97e17b stm32l0
|
||||
hw/mcu/st/stm32l1xx_hal_driver https://github.com/STMicroelectronics/stm32l1xx_hal_driver.git 44efc446fa69ed8344e7fd966e68ed11043b35d9 stm32l1
|
||||
hw/mcu/st/stm32l4xx_hal_driver https://github.com/STMicroelectronics/stm32l4xx_hal_driver.git aee3d5bf283ae5df87532b781bdd01b7caf256fc stm32l4
|
||||
hw/mcu/st/stm32l5xx_hal_driver https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git 675c32a75df37f39d50d61f51cb0dcf53f07e1cb stm32l5
|
||||
hw/mcu/st/stm32n6xx_hal_driver https://github.com/STMicroelectronics/stm32n6xx-hal-driver.git 49f9989d10cf6817d4b07ac01848956b46bd0fd6 stm32n6
|
||||
hw/mcu/st/stm32u5xx_hal_driver https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git 4d93097a67928e9377e655ddd14622adc31b9770 stm32u5
|
||||
hw/mcu/st/stm32wbxx_hal_driver https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git 2c5f06638be516c1b772f768456ba637f077bac8 stm32wb
|
||||
hw/mcu/ti https://github.com/hathach/ti_driver.git 143ed6cc20a7615d042b03b21e070197d473e6e5 msp430 msp432e4 tm4c
|
||||
@@ -66,10 +68,10 @@ hw/mcu/wch/ch32f20x https://github.com/openwch/ch32f20x.gi
|
||||
hw/mcu/wch/ch32v103 https://github.com/openwch/ch32v103.git 7578cae0b21f86dd053a1f781b2fc6ab99d0ec17 ch32v10x
|
||||
hw/mcu/wch/ch32v20x https://github.com/openwch/ch32v20x.git c4c38f507e258a4e69b059ccc2dc27dde33cea1b ch32v20x
|
||||
hw/mcu/wch/ch32v307 https://github.com/openwch/ch32v307.git 184f21b852cb95eed58e86e901837bc9fff68775 ch32v307
|
||||
lib/CMSIS_5 https://github.com/ARM-software/CMSIS_5.git 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf saml2x lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43 stm32c0 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5 stm32h7 stm32h7rs stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg tm4c
|
||||
lib/CMSIS_5 https://github.com/ARM-software/CMSIS_5.git 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf saml2x lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43 stm32c0 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5 stm32h7 stm32h7rs stm32l0 stm32l1 stm32l4 stm32l5 stm32n6 stm32u5 stm32wb sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg tm4c
|
||||
lib/CMSIS_6 https://github.com/ARM-software/CMSIS_6.git b0bbb0423b278ca632cfe1474eb227961d835fd2 ra
|
||||
lib/FreeRTOS-Kernel https://github.com/FreeRTOS/FreeRTOS-Kernel.git cc0e0707c0c748713485b870bb980852b210877f all
|
||||
lib/lwip https://github.com/lwip-tcpip/lwip.git 159e31b689577dbf69cf0683bbaffbd71fa5ee10 all
|
||||
lib/sct_neopixel https://github.com/gsteiert/sct_neopixel.git e73e04ca63495672d955f9268e003cffe168fcd8 lpc55
|
||||
tools/uf2 https://github.com/microsoft/uf2.git c594542b2faa01cc33a2b97c9fbebc38549df80a all
|
||||
======================================== ============================================================== ======================================== ====================================================================================================================================================================================================================================================================================================================================
|
||||
======================================== ================================================================ ======================================== ======================================================================================================================================================================================================================================================================================================================================================
|
||||
|
||||
26
examples/build_system/cmake/cpu/cortex-m55.cmake
Normal file
26
examples/build_system/cmake/cpu/cortex-m55.cmake
Normal file
@@ -0,0 +1,26 @@
|
||||
if (TOOLCHAIN STREQUAL "gcc")
|
||||
set(TOOLCHAIN_COMMON_FLAGS
|
||||
-mthumb
|
||||
-mcpu=cortex-m55
|
||||
-mfloat-abi=hard
|
||||
-mfpu=fpv5-d16
|
||||
-mcmse
|
||||
)
|
||||
set(FREERTOS_PORT GCC_ARM_CM55_NTZ_NONSECURE CACHE INTERNAL "")
|
||||
|
||||
elseif (TOOLCHAIN STREQUAL "clang")
|
||||
set(TOOLCHAIN_COMMON_FLAGS
|
||||
--target=arm-none-eabi
|
||||
-mcpu=cortex-m55
|
||||
-mfpu=fpv5-d16
|
||||
)
|
||||
set(FREERTOS_PORT GCC_ARM_CM55_NTZ_NONSECURE CACHE INTERNAL "")
|
||||
|
||||
elseif (TOOLCHAIN STREQUAL "iar")
|
||||
set(TOOLCHAIN_COMMON_FLAGS
|
||||
--cpu cortex-m55
|
||||
--fpu VFPv5_D16
|
||||
)
|
||||
set(FREERTOS_PORT IAR_ARM_CM55_NTZ_NONSECURE CACHE INTERNAL "")
|
||||
|
||||
endif ()
|
||||
28
examples/build_system/make/cpu/cortex-m55.mk
Normal file
28
examples/build_system/make/cpu/cortex-m55.mk
Normal file
@@ -0,0 +1,28 @@
|
||||
ifeq ($(TOOLCHAIN),gcc)
|
||||
CFLAGS += \
|
||||
-mthumb \
|
||||
-mcpu=cortex-m55 \
|
||||
-mfloat-abi=hard \
|
||||
-mfpu=fpv5-d16 \
|
||||
-mcmse
|
||||
|
||||
else ifeq ($(TOOLCHAIN),clang)
|
||||
CFLAGS += \
|
||||
--target=arm-none-eabi \
|
||||
-mcpu=cortex-m55 \
|
||||
-mfpu=fpv5-d16 \
|
||||
|
||||
else ifeq ($(TOOLCHAIN),iar)
|
||||
CFLAGS += \
|
||||
--cpu cortex-m55 \
|
||||
--fpu VFPv5_D16 \
|
||||
|
||||
ASFLAGS += \
|
||||
--cpu cortex-m55 \
|
||||
--fpu VFPv5_D16 \
|
||||
|
||||
else
|
||||
$(error "TOOLCHAIN is not supported")
|
||||
endif
|
||||
|
||||
FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM55_NTZ/non_secure
|
||||
@@ -11,6 +11,7 @@ mcu:STM32L0
|
||||
mcu:STM32F0
|
||||
mcu:KINETIS_KL
|
||||
mcu:STM32H7RS
|
||||
mcu:STM32N6
|
||||
family:broadcom_64bit
|
||||
family:broadcom_32bit
|
||||
family:espressif
|
||||
|
||||
@@ -16,3 +16,4 @@ mcu:STM32F4
|
||||
mcu:STM32F7
|
||||
mcu:STM32H7
|
||||
mcu:STM32H7RS
|
||||
mcu:STM32N6
|
||||
|
||||
@@ -16,3 +16,4 @@ mcu:STM32F4
|
||||
mcu:STM32F7
|
||||
mcu:STM32H7
|
||||
mcu:STM32H7RS
|
||||
mcu:STM32N6
|
||||
|
||||
@@ -14,3 +14,4 @@ mcu:STM32F4
|
||||
mcu:STM32F7
|
||||
mcu:STM32H7
|
||||
mcu:STM32H7RS
|
||||
mcu:STM32N6
|
||||
|
||||
@@ -19,3 +19,4 @@ mcu:STM32F4
|
||||
mcu:STM32F7
|
||||
mcu:STM32H7
|
||||
mcu:STM32H7RS
|
||||
mcu:STM32N6
|
||||
|
||||
@@ -16,3 +16,4 @@ mcu:STM32F4
|
||||
mcu:STM32F7
|
||||
mcu:STM32H7
|
||||
mcu:STM32H7RS
|
||||
mcu:STM32N6
|
||||
|
||||
@@ -19,3 +19,4 @@ mcu:STM32F4
|
||||
mcu:STM32F7
|
||||
mcu:STM32H7
|
||||
mcu:STM32H7RS
|
||||
mcu:STM32N6
|
||||
|
||||
@@ -16,3 +16,4 @@ mcu:STM32F4
|
||||
mcu:STM32F7
|
||||
mcu:STM32H7
|
||||
mcu:STM32H7RS
|
||||
mcu:STM32N6
|
||||
|
||||
@@ -26,7 +26,7 @@
|
||||
|
||||
/* metadata:
|
||||
name: MAX32650 EVKIT
|
||||
url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650-evkit.html#eb-overview
|
||||
url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650-evkit.html
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H_
|
||||
|
||||
@@ -6,19 +6,14 @@ set(LD_FILE_Clang ${LD_FILE_GNU})
|
||||
set(LD_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/stm32h7s3xx_flash.icf)
|
||||
|
||||
function(update_board TARGET)
|
||||
|
||||
target_compile_definitions(${TARGET} PUBLIC
|
||||
STM32H7S3xx
|
||||
SEGGER_RTT_SECTION="noncacheable_buffer"
|
||||
BUFFER_SIZE_UP=0x3000
|
||||
)
|
||||
|
||||
target_sources(${TARGET} PUBLIC
|
||||
# BSP
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tcpp0203/tcpp0203.c
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tcpp0203/tcpp0203_reg.c
|
||||
${ST_TCPP0203}/tcpp0203.c
|
||||
${ST_TCPP0203}/tcpp0203_reg.c
|
||||
)
|
||||
target_include_directories(${TARGET} PUBLIC
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tcpp0203
|
||||
${ST_TCPP0203}
|
||||
)
|
||||
endfunction()
|
||||
|
||||
@@ -25,8 +25,8 @@
|
||||
*/
|
||||
|
||||
/* metadata:
|
||||
name: STM32 H723 Nucleo
|
||||
url: https://www.st.com/en/evaluation-tools/nucleo-h723zg.html
|
||||
name: STM32 H7S3L8 Nucleo
|
||||
url: https://www.st.com/en/evaluation-tools/nucleo-h7s3l8.html
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H_
|
||||
|
||||
@@ -12,12 +12,8 @@ LD_FILE_GCC = $(BOARD_PATH)/stm32h7s3xx_flash.ld
|
||||
LD_FILE_IAR = $(BOARD_PATH)/stm32h7s3xx_flash.icf
|
||||
|
||||
SRC_C += \
|
||||
$(BOARD_PATH)/tcpp0203/tcpp0203.c \
|
||||
$(BOARD_PATH)/tcpp0203/tcpp0203_reg.c \
|
||||
$(ST_TCPP0203)/tcpp0203.c \
|
||||
$(ST_TCPP0203)/tcpp0203_reg.c \
|
||||
|
||||
INC += \
|
||||
$(TOP)/$(BOARD_PATH)/tcpp0203 \
|
||||
|
||||
CFLAGS += \
|
||||
-DSEGGER_RTT_SECTION=\"noncacheable_buffer\" \
|
||||
-DBUFFER_SIZE_UP=0x3000 \
|
||||
$(TOP)/$(ST_TCPP0203) \
|
||||
|
||||
@@ -1,6 +0,0 @@
|
||||
This software component is provided to you as part of a software package and
|
||||
applicable license terms are in the Package_license file. If you received this
|
||||
software component outside of a package or without applicable license terms,
|
||||
the terms of the BSD-3-Clause license shall apply.
|
||||
You may obtain a copy of the BSD-3-Clause at:
|
||||
https://opensource.org/licenses/BSD-3-Clause
|
||||
@@ -1,205 +0,0 @@
|
||||
<!DOCTYPE html>
|
||||
<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
|
||||
<head>
|
||||
<meta charset="utf-8" />
|
||||
<meta name="generator" content="pandoc" />
|
||||
<meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
|
||||
<title>Release Notes for TCPP0203 Component Driver</title>
|
||||
<style type="text/css">
|
||||
code{white-space: pre-wrap;}
|
||||
span.smallcaps{font-variant: small-caps;}
|
||||
span.underline{text-decoration: underline;}
|
||||
div.column{display: inline-block; vertical-align: top; width: 50%;}
|
||||
</style>
|
||||
<link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
|
||||
<!--[if lt IE 9]>
|
||||
<script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
|
||||
<![endif]-->
|
||||
<link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
|
||||
</head>
|
||||
<body>
|
||||
<div class="row">
|
||||
<div class="col-sm-12 col-lg-4">
|
||||
<center>
|
||||
<h1 id="release-notes-for-tcpp0203-component-driver">Release Notes for TCPP0203 Component Driver</h1>
|
||||
<p>Copyright © 2020 STMicroelectronics<br />
|
||||
</p>
|
||||
<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
|
||||
</center>
|
||||
<h1 id="purpose">Purpose</h1>
|
||||
<p>This driver provides a set of functions needed to drive TCPP0203 Type-C Port Protection component</p>
|
||||
</div>
|
||||
<div class="col-sm-12 col-lg-8">
|
||||
<h1 id="update-history">Update History</h1>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section6" checked aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">v1.2.3 / 21-Jan-2023</label>
|
||||
<div>
|
||||
<h2 id="main-changes">Main Changes</h2>
|
||||
<h3 id="maintenance-release">Maintenance release</h3>
|
||||
<h2 id="contents">Contents</h2>
|
||||
<table>
|
||||
<thead>
|
||||
<tr class="header">
|
||||
<th>Headline</th>
|
||||
</tr>
|
||||
</thead>
|
||||
<tbody>
|
||||
<tr class="odd">
|
||||
<td>MISRA Rule-81.13 correction on TCPP0203 component driver files</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<h2 id="backward-compatibility">Backward compatibility</h2>
|
||||
<p>No compatibility break with previous version</p>
|
||||
<h2 id="dependencies">Dependencies</h2>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">v1.2.2 / 21-Jan-2022</label>
|
||||
<div>
|
||||
<h2 id="main-changes-1">Main Changes</h2>
|
||||
<h3 id="maintenance-release-1">Maintenance release</h3>
|
||||
<h2 id="contents-1">Contents</h2>
|
||||
<table>
|
||||
<caption>Fixed bugs list</caption>
|
||||
<thead>
|
||||
<tr class="header">
|
||||
<th>Headline</th>
|
||||
</tr>
|
||||
</thead>
|
||||
<tbody>
|
||||
<tr class="odd">
|
||||
<td>MISRA corrections on TCPP0203 component driver files</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<h2 id="known-limitations">Known Limitations</h2>
|
||||
<p>Outstanding bugs list : None</p>
|
||||
<p>Requirements not met or planned in a forthcoming release : None</p>
|
||||
<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
|
||||
<ul>
|
||||
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3</li>
|
||||
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1</li>
|
||||
<li>STM32CubeIDE toolchain V1.8.0</li>
|
||||
</ul>
|
||||
<h2 id="backward-compatibility-1">Backward compatibility</h2>
|
||||
<p>No compatibility break with previous version</p>
|
||||
<h2 id="dependencies-1">Dependencies</h2>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">v1.2.1 / 18-June-2021</label>
|
||||
<div>
|
||||
<h2 id="main-changes-2">Main Changes</h2>
|
||||
<h3 id="maintenance-release-2">Maintenance release</h3>
|
||||
<h2 id="contents-2">Contents</h2>
|
||||
<table>
|
||||
<caption>Fixed bugs list</caption>
|
||||
<thead>
|
||||
<tr class="header">
|
||||
<th>Headline</th>
|
||||
</tr>
|
||||
</thead>
|
||||
<tbody>
|
||||
<tr class="odd">
|
||||
<td>License updates</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<h2 id="known-limitations-1">Known Limitations</h2>
|
||||
<p>Outstanding bugs list : None</p>
|
||||
<p>Requirements not met or planned in a forthcoming release : None</p>
|
||||
<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
|
||||
<ul>
|
||||
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3</li>
|
||||
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1</li>
|
||||
<li>STM32CubeIDE toolchain V1.6.0</li>
|
||||
</ul>
|
||||
<h2 id="backward-compatibility-2">Backward compatibility</h2>
|
||||
<p>No compatibility break with previous version</p>
|
||||
<h2 id="dependencies-2">Dependencies</h2>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">v1.2.0 / 06-Apr-2021</label>
|
||||
<div>
|
||||
<h2 id="main-changes-3">Main Changes</h2>
|
||||
<h3 id="maintenance-release-3">Maintenance release</h3>
|
||||
<h2 id="contents-3">Contents</h2>
|
||||
<table>
|
||||
<caption>Fixed bugs list</caption>
|
||||
<thead>
|
||||
<tr class="header">
|
||||
<th>Headline</th>
|
||||
</tr>
|
||||
</thead>
|
||||
<tbody>
|
||||
<tr class="odd">
|
||||
<td>CodeSpell correction on TCPP0203 component driver files</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<h2 id="known-limitations-2">Known Limitations</h2>
|
||||
<p>Outstanding bugs list : None</p>
|
||||
<p>Requirements not met or planned in a forthcoming release : None</p>
|
||||
<h2 id="development-toolchains-and-compilers-2">Development Toolchains and Compilers</h2>
|
||||
<ul>
|
||||
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3</li>
|
||||
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1</li>
|
||||
<li>STM32CubeIDE toolchain V1.5.0</li>
|
||||
</ul>
|
||||
<h2 id="backward-compatibility-3">Backward compatibility</h2>
|
||||
<p>No compatibility break with previous version</p>
|
||||
<h2 id="dependencies-3">Dependencies</h2>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">v1.1.0 / 12-Mar-2021</label>
|
||||
<div>
|
||||
<h2 id="main-changes-4">Main Changes</h2>
|
||||
<h3 id="maintenance-release-4">Maintenance release</h3>
|
||||
<h2 id="contents-4">Contents</h2>
|
||||
<table>
|
||||
<caption>Fixed bugs list</caption>
|
||||
<thead>
|
||||
<tr class="header">
|
||||
<th>Headline</th>
|
||||
</tr>
|
||||
</thead>
|
||||
<tbody>
|
||||
<tr class="odd">
|
||||
<td>MCUAstyle correction on TCPP0203 component driver files</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<h2 id="known-limitations-3">Known Limitations</h2>
|
||||
<p>Outstanding bugs list : None</p>
|
||||
<p>Requirements not met or planned in a forthcoming release : None</p>
|
||||
<h2 id="development-toolchains-and-compilers-3">Development Toolchains and Compilers</h2>
|
||||
<ul>
|
||||
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3</li>
|
||||
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1</li>
|
||||
<li>STM32CubeIDE toolchain V1.5.0</li>
|
||||
</ul>
|
||||
<h2 id="backward-compatibility-4">Backward compatibility</h2>
|
||||
<p>No compatibility break with previous version</p>
|
||||
<h2 id="dependencies-4">Dependencies</h2>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">v1.0.0 / 20-May-2020</label>
|
||||
<div>
|
||||
<h2 id="main-changes-5">Main Changes</h2>
|
||||
<ul>
|
||||
<li>First official release of <strong>TCPP0203</strong> Type-C port Protection Component drivers</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<footer class="sticky">
|
||||
<p>For complete documentation on STM32,visit: [<a href="http://www.st.com">www.st.com/stm32</a>]</p>
|
||||
This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge.
|
||||
</footer>
|
||||
</body>
|
||||
</html>
|
||||
Binary file not shown.
|
Before Width: | Height: | Size: 4.0 KiB |
File diff suppressed because it is too large
Load Diff
Binary file not shown.
|
Before Width: | Height: | Size: 7.3 KiB |
@@ -1,886 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file tcpp0203.c
|
||||
* @author MCD Application Team
|
||||
* @brief This file provides the TCPP02/03 Type-C port protection driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "tcpp0203.h"
|
||||
|
||||
#if defined(_TRACE)
|
||||
#include "usbpd_core.h"
|
||||
#include "usbpd_trace.h"
|
||||
#include "string.h"
|
||||
#include "stdio.h"
|
||||
#endif /* _TRACE */
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TCPP0203
|
||||
* @brief This file provides a set of functions needed to drive the
|
||||
* TCPP02/03 Type-C port protection.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TCPP0203_Private_Constants Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Compilation option in order to enable/disable a concistency check performed
|
||||
after each I2C access into TCPP0203 registers : goal is to check that written value in Reg0
|
||||
is properly reflected into reg1 register content.
|
||||
To enable register consistency check, please uncomment below definition.
|
||||
To disable it, comment below line */
|
||||
/* #define TCPP0203_REGISTER_CONSISTENCY_CHECK */
|
||||
|
||||
/** @defgroup TCPP0203_Private_Types Private Types
|
||||
* @{
|
||||
*/
|
||||
/* TCPP02/03 Type-C port protection driver structure initialization */
|
||||
TCPP0203_Drv_t TCPP0203_Driver =
|
||||
{
|
||||
TCPP0203_Init,
|
||||
TCPP0203_DeInit,
|
||||
TCPP0203_Reset,
|
||||
TCPP0203_SetVConnSwitch,
|
||||
TCPP0203_SetGateDriverProvider,
|
||||
TCPP0203_SetGateDriverConsumer,
|
||||
TCPP0203_SetPowerMode,
|
||||
TCPP0203_SetVBusDischarge,
|
||||
TCPP0203_SetVConnDischarge,
|
||||
TCPP0203_GetVConnSwitchAck,
|
||||
TCPP0203_GetGateDriverProviderAck,
|
||||
TCPP0203_GetGateDriverConsumerAck,
|
||||
TCPP0203_GetPowerModeAck,
|
||||
TCPP0203_GetVBusDischargeAck,
|
||||
TCPP0203_GetVConnDischargeAck,
|
||||
TCPP0203_GetOCPVConnFlag,
|
||||
TCPP0203_GetOCPVBusFlag,
|
||||
TCPP0203_GetOVPVBusFlag,
|
||||
TCPP0203_GetOVPCCFlag,
|
||||
TCPP0203_GetOTPFlag,
|
||||
TCPP0203_GetVBusOkFlag,
|
||||
TCPP0203_ReadTCPPType,
|
||||
TCPP0203_ReadVCONNPower,
|
||||
TCPP0203_WriteCtrlRegister,
|
||||
TCPP0203_ReadAckRegister,
|
||||
TCPP0203_ReadFlagRegister,
|
||||
};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TCPP0203_Private_Variables Private Variables
|
||||
* @{
|
||||
*/
|
||||
static uint8_t TCPP0203_DeviceType = TCPP0203_DEVICE_TYPE_03;
|
||||
|
||||
#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK)
|
||||
static uint8_t Reg0_Expected_Value = 0x00;
|
||||
static uint8_t Reg1_LastRead_Value = 0x00;
|
||||
#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/** @defgroup TCPP0203_Private_Function_Prototypes TCPP0203 Private Function Prototypes
|
||||
* @{
|
||||
*/
|
||||
static int32_t TCPP0203_ReadRegWrap(const void *handle, uint8_t Reg, uint8_t *Data, uint8_t Length);
|
||||
static int32_t TCPP0203_WriteRegWrap(const void *handle, uint8_t Reg, uint8_t *Data, uint8_t Length);
|
||||
|
||||
static int32_t TCPP0203_ModifyReg0(TCPP0203_Object_t *pObj, uint8_t Value, uint8_t Mask);
|
||||
|
||||
#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK)
|
||||
static int32_t TCPP0203_CheckReg0Reg1(TCPP0203_Object_t *pObj, uint8_t Reg0ExpectedValue);
|
||||
#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TCPP0203_Exported_Functions TCPP0203 Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Register Bus Io to component
|
||||
* @param Component object pointer
|
||||
* @retval Status of execution
|
||||
*/
|
||||
int32_t TCPP0203_RegisterBusIO(TCPP0203_Object_t *pObj, TCPP0203_IO_t *pIO)
|
||||
{
|
||||
int32_t ret;
|
||||
|
||||
if (pObj == NULL)
|
||||
{
|
||||
ret = TCPP0203_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
pObj->IO.Init = pIO->Init;
|
||||
pObj->IO.DeInit = pIO->DeInit;
|
||||
pObj->IO.Address = pIO->Address;
|
||||
pObj->IO.WriteReg = pIO->WriteReg;
|
||||
pObj->IO.ReadReg = pIO->ReadReg;
|
||||
pObj->IO.GetTick = pIO->GetTick;
|
||||
|
||||
pObj->Ctx.ReadReg = TCPP0203_ReadRegWrap;
|
||||
pObj->Ctx.WriteReg = TCPP0203_WriteRegWrap;
|
||||
pObj->Ctx.handle = pObj;
|
||||
|
||||
if (pObj->IO.Init != NULL)
|
||||
{
|
||||
ret = pObj->IO.Init();
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = TCPP0203_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the TCPP0203 interface
|
||||
* @param pObj Pointer to component object
|
||||
* @retval Component status (TCPP0203_OK / TCPP0203_ERROR)
|
||||
*/
|
||||
int32_t TCPP0203_Init(TCPP0203_Object_t *pObj)
|
||||
{
|
||||
int32_t ret = 0;
|
||||
uint8_t tmp;
|
||||
|
||||
if (pObj->IsInitialized == 0U)
|
||||
{
|
||||
/* Read TCPP Device type */
|
||||
ret += tcpp0203_read_reg(&pObj->Ctx, TCPP0203_READ_REG2, &tmp, 1);
|
||||
|
||||
if (ret == TCPP0203_OK)
|
||||
{
|
||||
TCPP0203_DeviceType = (tmp & TCPP0203_DEVICE_TYPE_MSK);
|
||||
}
|
||||
else
|
||||
{
|
||||
TCPP0203_DeviceType = TCPP0203_DEVICE_TYPE_02;
|
||||
}
|
||||
pObj->IsInitialized = 1U;
|
||||
}
|
||||
|
||||
if (ret != TCPP0203_OK)
|
||||
{
|
||||
ret = TCPP0203_ERROR;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the TCPP0203 interface
|
||||
* @param pObj Pointer to component object
|
||||
* @retval Component status (TCPP0203_OK / TCPP0203_ERROR)
|
||||
*/
|
||||
int32_t TCPP0203_DeInit(TCPP0203_Object_t *pObj)
|
||||
{
|
||||
if (pObj->IsInitialized == 1U)
|
||||
{
|
||||
/* De-Initialize IO BUS layer */
|
||||
pObj->IO.DeInit();
|
||||
|
||||
pObj->IsInitialized = 0U;
|
||||
}
|
||||
|
||||
return TCPP0203_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resets TCPP0203 register (Reg0)
|
||||
* @param pObj Pointer to component object
|
||||
* @retval Component status (TCPP0203_OK / TCPP0203_ERROR)
|
||||
*/
|
||||
int32_t TCPP0203_Reset(TCPP0203_Object_t *pObj)
|
||||
{
|
||||
int32_t ret = TCPP0203_OK;
|
||||
uint8_t tmp = TCPP0203_REG0_RST_VALUE;
|
||||
|
||||
/* Write reset values in Reg0 register */
|
||||
if (tcpp0203_write_reg(&pObj->Ctx, TCPP0203_PROG_CTRL, &tmp, 1) != TCPP0203_OK)
|
||||
{
|
||||
ret = TCPP0203_ERROR;
|
||||
}
|
||||
|
||||
#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK)
|
||||
Reg0_Expected_Value = TCPP0203_REG0_RST_VALUE;
|
||||
Reg1_LastRead_Value = TCPP0203_REG0_RST_VALUE;
|
||||
#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure TCPP0203 VConn Switch
|
||||
* @param pObj Pointer to component object
|
||||
* @param VConnSwitch VConn Switch requested setting
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TCPP0203_VCONN_SWITCH_OPEN VConn switch open
|
||||
* @arg TCPP0203_VCONN_SWITCH_CC1 VConn closed on CC1
|
||||
* @arg TCPP0203_VCONN_SWITCH_CC2 VConn closed on CC2
|
||||
* @retval Component status
|
||||
*/
|
||||
int32_t TCPP0203_SetVConnSwitch(TCPP0203_Object_t *pObj, uint8_t VConnSwitch)
|
||||
{
|
||||
int32_t ret = TCPP0203_OK;
|
||||
|
||||
if ((VConnSwitch != TCPP0203_VCONN_SWITCH_OPEN)
|
||||
&& (VConnSwitch != TCPP0203_VCONN_SWITCH_CC1)
|
||||
&& (VConnSwitch != TCPP0203_VCONN_SWITCH_CC2))
|
||||
{
|
||||
ret = TCPP0203_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update VConn switch setting in Writing register Reg0 */
|
||||
ret += TCPP0203_ModifyReg0(pObj, VConnSwitch, TCPP0203_VCONN_SWITCH_MSK);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure TCPP0203 Gate Driver for Provider path
|
||||
* @param pObj Pointer to component object
|
||||
* @param GateDriverProvider GDP switch load requested setting
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TCPP0203_GD_PROVIDER_SWITCH_OPEN GDP Switch Load Open
|
||||
* @arg TCPP0203_GD_PROVIDER_SWITCH_CLOSED GDP Switch Load closed
|
||||
* @retval Component status
|
||||
*/
|
||||
int32_t TCPP0203_SetGateDriverProvider(TCPP0203_Object_t *pObj, uint8_t GateDriverProvider)
|
||||
{
|
||||
int32_t ret = TCPP0203_OK;
|
||||
|
||||
if ((GateDriverProvider != TCPP0203_GD_PROVIDER_SWITCH_OPEN)
|
||||
&& (GateDriverProvider != TCPP0203_GD_PROVIDER_SWITCH_CLOSED))
|
||||
{
|
||||
ret = TCPP0203_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update GDP Switch Load setting in Writing register Reg0 */
|
||||
if (GateDriverProvider == TCPP0203_GD_PROVIDER_SWITCH_CLOSED)
|
||||
{
|
||||
/* If Gate Driver Provider is to be closed, Gate Driver Consumer should be open */
|
||||
ret += TCPP0203_ModifyReg0(pObj, (GateDriverProvider | TCPP0203_GD_CONSUMER_SWITCH_OPEN),
|
||||
(TCPP0203_GD_PROVIDER_SWITCH_MSK | TCPP0203_GD_CONSUMER_SWITCH_MSK));
|
||||
}
|
||||
else
|
||||
{
|
||||
ret += TCPP0203_ModifyReg0(pObj, GateDriverProvider, TCPP0203_GD_PROVIDER_SWITCH_MSK);
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure TCPP0203 Gate Driver for Consumer path
|
||||
* @param pObj Pointer to component object
|
||||
* @param GateDriverConsumer GDC switch load requested setting
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TCPP0203_GD_CONSUMER_SWITCH_OPEN GDC Switch Load Open
|
||||
* @arg TCPP0203_GD_CONSUMER_SWITCH_CLOSED GDC Switch Load closed
|
||||
* @retval Component status
|
||||
*/
|
||||
int32_t TCPP0203_SetGateDriverConsumer(TCPP0203_Object_t *pObj, uint8_t GateDriverConsumer)
|
||||
{
|
||||
int32_t ret = TCPP0203_OK;
|
||||
|
||||
/* Check if TCPP type is TCPP03. Otherwise, return error */
|
||||
if (TCPP0203_DeviceType != TCPP0203_DEVICE_TYPE_03)
|
||||
{
|
||||
return (TCPP0203_ERROR);
|
||||
}
|
||||
|
||||
if ((GateDriverConsumer != TCPP0203_GD_CONSUMER_SWITCH_OPEN)
|
||||
&& (GateDriverConsumer != TCPP0203_GD_CONSUMER_SWITCH_CLOSED))
|
||||
{
|
||||
ret = TCPP0203_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update GDC Switch Load setting in Writing register Reg0 */
|
||||
if (GateDriverConsumer == TCPP0203_GD_CONSUMER_SWITCH_CLOSED)
|
||||
{
|
||||
/* If Gate Driver Consumer is to be closed, Gate Driver Provider should be open */
|
||||
ret += TCPP0203_ModifyReg0(pObj, (GateDriverConsumer | TCPP0203_GD_PROVIDER_SWITCH_OPEN),
|
||||
(TCPP0203_GD_PROVIDER_SWITCH_MSK | TCPP0203_GD_CONSUMER_SWITCH_MSK));
|
||||
}
|
||||
else
|
||||
{
|
||||
ret += TCPP0203_ModifyReg0(pObj, GateDriverConsumer, TCPP0203_GD_CONSUMER_SWITCH_MSK);
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure TCPP0203 Power Mode
|
||||
* @param pObj Pointer to component object
|
||||
* @param PowerMode Power mode requested setting
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TCPP0203_POWER_MODE_HIBERNATE Hibernate
|
||||
* @arg TCPP0203_POWER_MODE_LOWPOWER Low Power
|
||||
* @arg TCPP0203_POWER_MODE_NORMAL Normal
|
||||
* @retval Component status
|
||||
*/
|
||||
int32_t TCPP0203_SetPowerMode(TCPP0203_Object_t *pObj, uint8_t PowerMode)
|
||||
{
|
||||
int32_t ret = TCPP0203_OK;
|
||||
|
||||
if ((PowerMode != TCPP0203_POWER_MODE_HIBERNATE)
|
||||
&& (PowerMode != TCPP0203_POWER_MODE_LOWPOWER)
|
||||
&& (PowerMode != TCPP0203_POWER_MODE_NORMAL))
|
||||
{
|
||||
ret = TCPP0203_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update Power Mode setting in Writing register Reg0 */
|
||||
ret += TCPP0203_ModifyReg0(pObj, PowerMode, TCPP0203_POWER_MODE_MSK);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure TCPP0203 Gate Driver for Provider path
|
||||
* @param pObj Pointer to component object
|
||||
* @param VBusDischarge VBUS Discharge requested setting
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TCPP0203_VBUS_DISCHARGE_OFF VBUS Discharge Off
|
||||
* @arg TCPP0203_VBUS_DISCHARGE_ON VBUS Discharge On
|
||||
* @retval Component status
|
||||
*/
|
||||
int32_t TCPP0203_SetVBusDischarge(TCPP0203_Object_t *pObj, uint8_t VBusDischarge)
|
||||
{
|
||||
int32_t ret = TCPP0203_OK;
|
||||
|
||||
if ((VBusDischarge != TCPP0203_VBUS_DISCHARGE_OFF)
|
||||
&& (VBusDischarge != TCPP0203_VBUS_DISCHARGE_ON))
|
||||
{
|
||||
ret = TCPP0203_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update VBUS Discharge setting in Writing register Reg0 */
|
||||
ret += TCPP0203_ModifyReg0(pObj, VBusDischarge, TCPP0203_VBUS_DISCHARGE_MSK);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure TCPP0203 Gate Driver for Provider path
|
||||
* @param pObj Pointer to component object
|
||||
* @param VConnDischarge GDP switch load requested setting
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TCPP0203_VCONN_DISCHARGE_OFF VConn Discharge Off
|
||||
* @arg TCPP0203_VCONN_DISCHARGE_ON VConn Discharge On
|
||||
* @retval Component status
|
||||
*/
|
||||
int32_t TCPP0203_SetVConnDischarge(TCPP0203_Object_t *pObj, uint8_t VConnDischarge)
|
||||
{
|
||||
int32_t ret = TCPP0203_OK;
|
||||
|
||||
if ((VConnDischarge != TCPP0203_VCONN_DISCHARGE_OFF)
|
||||
&& (VConnDischarge != TCPP0203_VCONN_DISCHARGE_ON))
|
||||
{
|
||||
ret = TCPP0203_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update VConn Discharge setting in Writing register Reg0 */
|
||||
ret += TCPP0203_ModifyReg0(pObj, VConnDischarge, TCPP0203_VCONN_DISCHARGE_MSK);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get VConn switch Ack value
|
||||
* @param pObj Pointer to component object
|
||||
* @param pVConnSwitchAck Pointer on VConn switch Ack value
|
||||
* This output parameter can be one of the following values:
|
||||
* @arg TCPP0203_VCONN_SWITCH_OPEN VConn switch open Ack
|
||||
* @arg TCPP0203_VCONN_SWITCH_CC1 VConn closed on CC1 Ack
|
||||
* @arg TCPP0203_VCONN_SWITCH_CC2 VConn closed on CC2 Ack
|
||||
* @retval Component status
|
||||
*/
|
||||
int32_t TCPP0203_GetVConnSwitchAck(TCPP0203_Object_t *pObj, uint8_t *pVConnSwitchAck)
|
||||
{
|
||||
int32_t ret;
|
||||
uint8_t tmp;
|
||||
|
||||
ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1);
|
||||
*pVConnSwitchAck = (tmp & TCPP0203_VCONN_SWITCH_ACK_MSK);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Gate Driver Provider Ack value
|
||||
* @param pObj Pointer to component object
|
||||
* @param pGateDriverProviderAck Pointer on Gate Driver Provider Ack value
|
||||
* This output parameter can be one of the following values:
|
||||
* @arg TCPP0203_GD_PROVIDER_SWITCH_ACK_OPEN Gate Driver Provider Open Ack
|
||||
* @arg TCPP0203_GD_PROVIDER_SWITCH_ACK_CLOSED Gate Driver Provider Closed Ack
|
||||
* @retval Component status
|
||||
*/
|
||||
int32_t TCPP0203_GetGateDriverProviderAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverProviderAck)
|
||||
{
|
||||
int32_t ret;
|
||||
uint8_t tmp;
|
||||
|
||||
ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1);
|
||||
*pGateDriverProviderAck = (tmp & TCPP0203_GD_PROVIDER_SWITCH_ACK_MSK);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Gate Driver Consumer Ack value
|
||||
* @param pObj Pointer to component object
|
||||
* @param pGateDriverConsumerAck Pointer on Gate Driver Consumer Ack value
|
||||
* This output parameter can be one of the following values:
|
||||
* @arg TCPP0203_GD_CONSUMER_SWITCH_ACK_OPEN Gate Driver Consumer Open Ack
|
||||
* @arg TCPP0203_GD_CONSUMER_SWITCH_ACK_CLOSED Gate Driver Consumer Closed Ack
|
||||
* @retval Component status
|
||||
*/
|
||||
int32_t TCPP0203_GetGateDriverConsumerAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverConsumerAck)
|
||||
{
|
||||
int32_t ret;
|
||||
uint8_t tmp;
|
||||
|
||||
/* Check if TCPP type is TCPP03. Otherwise, return error */
|
||||
if (TCPP0203_DeviceType != TCPP0203_DEVICE_TYPE_03)
|
||||
{
|
||||
return (TCPP0203_ERROR);
|
||||
}
|
||||
|
||||
ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1);
|
||||
*pGateDriverConsumerAck = (tmp & TCPP0203_GD_CONSUMER_SWITCH_ACK_MSK);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Power Mode Ack value
|
||||
* @param pObj Pointer to component object
|
||||
* @param pPowerModeAck Pointer on Power Mode Ack value
|
||||
* This output parameter can be one of the following values:
|
||||
* @arg TCPP0203_POWER_MODE_ACK_HIBERNATE Power Mode Hibernate Ack
|
||||
* @arg TCPP0203_POWER_MODE_ACK_LOWPOWER Power Mode Low Power Ack
|
||||
* @arg TCPP0203_POWER_MODE_ACK_NORMAL Power Mode Normal Ack
|
||||
* @retval Component status
|
||||
*/
|
||||
int32_t TCPP0203_GetPowerModeAck(TCPP0203_Object_t *pObj, uint8_t *pPowerModeAck)
|
||||
{
|
||||
int32_t ret;
|
||||
uint8_t tmp;
|
||||
|
||||
ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1);
|
||||
*pPowerModeAck = (tmp & TCPP0203_POWER_MODE_ACK_MSK);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get VBUS Discharge Ack value
|
||||
* @param pObj Pointer to component object
|
||||
* @param pVBusDischargeAck Pointer on VBUS Discharge Ack value
|
||||
* This output parameter can be one of the following values:
|
||||
* @arg TCPP0203_VBUS_DISCHARGE_ACK_OFF VBUS Discharge Off Ack
|
||||
* @arg TCPP0203_VBUS_DISCHARGE_ACK_ON VBUS Discharge On Ack
|
||||
* @retval Component status
|
||||
*/
|
||||
int32_t TCPP0203_GetVBusDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVBusDischargeAck)
|
||||
{
|
||||
int32_t ret;
|
||||
uint8_t tmp;
|
||||
|
||||
ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1);
|
||||
*pVBusDischargeAck = (tmp & TCPP0203_VBUS_DISCHARGE_ACK_MSK);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get VConn Discharge Ack value
|
||||
* @param pObj Pointer to component object
|
||||
* @param pVConnDischargeAck Pointer on VConn Discharge Ack value
|
||||
* This output parameter can be one of the following values:
|
||||
* @arg TCPP0203_VCONN_DISCHARGE_ACK_OFF VConn Discharge Off Ack
|
||||
* @arg TCPP0203_VCONN_DISCHARGE_ACK_ON VConn Discharge On Ack
|
||||
* @retval Component status
|
||||
*/
|
||||
int32_t TCPP0203_GetVConnDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVConnDischargeAck)
|
||||
{
|
||||
int32_t ret;
|
||||
uint8_t tmp;
|
||||
|
||||
ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1);
|
||||
*pVConnDischargeAck = (tmp & TCPP0203_VCONN_DISCHARGE_ACK_MSK);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get OCP VConn Flag value
|
||||
* @param pObj Pointer to component object
|
||||
* @param pOCPVConnFlag Pointer on OCP VConn Flag value
|
||||
* This output parameter can be one of the following values:
|
||||
* @arg TCPP0203_FLAG_OCP_VCONN_RESET OCP VConn flag not set
|
||||
* @arg TCPP0203_FLAG_OCP_VCONN_SET OCP VConn flag set
|
||||
* @retval Component status
|
||||
*/
|
||||
int32_t TCPP0203_GetOCPVConnFlag(TCPP0203_Object_t *pObj, uint8_t *pOCPVConnFlag)
|
||||
{
|
||||
int32_t ret;
|
||||
uint8_t tmp;
|
||||
|
||||
ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1);
|
||||
*pOCPVConnFlag = (tmp & TCPP0203_FLAG_OCP_VCONN_MSK);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get OCP VBUS Flag value
|
||||
* @param pObj Pointer to component object
|
||||
* @param pGetOCPVBusFlag Pointer on OCP VBUS Flag value
|
||||
* This output parameter can be one of the following values:
|
||||
* @arg TCPP0203_FLAG_OCP_VBUS_RESET OCP VBUS flag not set
|
||||
* @arg TCPP0203_FLAG_OCP_VBUS_SET OCP VBUS flag set
|
||||
* @retval Component status
|
||||
*/
|
||||
int32_t TCPP0203_GetOCPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pGetOCPVBusFlag)
|
||||
{
|
||||
int32_t ret;
|
||||
uint8_t tmp;
|
||||
|
||||
ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1);
|
||||
*pGetOCPVBusFlag = (tmp & TCPP0203_FLAG_OCP_VBUS_MSK);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get OVP VBUS Flag value
|
||||
* @param pObj Pointer to component object
|
||||
* @param pOVPVBusFlag Pointer on OVP VBUS Flag value
|
||||
* This output parameter can be one of the following values:
|
||||
* @arg TCPP0203_FLAG_OVP_VBUS_RESET OVP VBUS flag not set
|
||||
* @arg TCPP0203_FLAG_OVP_VBUS_SET OVP VBUS flag set
|
||||
* @retval Component status
|
||||
*/
|
||||
int32_t TCPP0203_GetOVPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPVBusFlag)
|
||||
{
|
||||
int32_t ret;
|
||||
uint8_t tmp;
|
||||
|
||||
ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1);
|
||||
*pOVPVBusFlag = (tmp & TCPP0203_FLAG_OVP_VBUS_MSK);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get OVP CC Flag value
|
||||
* @param pObj Pointer to component object
|
||||
* @param pOVPCCFlag Pointer on OVP CC Flag value
|
||||
* This output parameter can be one of the following values:
|
||||
* @arg TCPP0203_FLAG_OVP_CC_RESET OVP CC flag not set
|
||||
* @arg TCPP0203_FLAG_OVP_CC_SET OVP CC flag set
|
||||
* @retval Component status
|
||||
*/
|
||||
int32_t TCPP0203_GetOVPCCFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPCCFlag)
|
||||
{
|
||||
int32_t ret;
|
||||
uint8_t tmp;
|
||||
|
||||
ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1);
|
||||
*pOVPCCFlag = (tmp & TCPP0203_FLAG_OVP_CC_MSK);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Over Temperature Flag value
|
||||
* @param pObj Pointer to component object
|
||||
* @param pOTPFlag Pointer on Over Temperature Flag value
|
||||
* This output parameter can be one of the following values:
|
||||
* @arg TCPP0203_FLAG_OTP_RESET Over Temperature flag not set
|
||||
* @arg TCPP0203_FLAG_OTP_SET Over Temperature flag set
|
||||
* @retval Component status
|
||||
*/
|
||||
int32_t TCPP0203_GetOTPFlag(TCPP0203_Object_t *pObj, uint8_t *pOTPFlag)
|
||||
{
|
||||
int32_t ret;
|
||||
uint8_t tmp;
|
||||
|
||||
ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1);
|
||||
*pOTPFlag = (tmp & TCPP0203_FLAG_OTP_MSK);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get VBUS OK Flag value
|
||||
* @param pObj Pointer to component object
|
||||
* @param pVBusOkFlag Pointer on VBUS OK Flag value
|
||||
* This output parameter can be one of the following values:
|
||||
* @arg TCPP0203_FLAG_VBUS_OK_RESET VBUS OK flag not set
|
||||
* @arg TCPP0203_FLAG_VBUS_OK_SET VBUS OK flag set
|
||||
* @retval Component status
|
||||
*/
|
||||
int32_t TCPP0203_GetVBusOkFlag(TCPP0203_Object_t *pObj, uint8_t *pVBusOkFlag)
|
||||
{
|
||||
int32_t ret;
|
||||
uint8_t tmp;
|
||||
|
||||
ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1);
|
||||
*pVBusOkFlag = (tmp & TCPP0203_FLAG_VBUS_OK_MSK);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get TCPP0203 Device Type value
|
||||
* @param pObj Pointer to component object
|
||||
* @param pTCPPType Pointer on TCPP0203 Device Type value
|
||||
* This output parameter can be one of the following values:
|
||||
* @arg TCPP0203_DEVICE_TYPE_02 TCPP02 Type
|
||||
* @arg TCPP0203_DEVICE_TYPE_03 TCPP03 Type
|
||||
* @retval Component status
|
||||
*/
|
||||
int32_t TCPP0203_ReadTCPPType(TCPP0203_Object_t *pObj, uint8_t *pTCPPType)
|
||||
{
|
||||
int32_t ret;
|
||||
uint8_t tmp;
|
||||
|
||||
ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1);
|
||||
*pTCPPType = (tmp & TCPP0203_DEVICE_TYPE_MSK);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get VConn Power value
|
||||
* @param pObj Pointer to component object
|
||||
* @param pVCONNPower Pointer on VConn Power value
|
||||
* This output parameter can be one of the following values:
|
||||
* @arg TCPP0203_FLAG_VCONN_PWR_1W OCP VConn flag not set
|
||||
* @arg TCPP0203_FLAG_VCONN_PWR_0_1W OCP VConn flag set
|
||||
* @retval Component status
|
||||
*/
|
||||
int32_t TCPP0203_ReadVCONNPower(TCPP0203_Object_t *pObj, uint8_t *pVCONNPower)
|
||||
{
|
||||
int32_t ret;
|
||||
uint8_t tmp;
|
||||
|
||||
ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1);
|
||||
*pVCONNPower = (tmp & TCPP0203_FLAG_VCONN_PWR_MSK);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set complete Ctrl register value (Reg 0)
|
||||
* @param pObj Pointer to component object
|
||||
* @param pCtrlRegister Pointer on Ctrl register value
|
||||
* @retval Component status
|
||||
*/
|
||||
int32_t TCPP0203_WriteCtrlRegister(TCPP0203_Object_t *pObj, uint8_t *pCtrlRegister)
|
||||
{
|
||||
int32_t ret;
|
||||
|
||||
/* Update value in writing register (reg0) */
|
||||
ret = tcpp0203_write_reg(&pObj->Ctx, TCPP0203_PROG_CTRL, pCtrlRegister, 1);
|
||||
|
||||
#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK)
|
||||
Reg0_Expected_Value = *pCtrlRegister;
|
||||
#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get complete Ack register value
|
||||
* @param pObj Pointer to component object
|
||||
* @param pAckRegister Pointer on Ack register value
|
||||
* @retval Component status
|
||||
*/
|
||||
int32_t TCPP0203_ReadAckRegister(TCPP0203_Object_t *pObj, uint8_t *pAckRegister)
|
||||
{
|
||||
int32_t ret;
|
||||
|
||||
ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, pAckRegister, 1);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get complete Flag register value
|
||||
* @param pObj Pointer to component object
|
||||
* @param pFlagRegister Pointer on Flag register value
|
||||
* @retval Component status
|
||||
*/
|
||||
int32_t TCPP0203_ReadFlagRegister(TCPP0203_Object_t *pObj, uint8_t *pFlagRegister)
|
||||
{
|
||||
int32_t ret;
|
||||
|
||||
ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, pFlagRegister, 1);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/******************** Static functions ****************************************/
|
||||
/**
|
||||
* @brief Wrap TCPP0203 read function to Bus IO function
|
||||
* @param handle Component object handle
|
||||
* @param Reg Target register address to read
|
||||
* @param pData Buffer where Target register value should be stored
|
||||
* @param Length buffer size to be read
|
||||
* @retval error status
|
||||
*/
|
||||
static int32_t TCPP0203_ReadRegWrap(const void *handle, uint8_t Reg, uint8_t *pData, uint8_t Length)
|
||||
{
|
||||
const TCPP0203_Object_t *pObj = (const TCPP0203_Object_t *)handle;
|
||||
|
||||
return pObj->IO.ReadReg(pObj->IO.Address, Reg, pData, Length);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wrap TCPP0203 write function to Bus IO function
|
||||
* @param handle Component object handle
|
||||
* @param Reg Target register address to write
|
||||
* @param pData Target register value to be written
|
||||
* @param Length Buffer size to be written
|
||||
* @retval error status
|
||||
*/
|
||||
static int32_t TCPP0203_WriteRegWrap(const void *handle, uint8_t Reg, uint8_t *pData, uint8_t Length)
|
||||
{
|
||||
const TCPP0203_Object_t *pObj = (const TCPP0203_Object_t *)handle;
|
||||
|
||||
#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK)
|
||||
Reg0_Expected_Value = *pData;
|
||||
#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */
|
||||
|
||||
return pObj->IO.WriteReg(pObj->IO.Address, Reg, pData, Length);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief TCPP0203 register update function to Bus IO function
|
||||
* @param handle Component object handle
|
||||
* @param Reg Target register address to write
|
||||
* @param pData Target register value to be written
|
||||
* @param Length Buffer size to be written
|
||||
* @retval error status
|
||||
*/
|
||||
static int32_t TCPP0203_ModifyReg0(TCPP0203_Object_t *pObj, uint8_t Value, uint8_t Mask)
|
||||
{
|
||||
int32_t ret;
|
||||
uint8_t tmp;
|
||||
|
||||
/* Read current content of ACK register (reflects content of bits set to 1 in Writing register Reg0) */
|
||||
ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1);
|
||||
|
||||
/* Update only the area dedicated to Mask */
|
||||
tmp &= ~(Mask);
|
||||
tmp |= (Value & Mask);
|
||||
|
||||
#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK)
|
||||
Reg0_Expected_Value = tmp;
|
||||
#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */
|
||||
|
||||
/* Update value in writing register (reg0) */
|
||||
ret += tcpp0203_write_reg(&pObj->Ctx, TCPP0203_PROG_CTRL, &tmp, 1);
|
||||
|
||||
#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK)
|
||||
ret += TCPP0203_CheckReg0Reg1(pObj, Reg0_Expected_Value);
|
||||
#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK)
|
||||
/**
|
||||
* @brief TCPP0203 register control function between Reg0 and Reg1 value
|
||||
* @param handle Component object handle
|
||||
* @param Reg0ExpectedValue Value expected in Reg0 (built after all calls to write functions)
|
||||
* @retval error status
|
||||
*/
|
||||
static int32_t TCPP0203_CheckReg0Reg1(TCPP0203_Object_t *pObj, uint8_t Reg0ExpectedValue)
|
||||
{
|
||||
int32_t ret;
|
||||
|
||||
/* Read current content of ACK register (expected to reflect content of bits set to 1 in Writing register Reg0) */
|
||||
ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &Reg1_LastRead_Value, 1);
|
||||
|
||||
#ifdef _TRACE
|
||||
char str[12];
|
||||
sprintf(str, "Exp0_0x%02x", Reg0ExpectedValue);
|
||||
USBPD_TRACE_Add(USBPD_TRACE_DEBUG, 0U, 0U, (uint8_t *)str, sizeof(str) - 1U);
|
||||
sprintf(str, "Reg1_0x%02x", Reg1_LastRead_Value);
|
||||
USBPD_TRACE_Add(USBPD_TRACE_DEBUG, 0U, 0U, (uint8_t *)str, sizeof(str) - 1U);
|
||||
#endif /* _TRACE */
|
||||
|
||||
/* Control if Reg1 value is same as Reg0 expected one */
|
||||
if (Reg1_LastRead_Value != Reg0ExpectedValue)
|
||||
{
|
||||
while (1);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -1,353 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file tcpp0203.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains all the functions prototypes for the
|
||||
* tcpp0203.c driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef TCPP0203_H
|
||||
#define TCPP0203_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "tcpp0203_reg.h"
|
||||
#include <stddef.h>
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Component
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TCPP0203
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup TCPP0203_Exported_Types TCPP0203 Exported Types
|
||||
* @{
|
||||
*/
|
||||
typedef int32_t (*TCPP0203_Init_Func)(void);
|
||||
typedef int32_t (*TCPP0203_DeInit_Func)(void);
|
||||
typedef int32_t (*TCPP0203_GetTick_Func)(void);
|
||||
typedef int32_t (*TCPP0203_WriteReg_Func)(uint16_t, uint16_t, uint8_t *, uint16_t);
|
||||
typedef int32_t (*TCPP0203_ReadReg_Func)(uint16_t, uint16_t, uint8_t *, uint16_t);
|
||||
|
||||
typedef struct
|
||||
{
|
||||
TCPP0203_Init_Func Init;
|
||||
TCPP0203_DeInit_Func DeInit;
|
||||
uint16_t Address;
|
||||
TCPP0203_WriteReg_Func WriteReg;
|
||||
TCPP0203_ReadReg_Func ReadReg;
|
||||
TCPP0203_GetTick_Func GetTick;
|
||||
} TCPP0203_IO_t;
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
TCPP0203_IO_t IO;
|
||||
TCPP0203_ctx_t Ctx;
|
||||
uint8_t IsInitialized;
|
||||
} TCPP0203_Object_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
int32_t (*Init)(TCPP0203_Object_t *);
|
||||
int32_t (*DeInit)(TCPP0203_Object_t *);
|
||||
int32_t (*Reset)(TCPP0203_Object_t *);
|
||||
int32_t (*SetVConnSwitch)(TCPP0203_Object_t *, uint8_t);
|
||||
int32_t (*SetGateDriverProvider)(TCPP0203_Object_t *, uint8_t);
|
||||
int32_t (*SetGateDriverConsumer)(TCPP0203_Object_t *, uint8_t);
|
||||
int32_t (*SetPowerMode)(TCPP0203_Object_t *, uint8_t);
|
||||
int32_t (*SetVBusDischarge)(TCPP0203_Object_t *, uint8_t);
|
||||
int32_t (*SetVConnDischarge)(TCPP0203_Object_t *, uint8_t);
|
||||
int32_t (*GetVConnSwitchAck)(TCPP0203_Object_t *, uint8_t *);
|
||||
int32_t (*GetGateDriverProviderAck)(TCPP0203_Object_t *, uint8_t *);
|
||||
int32_t (*GetGateDriverConsumerAck)(TCPP0203_Object_t *, uint8_t *);
|
||||
int32_t (*GetPowerModeAck)(TCPP0203_Object_t *, uint8_t *);
|
||||
int32_t (*GetVBusDischargeAck)(TCPP0203_Object_t *, uint8_t *);
|
||||
int32_t (*GetVConnDischargeAck)(TCPP0203_Object_t *, uint8_t *);
|
||||
int32_t (*GetOCPVConnFlag)(TCPP0203_Object_t *, uint8_t *);
|
||||
int32_t (*GetOCPVBusFlag)(TCPP0203_Object_t *, uint8_t *);
|
||||
int32_t (*GetOVPVBusFlag)(TCPP0203_Object_t *, uint8_t *);
|
||||
int32_t (*GetOVPCCFlag)(TCPP0203_Object_t *, uint8_t *);
|
||||
int32_t (*GetOTPFlag)(TCPP0203_Object_t *, uint8_t *);
|
||||
int32_t (*GetVBusOkFlag)(TCPP0203_Object_t *, uint8_t *);
|
||||
int32_t (*ReadTCPPType)(TCPP0203_Object_t *, uint8_t *);
|
||||
int32_t (*ReadVCONNPower)(TCPP0203_Object_t *, uint8_t *);
|
||||
int32_t (*WriteCtrlRegister)(TCPP0203_Object_t *, uint8_t *);
|
||||
int32_t (*ReadAckRegister)(TCPP0203_Object_t *, uint8_t *);
|
||||
int32_t (*ReadFlagRegister)(TCPP0203_Object_t *, uint8_t *);
|
||||
} TCPP0203_Drv_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TCPP0203_Exported_Constants TCPP0203 Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief TCPP0203 Driver Response codes
|
||||
*/
|
||||
#define TCPP0203_OK (0)
|
||||
#define TCPP0203_ERROR (-1)
|
||||
|
||||
/**
|
||||
* @brief TCPP0203 possible I2C Addresses
|
||||
*/
|
||||
#define TCPP0203_I2C_ADDRESS_X68 (0x68U)
|
||||
#define TCPP0203_I2C_ADDRESS_X6A (0x6AU)
|
||||
|
||||
/**
|
||||
* @brief TCPP0203 Reg0 Reset Value
|
||||
*/
|
||||
#define TCPP0203_REG0_RST_VALUE TCPP0203_GD_CONSUMER_SWITCH_CLOSED
|
||||
|
||||
/**
|
||||
* @brief TCPP0203 VCONN Switch
|
||||
*/
|
||||
#define TCPP0203_VCONN_SWITCH_POS (0U)
|
||||
#define TCPP0203_VCONN_SWITCH_MSK (0x03U << TCPP0203_VCONN_SWITCH_POS)
|
||||
#define TCPP0203_VCONN_SWITCH_OPEN (0x00U)
|
||||
#define TCPP0203_VCONN_SWITCH_CC1 (0x01U << TCPP0203_VCONN_SWITCH_POS)
|
||||
#define TCPP0203_VCONN_SWITCH_CC2 (0x02U << TCPP0203_VCONN_SWITCH_POS)
|
||||
|
||||
/**
|
||||
* @brief TCPP0203 Gate Driver Provider values
|
||||
*/
|
||||
#define TCPP0203_GD_PROVIDER_SWITCH_POS (2U)
|
||||
#define TCPP0203_GD_PROVIDER_SWITCH_MSK (0x01U << TCPP0203_GD_PROVIDER_SWITCH_POS)
|
||||
#define TCPP0203_GD_PROVIDER_SWITCH_OPEN (0x00U)
|
||||
#define TCPP0203_GD_PROVIDER_SWITCH_CLOSED (TCPP0203_GD_PROVIDER_SWITCH_MSK)
|
||||
|
||||
/**
|
||||
* @brief TCPP0203 Gate Driver Consumer values
|
||||
*/
|
||||
#define TCPP0203_GD_CONSUMER_SWITCH_POS (3U)
|
||||
#define TCPP0203_GD_CONSUMER_SWITCH_MSK (0x01U << TCPP0203_GD_CONSUMER_SWITCH_POS)
|
||||
#define TCPP0203_GD_CONSUMER_SWITCH_CLOSED (0x00U)
|
||||
#define TCPP0203_GD_CONSUMER_SWITCH_OPEN (TCPP0203_GD_CONSUMER_SWITCH_MSK)
|
||||
|
||||
/**
|
||||
* @brief TCPP0203 Power Mode values
|
||||
*/
|
||||
#define TCPP0203_POWER_MODE_POS (4U)
|
||||
#define TCPP0203_POWER_MODE_MSK (0x03U << TCPP0203_POWER_MODE_POS)
|
||||
#define TCPP0203_POWER_MODE_HIBERNATE (0x00U)
|
||||
#define TCPP0203_POWER_MODE_LOWPOWER (0x02U << TCPP0203_POWER_MODE_POS)
|
||||
#define TCPP0203_POWER_MODE_NORMAL (0x01U << TCPP0203_POWER_MODE_POS)
|
||||
|
||||
/**
|
||||
* @brief TCPP0203 VBUS Discharge management
|
||||
*/
|
||||
#define TCPP0203_VBUS_DISCHARGE_POS (6U)
|
||||
#define TCPP0203_VBUS_DISCHARGE_MSK (0x01U << TCPP0203_VBUS_DISCHARGE_POS)
|
||||
#define TCPP0203_VBUS_DISCHARGE_OFF (0x00U)
|
||||
#define TCPP0203_VBUS_DISCHARGE_ON (TCPP0203_VBUS_DISCHARGE_MSK)
|
||||
|
||||
/**
|
||||
* @brief TCPP0203 VConn Discharge management
|
||||
*/
|
||||
#define TCPP0203_VCONN_DISCHARGE_POS (7U)
|
||||
#define TCPP0203_VCONN_DISCHARGE_MSK (0x01U << TCPP0203_VCONN_DISCHARGE_POS)
|
||||
#define TCPP0203_VCONN_DISCHARGE_OFF (0x00U)
|
||||
#define TCPP0203_VCONN_DISCHARGE_ON (TCPP0203_VCONN_DISCHARGE_MSK)
|
||||
|
||||
/**
|
||||
* @brief TCPP0203 VCONN Switch Acknowledge
|
||||
*/
|
||||
#define TCPP0203_VCONN_SWITCH_ACK_POS (0U)
|
||||
#define TCPP0203_VCONN_SWITCH_ACK_MSK (0x03U << TCPP0203_VCONN_SWITCH_ACK_POS)
|
||||
#define TCPP0203_VCONN_SWITCH_ACK_OPEN (0x00U)
|
||||
#define TCPP0203_VCONN_SWITCH_ACK_CC1 (0x02U << TCPP0203_VCONN_SWITCH_ACK_POS)
|
||||
#define TCPP0203_VCONN_SWITCH_ACK_CC2 (0x01U << TCPP0203_VCONN_SWITCH_ACK_POS)
|
||||
|
||||
/**
|
||||
* @brief TCPP0203 Gate Driver Provider Acknowledge
|
||||
*/
|
||||
#define TCPP0203_GD_PROVIDER_SWITCH_ACK_POS (2U)
|
||||
#define TCPP0203_GD_PROVIDER_SWITCH_ACK_MSK (0x01U << TCPP0203_GD_PROVIDER_SWITCH_ACK_POS)
|
||||
#define TCPP0203_GD_PROVIDER_SWITCH_ACK_OPEN (0x00U)
|
||||
#define TCPP0203_GD_PROVIDER_SWITCH_ACK_CLOSED (TCPP0203_GD_PROVIDER_SWITCH_ACK_MSK)
|
||||
|
||||
/**
|
||||
* @brief TCPP0203 Gate Driver Consumer Acknowledge
|
||||
*/
|
||||
#define TCPP0203_GD_CONSUMER_SWITCH_ACK_POS (3U)
|
||||
#define TCPP0203_GD_CONSUMER_SWITCH_ACK_MSK (0x01U << TCPP0203_GD_CONSUMER_SWITCH_ACK_POS)
|
||||
#define TCPP0203_GD_CONSUMER_SWITCH_ACK_CLOSED (0x00U)
|
||||
#define TCPP0203_GD_CONSUMER_SWITCH_ACK_OPEN (TCPP0203_GD_CONSUMER_SWITCH_ACK_MSK)
|
||||
|
||||
/**
|
||||
* @brief TCPP0203 Power Mode Acknowledge
|
||||
*/
|
||||
#define TCPP0203_POWER_MODE_ACK_POS (4U)
|
||||
#define TCPP0203_POWER_MODE_ACK_MSK (0x03U << TCPP0203_POWER_MODE_ACK_POS)
|
||||
#define TCPP0203_POWER_MODE_ACK_HIBERNATE (0x00U)
|
||||
#define TCPP0203_POWER_MODE_ACK_LOWPOWER (0x01U << TCPP0203_POWER_MODE_ACK_POS)
|
||||
#define TCPP0203_POWER_MODE_ACK_NORMAL (0x02U << TCPP0203_POWER_MODE_ACK_POS)
|
||||
|
||||
/**
|
||||
* @brief TCPP0203 VBUS Discharge Acknowledge
|
||||
*/
|
||||
#define TCPP0203_VBUS_DISCHARGE_ACK_POS (6U)
|
||||
#define TCPP0203_VBUS_DISCHARGE_ACK_MSK (0x01U << TCPP0203_VBUS_DISCHARGE_ACK_POS)
|
||||
#define TCPP0203_VBUS_DISCHARGE_ACK_OFF (0x00U)
|
||||
#define TCPP0203_VBUS_DISCHARGE_ACK_ON (TCPP0203_VBUS_DISCHARGE_ACK_MSK)
|
||||
|
||||
/**
|
||||
* @brief TCPP0203 VConn Discharge Acknowledge
|
||||
*/
|
||||
#define TCPP0203_VCONN_DISCHARGE_ACK_POS (7U)
|
||||
#define TCPP0203_VCONN_DISCHARGE_ACK_MSK (0x01U << TCPP0203_VCONN_DISCHARGE_ACK_POS)
|
||||
#define TCPP0203_VCONN_DISCHARGE_ACK_OFF (0x00U)
|
||||
#define TCPP0203_VCONN_DISCHARGE_ACK_ON (TCPP0203_VCONN_DISCHARGE_ACK_MSK)
|
||||
|
||||
/**
|
||||
* @brief TCPP0203 OCP Vconn Flag management
|
||||
*/
|
||||
#define TCPP0203_FLAG_OCP_VCONN_POS (0U)
|
||||
#define TCPP0203_FLAG_OCP_VCONN_MSK (0x01U << TCPP0203_FLAG_OCP_VCONN_POS)
|
||||
#define TCPP0203_FLAG_OCP_VCONN_SET (TCPP0203_FLAG_OCP_VCONN_MSK)
|
||||
#define TCPP0203_FLAG_OCP_VCONN_RESET (0x00U)
|
||||
|
||||
/**
|
||||
* @brief TCPP0203 OCP VBUS Flag management
|
||||
*/
|
||||
#define TCPP0203_FLAG_OCP_VBUS_POS (1U)
|
||||
#define TCPP0203_FLAG_OCP_VBUS_MSK (0x01U << TCPP0203_FLAG_OCP_VBUS_POS)
|
||||
#define TCPP0203_FLAG_OCP_VBUS_SET (TCPP0203_FLAG_OCP_VBUS_MSK)
|
||||
#define TCPP0203_FLAG_OCP_VBUS_RESET (0x00U)
|
||||
|
||||
/**
|
||||
* @brief TCPP0203 OVP VBUS Flag management
|
||||
*/
|
||||
#define TCPP0203_FLAG_OVP_VBUS_POS (2U)
|
||||
#define TCPP0203_FLAG_OVP_VBUS_MSK (0x01U << TCPP0203_FLAG_OVP_VBUS_POS)
|
||||
#define TCPP0203_FLAG_OVP_VBUS_SET (TCPP0203_FLAG_OVP_VBUS_MSK)
|
||||
#define TCPP0203_FLAG_OVP_VBUS_RESET (0x00U)
|
||||
|
||||
/**
|
||||
* @brief TCPP0203 OVP CC Flag management
|
||||
*/
|
||||
#define TCPP0203_FLAG_OVP_CC_POS (3U)
|
||||
#define TCPP0203_FLAG_OVP_CC_MSK (0x01U << TCPP0203_FLAG_OVP_CC_POS)
|
||||
#define TCPP0203_FLAG_OVP_CC_SET (TCPP0203_FLAG_OVP_CC_MSK)
|
||||
#define TCPP0203_FLAG_OVP_CC_RESET (0x00U)
|
||||
|
||||
/**
|
||||
* @brief TCPP0203 OTP Flag management
|
||||
*/
|
||||
#define TCPP0203_FLAG_OTP_POS (4U)
|
||||
#define TCPP0203_FLAG_OTP_MSK (0x01U << TCPP0203_FLAG_OTP_POS)
|
||||
#define TCPP0203_FLAG_OTP_SET (TCPP0203_FLAG_OTP_MSK)
|
||||
#define TCPP0203_FLAG_OTP_RESET (0x00U)
|
||||
|
||||
/**
|
||||
* @brief TCPP0203 VBUS OK Flag management
|
||||
*/
|
||||
#define TCPP0203_FLAG_VBUS_OK_POS (5U)
|
||||
#define TCPP0203_FLAG_VBUS_OK_MSK (0x01U << TCPP0203_FLAG_VBUS_OK_POS)
|
||||
#define TCPP0203_FLAG_VBUS_OK_SET (TCPP0203_FLAG_VBUS_OK_MSK)
|
||||
#define TCPP0203_FLAG_VBUS_OK_RESET (0x00U)
|
||||
|
||||
/**
|
||||
* @brief TCPP0203 VConn Power
|
||||
*/
|
||||
#define TCPP0203_FLAG_VCONN_PWR_POS (6U)
|
||||
#define TCPP0203_FLAG_VCONN_PWR_MSK (0x01U << TCPP0203_FLAG_VCONN_PWR_POS)
|
||||
#define TCPP0203_FLAG_VCONN_PWR_1W (TCPP0203_FLAG_VCONN_PWR_MSK)
|
||||
#define TCPP0203_FLAG_VCONN_PWR_0_1W (0x00U)
|
||||
|
||||
/**
|
||||
* @brief TCPP0203 Device Type
|
||||
*/
|
||||
#define TCPP0203_DEVICE_TYPE_POS (7U)
|
||||
#define TCPP0203_DEVICE_TYPE_MSK (0x01U << TCPP0203_DEVICE_TYPE_POS)
|
||||
#define TCPP0203_DEVICE_TYPE_02 (TCPP0203_DEVICE_TYPE_MSK)
|
||||
#define TCPP0203_DEVICE_TYPE_03 (0x00U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TCPP0203_Exported_Macros TCPP0203 Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TCPP0203_Exported_Functions TCPP0203 Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
TCPP02/03 Type-C port protection functions
|
||||
------------------------------------------------------------------------------*/
|
||||
/* High Layer codec functions */
|
||||
int32_t TCPP0203_RegisterBusIO(TCPP0203_Object_t *pObj, TCPP0203_IO_t *pIO);
|
||||
int32_t TCPP0203_Init(TCPP0203_Object_t *pObj);
|
||||
int32_t TCPP0203_DeInit(TCPP0203_Object_t *pObj);
|
||||
int32_t TCPP0203_Reset(TCPP0203_Object_t *pObj);
|
||||
int32_t TCPP0203_SetVConnSwitch(TCPP0203_Object_t *pObj, uint8_t VConnSwitch);
|
||||
int32_t TCPP0203_SetGateDriverProvider(TCPP0203_Object_t *pObj, uint8_t GateDriverProvider);
|
||||
int32_t TCPP0203_SetGateDriverConsumer(TCPP0203_Object_t *pObj, uint8_t GateDriverConsumer);
|
||||
int32_t TCPP0203_SetPowerMode(TCPP0203_Object_t *pObj, uint8_t PowerMode);
|
||||
int32_t TCPP0203_SetVBusDischarge(TCPP0203_Object_t *pObj, uint8_t VBusDischarge);
|
||||
int32_t TCPP0203_SetVConnDischarge(TCPP0203_Object_t *pObj, uint8_t VConnDischarge);
|
||||
int32_t TCPP0203_GetVConnSwitchAck(TCPP0203_Object_t *pObj, uint8_t *pVConnSwitchAck);
|
||||
int32_t TCPP0203_GetGateDriverProviderAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverProviderAck);
|
||||
int32_t TCPP0203_GetGateDriverConsumerAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverConsumerAck);
|
||||
int32_t TCPP0203_GetPowerModeAck(TCPP0203_Object_t *pObj, uint8_t *pPowerModeAck);
|
||||
int32_t TCPP0203_GetVBusDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVBusDischargeAck);
|
||||
int32_t TCPP0203_GetVConnDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVConnDischargeAck);
|
||||
int32_t TCPP0203_GetOCPVConnFlag(TCPP0203_Object_t *pObj, uint8_t *pOCPVConnFlag);
|
||||
int32_t TCPP0203_GetOCPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pGetOCPVBusFlag);
|
||||
int32_t TCPP0203_GetOVPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPVBusFlag);
|
||||
int32_t TCPP0203_GetOVPCCFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPCCFlag);
|
||||
int32_t TCPP0203_GetOTPFlag(TCPP0203_Object_t *pObj, uint8_t *pOTPFlag);
|
||||
int32_t TCPP0203_GetVBusOkFlag(TCPP0203_Object_t *pObj, uint8_t *pVBusOkFlag);
|
||||
int32_t TCPP0203_ReadTCPPType(TCPP0203_Object_t *pObj, uint8_t *pTCPPType);
|
||||
int32_t TCPP0203_ReadVCONNPower(TCPP0203_Object_t *pObj, uint8_t *pVCONNPower);
|
||||
int32_t TCPP0203_WriteCtrlRegister(TCPP0203_Object_t *pObj, uint8_t *pCtrlRegister);
|
||||
int32_t TCPP0203_ReadAckRegister(TCPP0203_Object_t *pObj, uint8_t *pAckRegister);
|
||||
int32_t TCPP0203_ReadFlagRegister(TCPP0203_Object_t *pObj, uint8_t *pFlagRegister);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* TCPP02/03 Type-C port protection driver structure */
|
||||
extern TCPP0203_Drv_t TCPP0203_Driver;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* TCPP0203_H */
|
||||
@@ -1,73 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file tcpp0203_reg.c
|
||||
* @author MCD Application Team
|
||||
* @brief This file provides unitary register function to control the TCPP02-03
|
||||
* Type-C port protection driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "tcpp0203_reg.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TCPP0203
|
||||
* @brief This file provides a set of functions needed to drive the
|
||||
* TCPP02/03 Type-C port protection codec.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/************** Generic Function *******************/
|
||||
/*******************************************************************************
|
||||
* Function Name : tcpp0203_read_reg
|
||||
* Description : Generic Reading function. It must be fulfilled with either
|
||||
* I2C or SPI reading functions
|
||||
* Input : Register Address, length of buffer
|
||||
* Output : data Read
|
||||
*******************************************************************************/
|
||||
int32_t tcpp0203_read_reg(const TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length)
|
||||
{
|
||||
return ctx->ReadReg(ctx->handle, reg, data, length);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : tcpp0203_write_reg
|
||||
* Description : Generic Writing function. It must be fulfilled with either
|
||||
* I2C or SPI writing function
|
||||
* Input : Register Address, data to be written, length of buffer
|
||||
* Output : None
|
||||
*******************************************************************************/
|
||||
int32_t tcpp0203_write_reg(const TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length)
|
||||
{
|
||||
return ctx->WriteReg(ctx->handle, reg, data, length);
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -1,98 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file tcpp0203_reg.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header of tcpp0203_reg.c
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef TCPP0203_REG_H
|
||||
#define TCPP0203_REG_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Component
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TCPP0203
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup TCPP0203_Exported_Constants TCPP0203 Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/****************************** REGISTER MAPPING ******************************/
|
||||
/******************************************************************************/
|
||||
#define TCPP0203_WRITE_REG 0x00U
|
||||
#define TCPP0203_PROG_CTRL TCPP0203_WRITE_REG
|
||||
#define TCPP0203_READ_REG1 0x01U
|
||||
#define TCPP0203_ACK_REG TCPP0203_READ_REG1
|
||||
#define TCPP0203_READ_REG2 0x02U
|
||||
#define TCPP0203_FLAG_REG TCPP0203_READ_REG2
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************** Generic Function *******************/
|
||||
|
||||
typedef int32_t (*TCPP0203_Write_Func)(const void *, uint8_t, uint8_t *, uint8_t);
|
||||
typedef int32_t (*TCPP0203_Read_Func)(const void *, uint8_t, uint8_t *, uint8_t);
|
||||
|
||||
typedef struct
|
||||
{
|
||||
TCPP0203_Write_Func WriteReg;
|
||||
TCPP0203_Read_Func ReadReg;
|
||||
void *handle;
|
||||
} TCPP0203_ctx_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Register : Generic - All
|
||||
* Address : Generic - All
|
||||
* Bit Group Name: None
|
||||
* Permission : W
|
||||
*******************************************************************************/
|
||||
int32_t tcpp0203_write_reg(const TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length);
|
||||
int32_t tcpp0203_read_reg(const TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* TCPP0203_REG_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -5,6 +5,7 @@ set(ST_PREFIX stm32${ST_FAMILY}xx)
|
||||
|
||||
set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
|
||||
set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
|
||||
set(ST_TCPP0203 ${TOP}/hw/mcu/st/stm32-tcpp0203)
|
||||
set(CMSIS_5 ${TOP}/lib/CMSIS_5)
|
||||
|
||||
# include board specific
|
||||
@@ -86,6 +87,8 @@ function(add_board_target BOARD_TARGET)
|
||||
BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
|
||||
BOARD_TUH_RHPORT=${RHPORT_HOST}
|
||||
BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
|
||||
SEGGER_RTT_SECTION="noncacheable_buffer"
|
||||
BUFFER_SIZE_UP=0x3000
|
||||
)
|
||||
|
||||
update_board(${BOARD_TARGET})
|
||||
|
||||
@@ -2,6 +2,7 @@ ST_FAMILY = h7rs
|
||||
ST_PREFIX = stm32${ST_FAMILY}xx
|
||||
ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
|
||||
ST_HAL_DRIVER = hw/mcu/st/${ST_PREFIX}_hal_driver
|
||||
ST_TCPP0203 = hw/mcu/st/stm32-tcpp0203
|
||||
|
||||
UF2_FAMILY_ID = 0x6db66083
|
||||
|
||||
@@ -42,6 +43,8 @@ CFLAGS += \
|
||||
-DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \
|
||||
-DBOARD_TUH_RHPORT=${RHPORT_HOST} \
|
||||
-DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \
|
||||
-DSEGGER_RTT_SECTION=\"noncacheable_buffer\" \
|
||||
-DBUFFER_SIZE_UP=0x3000 \
|
||||
|
||||
# GCC Flags
|
||||
CFLAGS_GCC += \
|
||||
|
||||
150
hw/bsp/stm32n6/FreeRTOSConfig/FreeRTOSConfig.h
Normal file
150
hw/bsp/stm32n6/FreeRTOSConfig/FreeRTOSConfig.h
Normal file
@@ -0,0 +1,150 @@
|
||||
/*
|
||||
* FreeRTOS Kernel V10.0.0
|
||||
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software. If you wish to use our Amazon
|
||||
* FreeRTOS name, please do so in a fair use way that does not cause confusion.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* http://www.FreeRTOS.org
|
||||
* http://aws.amazon.com/freertos
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
|
||||
#ifndef FREERTOS_CONFIG_H
|
||||
#define FREERTOS_CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Application specific definitions.
|
||||
*
|
||||
* These definitions should be adjusted for your particular hardware and
|
||||
* application requirements.
|
||||
*
|
||||
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
|
||||
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
|
||||
*
|
||||
* See http://www.freertos.org/a00110.html.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
// skip if included from IAR assembler
|
||||
#ifndef __IASMARM__
|
||||
#include "stm32n6xx.h"
|
||||
#endif
|
||||
|
||||
/* Cortex M55 port configuration. */
|
||||
#define configENABLE_MVE 0
|
||||
#define configENABLE_MPU 0
|
||||
#define configENABLE_FPU 1
|
||||
#define configENABLE_TRUSTZONE 0
|
||||
#define configMINIMAL_SECURE_STACK_SIZE (1024)
|
||||
|
||||
#define configUSE_PREEMPTION 1
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
|
||||
#define configCPU_CLOCK_HZ SystemCoreClock
|
||||
#define configTICK_RATE_HZ ( 1000 )
|
||||
#define configMAX_PRIORITIES ( 5 )
|
||||
#define configMINIMAL_STACK_SIZE ( 128 )
|
||||
#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*8*1024 )
|
||||
#define configMAX_TASK_NAME_LEN 16
|
||||
#define configUSE_16_BIT_TICKS 0
|
||||
#define configIDLE_SHOULD_YIELD 1
|
||||
#define configUSE_MUTEXES 1
|
||||
#define configUSE_RECURSIVE_MUTEXES 1
|
||||
#define configUSE_COUNTING_SEMAPHORES 1
|
||||
#define configQUEUE_REGISTRY_SIZE 4
|
||||
#define configUSE_QUEUE_SETS 0
|
||||
#define configUSE_TIME_SLICING 0
|
||||
#define configUSE_NEWLIB_REENTRANT 0
|
||||
#define configENABLE_BACKWARD_COMPATIBILITY 1
|
||||
#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
|
||||
|
||||
#define configSUPPORT_STATIC_ALLOCATION 1
|
||||
#define configSUPPORT_DYNAMIC_ALLOCATION 0
|
||||
|
||||
/* Hook function related definitions. */
|
||||
#define configUSE_IDLE_HOOK 0
|
||||
#define configUSE_TICK_HOOK 0
|
||||
#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
|
||||
#define configCHECK_FOR_STACK_OVERFLOW 2
|
||||
#define configCHECK_HANDLER_INSTALLATION 0
|
||||
|
||||
/* Run time and task stats gathering related definitions. */
|
||||
#define configGENERATE_RUN_TIME_STATS 0
|
||||
#define configRECORD_STACK_HIGH_ADDRESS 1
|
||||
#define configUSE_TRACE_FACILITY 1 // legacy trace
|
||||
#define configUSE_STATS_FORMATTING_FUNCTIONS 0
|
||||
|
||||
/* Co-routine definitions. */
|
||||
#define configUSE_CO_ROUTINES 0
|
||||
#define configMAX_CO_ROUTINE_PRIORITIES 2
|
||||
|
||||
/* Software timer related definitions. */
|
||||
#define configUSE_TIMERS 1
|
||||
#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
|
||||
#define configTIMER_QUEUE_LENGTH 32
|
||||
#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
|
||||
|
||||
/* Optional functions - most linkers will remove unused functions anyway. */
|
||||
#define INCLUDE_vTaskPrioritySet 0
|
||||
#define INCLUDE_uxTaskPriorityGet 0
|
||||
#define INCLUDE_vTaskDelete 0
|
||||
#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
|
||||
#define INCLUDE_xResumeFromISR 0
|
||||
#define INCLUDE_vTaskDelayUntil 1
|
||||
#define INCLUDE_vTaskDelay 1
|
||||
#define INCLUDE_xTaskGetSchedulerState 0
|
||||
#define INCLUDE_xTaskGetCurrentTaskHandle 1
|
||||
#define INCLUDE_uxTaskGetStackHighWaterMark 0
|
||||
#define INCLUDE_xTaskGetIdleTaskHandle 0
|
||||
#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
|
||||
#define INCLUDE_pcTaskGetTaskName 0
|
||||
#define INCLUDE_eTaskGetState 0
|
||||
#define INCLUDE_xEventGroupSetBitFromISR 0
|
||||
#define INCLUDE_xTimerPendFunctionCall 0
|
||||
|
||||
/* FreeRTOS hooks to NVIC vectors */
|
||||
#define xPortPendSVHandler PendSV_Handler
|
||||
#define xPortSysTickHandler SysTick_Handler
|
||||
#define vPortSVCHandler SVC_Handler
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Interrupt nesting behavior configuration.
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
|
||||
#define configPRIO_BITS 4
|
||||
|
||||
/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
|
||||
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<<configPRIO_BITS) - 1)
|
||||
|
||||
/* The highest interrupt priority that can be used by any interrupt service
|
||||
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
|
||||
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
|
||||
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
|
||||
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
|
||||
|
||||
/* Interrupt priorities used by the kernel port layer itself. These are generic
|
||||
to all Cortex-M ports, and do not rely on any particular library functions. */
|
||||
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
|
||||
|
||||
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
|
||||
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
|
||||
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,203 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** @file : STM32N657XX_AXISRAM2_fsbl.ld
|
||||
**
|
||||
** @author : GPM Application Team
|
||||
**
|
||||
** @brief : Linker script for STM32N657XX Device from STM32N6 series
|
||||
** 512 KBytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is, without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
******************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** Copyright (c) 2023 STMicroelectronics.
|
||||
** All rights reserved.
|
||||
**
|
||||
** This software is licensed under terms that can be found in the LICENSE file
|
||||
** in the root directory of this software component.
|
||||
** If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
**
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
|
||||
_sstack = _estack - _Min_Stack_Size;
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x800; /* required amount of stack */
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
ROM (xrw) : ORIGIN = 0x34180400, LENGTH = 255K
|
||||
RAM (xrw) : ORIGIN = 0x341C0000, LENGTH = 256K
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "RAM" Ram type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >ROM
|
||||
|
||||
/* The program code and other data into "RAM" Ram type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
*(.RamFunc) /* .RamFunc sections */
|
||||
*(.RamFunc*) /* .RamFunc* sections */
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >ROM
|
||||
|
||||
/* Constant data into "RAM" Ram type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >ROM
|
||||
|
||||
.ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(4);
|
||||
} >ROM
|
||||
|
||||
.ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(4);
|
||||
} >ROM
|
||||
|
||||
.preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >ROM
|
||||
|
||||
.init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >ROM
|
||||
|
||||
.fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >ROM
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM AT> ROM
|
||||
|
||||
.noncacheable :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__snoncacheable = .;/* create symbol for start of section */
|
||||
KEEP(*(.noncacheable))
|
||||
. = ALIGN(8);
|
||||
__enoncacheable = .; /* create symbol for end of section */
|
||||
} > RAM
|
||||
|
||||
|
||||
.gnu.sgstubs :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.gnu.sgstubs*) /* Secure Gateway stubs */
|
||||
. = ALIGN(4);
|
||||
} >ROM
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
17
hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake
Normal file
17
hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake
Normal file
@@ -0,0 +1,17 @@
|
||||
set(MCU_VARIANT stm32n657xx)
|
||||
set(JLINK_DEVICE stm32n6xx)
|
||||
|
||||
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32N657XX_AXISRAM2_fsbl.ld)
|
||||
|
||||
function(update_board TARGET)
|
||||
target_compile_definitions(${TARGET} PUBLIC
|
||||
STM32N657xx
|
||||
)
|
||||
target_sources(${TARGET} PUBLIC
|
||||
${ST_TCPP0203}/tcpp0203.c
|
||||
${ST_TCPP0203}/tcpp0203_reg.c
|
||||
)
|
||||
target_include_directories(${TARGET} PUBLIC
|
||||
${ST_TCPP0203}
|
||||
)
|
||||
endfunction()
|
||||
283
hw/bsp/stm32n6/boards/stm32n657nucleo/board.h
Normal file
283
hw/bsp/stm32n6/boards/stm32n657nucleo/board.h
Normal file
@@ -0,0 +1,283 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2021, Ha Thach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
/* metadata:
|
||||
name: STM32 N657X0-Q Nucleo
|
||||
url: https://www.st.com/en/evaluation-tools/nucleo-n657x0-q.html
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H_
|
||||
#define BOARD_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "stm32n657xx.h"
|
||||
#include "stm32n6xx_ll_exti.h"
|
||||
#include "stm32n6xx_ll_system.h"
|
||||
#include "tcpp0203.h"
|
||||
|
||||
#define UART_DEV USART1
|
||||
#define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE
|
||||
|
||||
#define BOARD_TUD_RHPORT 1
|
||||
|
||||
// VBUS Sense detection
|
||||
#define OTG_FS_VBUS_SENSE 1
|
||||
#define OTG_HS_VBUS_SENSE 1
|
||||
|
||||
#define PINID_LED 0
|
||||
#define PINID_BUTTON 1
|
||||
#define PINID_UART_TX 2
|
||||
#define PINID_UART_RX 3
|
||||
#define PINID_TCPP0203_EN 4
|
||||
|
||||
static board_pindef_t board_pindef[] = {
|
||||
{// LED
|
||||
.port = GPIOG,
|
||||
.pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
|
||||
.active_state = 1},
|
||||
{// Button
|
||||
.port = GPIOC,
|
||||
.pin_init = {.Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
|
||||
.active_state = 1},
|
||||
{// UART TX
|
||||
.port = GPIOE,
|
||||
.pin_init = {.Pin = GPIO_PIN_5, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF7_USART1},
|
||||
.active_state = 0},
|
||||
{// UART RX
|
||||
.port = GPIOE,
|
||||
.pin_init = {.Pin = GPIO_PIN_6, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF7_USART1},
|
||||
.active_state = 0},
|
||||
{// VBUS input pin used for TCPP0203 EN
|
||||
.port = GPIOA,
|
||||
.pin_init = {.Pin = GPIO_PIN_7, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
|
||||
.active_state = 0},
|
||||
{
|
||||
// I2C SCL for TCPP0203
|
||||
.port = GPIOB,
|
||||
.pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
|
||||
},
|
||||
{
|
||||
// I2C SDA for TCPP0203
|
||||
.port = GPIOB,
|
||||
.pin_init = {.Pin = GPIO_PIN_11, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
|
||||
},
|
||||
{
|
||||
// INT for TCPP0203
|
||||
.port = GPIOD,
|
||||
.pin_init = {.Pin = GPIO_PIN_2, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
|
||||
},
|
||||
};
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// RCC Clock
|
||||
//--------------------------------------------------------------------+
|
||||
void SystemClock_Config(void) {
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
/* Configure the power domain */
|
||||
if (HAL_PWREx_ConfigSupply(PWR_EXTERNAL_SOURCE_SUPPLY) != HAL_OK) {
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/* Get current CPU/System buses clocks configuration */
|
||||
/* and if necessary switch to intermediate HSI clock */
|
||||
/* to ensure target clock can be set */
|
||||
HAL_RCC_GetClockConfig(&RCC_ClkInitStruct);
|
||||
if ((RCC_ClkInitStruct.CPUCLKSource == RCC_CPUCLKSOURCE_IC1) ||
|
||||
(RCC_ClkInitStruct.SYSCLKSource == RCC_SYSCLKSOURCE_IC2_IC6_IC11)) {
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_CPUCLK | RCC_CLOCKTYPE_SYSCLK);
|
||||
RCC_ClkInitStruct.CPUCLKSource = RCC_CPUCLKSOURCE_HSI;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) {
|
||||
Error_Handler();
|
||||
}
|
||||
}
|
||||
|
||||
/* HSE selected as source (stable clock on Level 0 samples */
|
||||
/* PLL1 output = ((HSE/PLLM)*PLLN)/PLLP1/PLLP2 */
|
||||
/* = ((48000000/3)*75)/1/1 */
|
||||
/* = (16000000*75)/1/1 */
|
||||
/* = 1200000000 (1200 MHz) */
|
||||
/* PLL2 off */
|
||||
/* PLL3 off */
|
||||
/* PLL4 off */
|
||||
|
||||
/* Enable HSE && HSI */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
|
||||
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* 48 MHz */
|
||||
|
||||
RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL1.PLLSource = RCC_PLLSOURCE_HSE;
|
||||
RCC_OscInitStruct.PLL1.PLLM = 3;
|
||||
RCC_OscInitStruct.PLL1.PLLN = 75; /* PLL1 VCO = 48/3 * 75 = 1200MHz */
|
||||
RCC_OscInitStruct.PLL1.PLLP1 = 1; /* PLL output = PLL VCO frequency / (PLLP1 * PLLP2) */
|
||||
RCC_OscInitStruct.PLL1.PLLP2 = 1; /* PLL output = 1200 MHz */
|
||||
RCC_OscInitStruct.PLL1.PLLFractional = 0;
|
||||
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
/* Initialization error */
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/* Select PLL1 outputs as CPU and System bus clock source */
|
||||
/* CPUCLK = ic1_ck = PLL1 output/ic1_divider = 600 MHz */
|
||||
/* SYSCLK = ic2_ck = PLL1 output/ic2_divider = 400 MHz */
|
||||
/* Configure the HCLK clock divider */
|
||||
/* HCLK = PLL1 SYSCLK/HCLK divider = 200 MHz */
|
||||
/* PCLKx = HCLK / PCLKx divider = 200 MHz */
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_CPUCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK |
|
||||
RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK4 | RCC_CLOCKTYPE_PCLK5);
|
||||
RCC_ClkInitStruct.CPUCLKSource = RCC_CPUCLKSOURCE_IC1;
|
||||
RCC_ClkInitStruct.IC1Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1;
|
||||
RCC_ClkInitStruct.IC1Selection.ClockDivider = 2;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_IC2_IC6_IC11;
|
||||
RCC_ClkInitStruct.IC2Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1;
|
||||
RCC_ClkInitStruct.IC2Selection.ClockDivider = 3;
|
||||
RCC_ClkInitStruct.IC6Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1;
|
||||
RCC_ClkInitStruct.IC6Selection.ClockDivider = 3;
|
||||
RCC_ClkInitStruct.IC11Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1;
|
||||
RCC_ClkInitStruct.IC11Selection.ClockDivider = 3;
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1;
|
||||
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1;
|
||||
RCC_ClkInitStruct.APB5CLKDivider = RCC_APB5_DIV1;
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) {
|
||||
/* Initialization Error */
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/** Initializes the peripherals clock
|
||||
*/
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USBOTGHS1;
|
||||
PeriphClkInitStruct.UsbOtgHs1ClockSelection = RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT;
|
||||
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
|
||||
/* Initialization Error */
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/** Set USB OTG HS PHY1 Reference Clock Source */
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USBPHY1;
|
||||
PeriphClkInitStruct.UsbPhy1ClockSelection = RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT;
|
||||
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
|
||||
/* Initialization Error */
|
||||
Error_Handler();
|
||||
}
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// USB PD
|
||||
//--------------------------------------------------------------------+
|
||||
static I2C_HandleTypeDef i2c_handle = {
|
||||
.Instance = I2C2,
|
||||
.Init = {
|
||||
.Timing = 0x20C0EDFF,
|
||||
.OwnAddress1 = 0,
|
||||
.AddressingMode = I2C_ADDRESSINGMODE_7BIT,
|
||||
.DualAddressMode = I2C_DUALADDRESS_DISABLE,
|
||||
.OwnAddress2 = 0,
|
||||
.OwnAddress2Masks = I2C_OA2_NOMASK,
|
||||
.GeneralCallMode = I2C_GENERALCALL_DISABLE,
|
||||
.NoStretchMode = I2C_NOSTRETCH_DISABLE,
|
||||
}};
|
||||
static TCPP0203_Object_t tcpp0203_obj = {0};
|
||||
|
||||
int32_t board_tcpp0203_init(void) {
|
||||
board_pindef_t *pindef = &board_pindef[PINID_TCPP0203_EN];
|
||||
HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, GPIO_PIN_SET);
|
||||
|
||||
__HAL_RCC_I2C2_CLK_ENABLE();
|
||||
__HAL_RCC_I2C2_FORCE_RESET();
|
||||
__HAL_RCC_I2C2_RELEASE_RESET();
|
||||
if (HAL_I2C_Init(&i2c_handle) != HAL_OK) {
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
NVIC_SetPriority(EXTI8_IRQn, 12);
|
||||
NVIC_EnableIRQ(EXTI8_IRQn);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32_t board_tcpp0203_deinit(void) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32_t i2c_readreg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) {
|
||||
TU_ASSERT(HAL_OK == HAL_I2C_Mem_Read(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000));
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32_t i2c_writereg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) {
|
||||
TU_ASSERT(HAL_OK == HAL_I2C_Mem_Write(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void board_init2(void) {
|
||||
TCPP0203_IO_t io_ctx;
|
||||
|
||||
io_ctx.Address = TCPP0203_I2C_ADDRESS_X68;
|
||||
io_ctx.Init = board_tcpp0203_init;
|
||||
io_ctx.DeInit = board_tcpp0203_deinit;
|
||||
io_ctx.ReadReg = i2c_readreg;
|
||||
io_ctx.WriteReg = i2c_writereg;
|
||||
|
||||
TU_ASSERT(TCPP0203_RegisterBusIO(&tcpp0203_obj, &io_ctx) == TCPP0203_OK, );
|
||||
|
||||
TU_ASSERT(TCPP0203_Init(&tcpp0203_obj) == TCPP0203_OK, );
|
||||
|
||||
TU_ASSERT(TCPP0203_SetPowerMode(&tcpp0203_obj, TCPP0203_POWER_MODE_NORMAL) == TCPP0203_OK, );
|
||||
}
|
||||
|
||||
void board_vbus_set(uint8_t rhport, bool state) {
|
||||
(void) state;
|
||||
if (rhport == 1) {
|
||||
TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, );
|
||||
}
|
||||
}
|
||||
|
||||
void EXTI8_IRQHandler(void) {
|
||||
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_8);
|
||||
if (tcpp0203_obj.IsInitialized) {
|
||||
TU_ASSERT(TCPP0203_SetPowerMode(&tcpp0203_obj, TCPP0203_POWER_MODE_NORMAL) == TCPP0203_OK, );
|
||||
TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, );
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
17
hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk
Normal file
17
hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk
Normal file
@@ -0,0 +1,17 @@
|
||||
MCU_VARIANT = stm32n657xx
|
||||
CFLAGS += -DSTM32N657xx
|
||||
JLINK_DEVICE = stm32n6xx
|
||||
|
||||
LD_FILE_GCC = $(BOARD_PATH)/STM32N657XX_AXISRAM2_fsbl.ld
|
||||
|
||||
# flash target using on-board stlink
|
||||
flash: flash-stlink
|
||||
|
||||
PORT = 1
|
||||
|
||||
SRC_C += \
|
||||
$(ST_TCPP0203)/tcpp0203.c \
|
||||
$(ST_TCPP0203)/tcpp0203_reg.c \
|
||||
|
||||
INC += \
|
||||
$(TOP)/$(ST_TCPP0203) \
|
||||
280
hw/bsp/stm32n6/family.c
Normal file
280
hw/bsp/stm32n6/family.c
Normal file
@@ -0,0 +1,280 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2019
|
||||
* William D. Jones (thor0505@comcast.net),
|
||||
* Ha Thach (tinyusb.org)
|
||||
* Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
/* metadata:
|
||||
manufacturer: STMicroelectronics
|
||||
*/
|
||||
|
||||
// Suppress warning caused by mcu driver
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wcast-align"
|
||||
#endif
|
||||
|
||||
#include "stm32n6xx_hal.h"
|
||||
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
#include "bsp/board_api.h"
|
||||
|
||||
TU_ATTR_UNUSED static void Error_Handler(void) { }
|
||||
|
||||
void HardFault_Handler(void);
|
||||
|
||||
typedef struct {
|
||||
GPIO_TypeDef* port;
|
||||
GPIO_InitTypeDef pin_init;
|
||||
uint8_t active_state;
|
||||
} board_pindef_t;
|
||||
|
||||
#include "board.h"
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// MACRO TYPEDEF CONSTANT ENUM
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
#ifdef UART_DEV
|
||||
UART_HandleTypeDef UartHandle = {
|
||||
.Instance = UART_DEV,
|
||||
.Init = {
|
||||
.BaudRate = CFG_BOARD_UART_BAUDRATE,
|
||||
.WordLength = UART_WORDLENGTH_8B,
|
||||
.StopBits = UART_STOPBITS_1,
|
||||
.Parity = UART_PARITY_NONE,
|
||||
.HwFlowCtl = UART_HWCONTROL_NONE,
|
||||
.Mode = UART_MODE_TX_RX,
|
||||
.OverSampling = UART_OVERSAMPLING_16,
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifndef SWO_FREQ
|
||||
#define SWO_FREQ 4000000
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Forward USB interrupt events to TinyUSB IRQ Handler
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
// Despite being call USB2_OTG_FS on some MCUs
|
||||
// OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port
|
||||
void USB2_OTG_HS_IRQHandler(void) {
|
||||
tusb_int_handler(0, true);
|
||||
}
|
||||
|
||||
// Despite being call USB1_OTG_HS on some MCUs
|
||||
// OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
|
||||
void USB1_OTG_HS_IRQHandler(void) {
|
||||
tusb_int_handler(1, true);
|
||||
}
|
||||
|
||||
void board_init(void) {
|
||||
|
||||
/* Enable BusFault and SecureFault handlers (HardFault is default) */
|
||||
SCB->SHCSR |= (SCB_SHCSR_BUSFAULTENA_Msk | SCB_SHCSR_SECUREFAULTENA_Msk);
|
||||
|
||||
HAL_PWREx_EnableVddA();
|
||||
HAL_PWREx_EnableVddIO2();
|
||||
HAL_PWREx_EnableVddIO3();
|
||||
HAL_PWREx_EnableVddIO4();
|
||||
HAL_PWREx_EnableVddIO5();
|
||||
|
||||
HAL_Init();
|
||||
|
||||
// Implemented in board.h
|
||||
SystemClock_Config();
|
||||
|
||||
// Enable All GPIOs clocks
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOD_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOE_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOF_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOG_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOH_CLK_ENABLE();
|
||||
__HAL_RCC_GPION_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOO_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOP_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOQ_CLK_ENABLE();
|
||||
|
||||
// HAL_ICACHE_Enable();
|
||||
|
||||
for (uint8_t i = 0; i < TU_ARRAY_SIZE(board_pindef); i++) {
|
||||
HAL_GPIO_Init(board_pindef[i].port, &board_pindef[i].pin_init);
|
||||
}
|
||||
|
||||
NVIC_SetPriority(UCPD1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),5, 0));
|
||||
NVIC_EnableIRQ(UCPD1_IRQn);
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
// 1ms tick timer
|
||||
SysTick_Config(SystemCoreClock / 1000);
|
||||
|
||||
#elif CFG_TUSB_OS == OPT_OS_FREERTOS
|
||||
// Explicitly disable systick to prevent its ISR runs before scheduler start
|
||||
SysTick->CTRL &= ~1U;
|
||||
|
||||
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
|
||||
|
||||
NVIC_SetPriority(USB1_OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#ifdef UART_DEV
|
||||
UART_CLK_EN();
|
||||
HAL_UART_Init(&UartHandle);
|
||||
#endif
|
||||
|
||||
|
||||
__HAL_RCC_USB1_OTG_HS_CLK_ENABLE();
|
||||
__HAL_RCC_PWR_CLK_ENABLE();
|
||||
HAL_PWREx_EnableVddUSBVMEN();
|
||||
while(__HAL_PWR_GET_FLAG(PWR_FLAG_USB33RDY));
|
||||
HAL_PWREx_EnableVddUSB();
|
||||
|
||||
LL_AHB5_GRP1_ForceReset(0x00800000);
|
||||
__HAL_RCC_USB1_OTG_HS_FORCE_RESET();
|
||||
__HAL_RCC_USB1_OTG_HS_PHY_FORCE_RESET();
|
||||
|
||||
LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock();
|
||||
LL_AHB5_GRP1_ReleaseReset(0x00800000);
|
||||
|
||||
/* Peripheral clock enable */
|
||||
__HAL_RCC_USB1_OTG_HS_CLK_ENABLE();
|
||||
|
||||
/* Required few clock cycles before accessing USB PHY Controller Registers */
|
||||
for (volatile uint32_t i = 0; i < 10; i++) {
|
||||
__NOP(); // No Operation instruction to create a delay
|
||||
}
|
||||
|
||||
USB1_HS_PHYC->USBPHYC_CR &= ~(0x7 << 0x4);
|
||||
|
||||
USB1_HS_PHYC->USBPHYC_CR |= (0x1 << 16) |
|
||||
(0x2 << 4) |
|
||||
(0x1 << 2) |
|
||||
0x1U;
|
||||
|
||||
__HAL_RCC_USB1_OTG_HS_PHY_RELEASE_RESET();
|
||||
|
||||
/* Required few clock cycles before Releasing Reset */
|
||||
for (volatile uint32_t i = 0; i < 10; i++) {
|
||||
__NOP(); // No Operation instruction to create a delay
|
||||
}
|
||||
|
||||
__HAL_RCC_USB1_OTG_HS_RELEASE_RESET();
|
||||
|
||||
/* Peripheral PHY clock enable */
|
||||
__HAL_RCC_USB1_OTG_HS_PHY_CLK_ENABLE();
|
||||
|
||||
board_init2();
|
||||
|
||||
#if CFG_TUH_ENABLED
|
||||
board_vbus_set(BOARD_TUH_RHPORT, 1);
|
||||
#endif
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Board porting API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
void board_led_write(bool state) {
|
||||
#ifdef PINID_LED
|
||||
board_pindef_t* pindef = &board_pindef[PINID_LED];
|
||||
GPIO_PinState pin_state = state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET;
|
||||
HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, pin_state);
|
||||
#else
|
||||
(void) state;
|
||||
#endif
|
||||
}
|
||||
|
||||
uint32_t board_button_read(void) {
|
||||
#ifdef PINID_BUTTON
|
||||
board_pindef_t* pindef = &board_pindef[PINID_BUTTON];
|
||||
return pindef->active_state == HAL_GPIO_ReadPin(pindef->port, pindef->pin_init.Pin);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
size_t board_get_unique_id(uint8_t id[], size_t max_len) {
|
||||
(void) max_len;
|
||||
volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
|
||||
uint32_t* id32 = (uint32_t*) (uintptr_t) id;
|
||||
uint8_t const len = 12;
|
||||
|
||||
id32[0] = stm32_uuid[0];
|
||||
id32[1] = stm32_uuid[1];
|
||||
id32[2] = stm32_uuid[2];
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
int board_uart_read(uint8_t *buf, int len) {
|
||||
(void) buf;
|
||||
(void) len;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_uart_write(void const *buf, int len) {
|
||||
#ifdef UART_DEV
|
||||
HAL_UART_Transmit(&UartHandle, (uint8_t * )(uintptr_t)
|
||||
buf, len, 0xffff);
|
||||
return len;
|
||||
#else
|
||||
(void) buf; (void) len;
|
||||
return -1;
|
||||
#endif
|
||||
}
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
volatile uint32_t system_ticks = 0;
|
||||
|
||||
void SysTick_Handler(void) {
|
||||
HAL_IncTick();
|
||||
system_ticks++;
|
||||
}
|
||||
|
||||
uint32_t board_millis(void) {
|
||||
return system_ticks;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
void HardFault_Handler(void) {
|
||||
__asm("BKPT #0\n");
|
||||
}
|
||||
|
||||
// Required by __libc_init_array in startup code if we are compiling using
|
||||
// -nostdlib/-nostartfiles.
|
||||
void _init(void) {
|
||||
}
|
||||
148
hw/bsp/stm32n6/family.cmake
Normal file
148
hw/bsp/stm32n6/family.cmake
Normal file
@@ -0,0 +1,148 @@
|
||||
include_guard()
|
||||
|
||||
set(ST_FAMILY n6)
|
||||
set(ST_PREFIX stm32${ST_FAMILY}xx)
|
||||
|
||||
set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
|
||||
set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
|
||||
set(CMSIS_5 ${TOP}/lib/CMSIS_5)
|
||||
set(ST_TCPP0203 ${TOP}/hw/mcu/st/stm32-tcpp0203)
|
||||
|
||||
# include board specific
|
||||
include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
|
||||
|
||||
# toolchain set up
|
||||
set(CMAKE_SYSTEM_CPU cortex-m55 CACHE INTERNAL "System Processor")
|
||||
set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
|
||||
|
||||
set(FAMILY_MCUS STM32N6 CACHE INTERNAL "")
|
||||
|
||||
# ----------------------
|
||||
# Port & Speed Selection
|
||||
# ----------------------
|
||||
if (NOT DEFINED RHPORT_DEVICE)
|
||||
set(RHPORT_DEVICE 1)
|
||||
endif ()
|
||||
if (NOT DEFINED RHPORT_HOST)
|
||||
set(RHPORT_HOST 1)
|
||||
endif ()
|
||||
|
||||
# N6 are all high speed
|
||||
if (NOT DEFINED RHPORT_DEVICE_SPEED)
|
||||
set(RHPORT_DEVICE_SPEED OPT_MODE_HIGH_SPEED)
|
||||
endif ()
|
||||
if (NOT DEFINED RHPORT_HOST_SPEED)
|
||||
set(RHPORT_HOST_SPEED OPT_MODE_HIGH_SPEED)
|
||||
endif ()
|
||||
|
||||
cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED)
|
||||
|
||||
#------------------------------------
|
||||
# BOARD_TARGET
|
||||
#------------------------------------
|
||||
# only need to be built ONCE for all examples
|
||||
function(add_board_target BOARD_TARGET)
|
||||
if (TARGET ${BOARD_TARGET})
|
||||
return()
|
||||
endif()
|
||||
|
||||
# Startup & Linker script
|
||||
set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
|
||||
set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
|
||||
set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
|
||||
|
||||
if(NOT DEFINED LD_FILE_GNU)
|
||||
set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash.ld)
|
||||
endif()
|
||||
set(LD_FILE_Clang ${LD_FILE_GNU})
|
||||
if(NOT DEFINED LD_FILE_IAR)
|
||||
set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
|
||||
endif()
|
||||
|
||||
add_library(${BOARD_TARGET} STATIC
|
||||
${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}_fsbl.c
|
||||
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
|
||||
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
|
||||
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c
|
||||
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
|
||||
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c
|
||||
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_i2c.c
|
||||
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
|
||||
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
|
||||
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
|
||||
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
|
||||
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
|
||||
${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
|
||||
)
|
||||
target_include_directories(${BOARD_TARGET} PUBLIC
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}
|
||||
${CMSIS_5}/CMSIS/Core/Include
|
||||
${ST_CMSIS}/Include
|
||||
${ST_HAL_DRIVER}/Inc
|
||||
)
|
||||
target_compile_definitions(${BOARD_TARGET} PUBLIC
|
||||
BOARD_TUD_RHPORT=${RHPORT_DEVICE}
|
||||
BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
|
||||
BOARD_TUH_RHPORT=${RHPORT_HOST}
|
||||
BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
|
||||
SEGGER_RTT_SECTION="noncacheable_buffer"
|
||||
BUFFER_SIZE_UP=0x3000
|
||||
)
|
||||
|
||||
update_board(${BOARD_TARGET})
|
||||
|
||||
if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
|
||||
target_link_options(${BOARD_TARGET} PUBLIC
|
||||
"LINKER:--script=${LD_FILE_GNU}"
|
||||
-nostartfiles
|
||||
--specs=nosys.specs --specs=nano.specs
|
||||
)
|
||||
elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
|
||||
target_link_options(${BOARD_TARGET} PUBLIC
|
||||
"LINKER:--script=${LD_FILE_Clang}"
|
||||
)
|
||||
elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
|
||||
target_link_options(${BOARD_TARGET} PUBLIC
|
||||
"LINKER:--config=${LD_FILE_IAR}"
|
||||
)
|
||||
endif ()
|
||||
endfunction()
|
||||
|
||||
|
||||
#------------------------------------
|
||||
# Functions
|
||||
#------------------------------------
|
||||
function(family_configure_example TARGET RTOS)
|
||||
family_configure_common(${TARGET} ${RTOS})
|
||||
|
||||
# Board target
|
||||
add_board_target(board_${BOARD})
|
||||
|
||||
#---------- Port Specific ----------
|
||||
# These files are built for each example since it depends on example's tusb_config.h
|
||||
target_sources(${TARGET} PUBLIC
|
||||
# BSP
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
|
||||
)
|
||||
target_include_directories(${TARGET} PUBLIC
|
||||
# family, hw, board
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
|
||||
)
|
||||
|
||||
# Add TinyUSB target and port source
|
||||
family_add_tinyusb(${TARGET} OPT_MCU_STM32N6 ${RTOS})
|
||||
target_sources(${TARGET} PUBLIC
|
||||
${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
|
||||
${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c
|
||||
${TOP}/src/portable/synopsys/dwc2/dwc2_common.c
|
||||
)
|
||||
target_link_libraries(${TARGET} PUBLIC board_${BOARD})
|
||||
|
||||
# Flashing
|
||||
family_add_bin_hex(${TARGET})
|
||||
family_flash_stlink(${TARGET})
|
||||
family_flash_jlink(${TARGET})
|
||||
endfunction()
|
||||
89
hw/bsp/stm32n6/family.mk
Normal file
89
hw/bsp/stm32n6/family.mk
Normal file
@@ -0,0 +1,89 @@
|
||||
ST_FAMILY = n6
|
||||
ST_PREFIX = stm32${ST_FAMILY}xx
|
||||
ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
|
||||
ST_HAL_DRIVER = hw/mcu/st/${ST_PREFIX}_hal_driver
|
||||
ST_TCPP0203 = hw/mcu/st/stm32-tcpp0203
|
||||
|
||||
UF2_FAMILY_ID = 0x6db66083
|
||||
|
||||
include $(TOP)/$(BOARD_PATH)/board.mk
|
||||
CPU_CORE ?= cortex-m55
|
||||
|
||||
# ----------------------
|
||||
# Port & Speed Selection
|
||||
# ----------------------
|
||||
RHPORT_DEVICE ?= 1
|
||||
RHPORT_HOST ?= 1
|
||||
|
||||
ifndef RHPORT_DEVICE_SPEED
|
||||
RHPORT_DEVICE_SPEED = OPT_MODE_HIGH_SPEED
|
||||
endif
|
||||
|
||||
ifndef RHPORT_HOST_SPEED
|
||||
RHPORT_HOST_SPEED = OPT_MODE_HIGH_SPEED
|
||||
endif
|
||||
|
||||
# --------------
|
||||
# Compiler Flags
|
||||
# --------------
|
||||
CFLAGS += \
|
||||
-DCFG_TUSB_MCU=OPT_MCU_STM32N6 \
|
||||
-DBOARD_TUD_RHPORT=${RHPORT_DEVICE} \
|
||||
-DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \
|
||||
-DBOARD_TUH_RHPORT=${RHPORT_HOST} \
|
||||
-DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \
|
||||
-DSEGGER_RTT_SECTION=\"noncacheable_buffer\" \
|
||||
-DBUFFER_SIZE_UP=0x3000 \
|
||||
|
||||
# GCC Flags
|
||||
CFLAGS_GCC += \
|
||||
-flto \
|
||||
|
||||
# suppress warning caused by vendor mcu driver
|
||||
CFLAGS_GCC += \
|
||||
-Wno-error=cast-align \
|
||||
-Wno-error=unused-parameter \
|
||||
|
||||
LDFLAGS_GCC += \
|
||||
-nostdlib -nostartfiles \
|
||||
--specs=nosys.specs --specs=nano.specs
|
||||
|
||||
# -----------------
|
||||
# Sources & Include
|
||||
# -----------------
|
||||
|
||||
SRC_C += \
|
||||
src/portable/synopsys/dwc2/dcd_dwc2.c \
|
||||
src/portable/synopsys/dwc2/hcd_dwc2.c \
|
||||
src/portable/synopsys/dwc2/dwc2_common.c \
|
||||
$(ST_CMSIS)/Source/Templates/system_${ST_PREFIX}_fsbl.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_cortex.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_dma.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_gpio.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_hcd.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_i2c.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pcd.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pcd_ex.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr_ex.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc_ex.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rif.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart_ex.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_ll_usb.c \
|
||||
|
||||
INC += \
|
||||
$(TOP)/$(BOARD_PATH) \
|
||||
$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
|
||||
$(TOP)/$(ST_CMSIS)/Include \
|
||||
$(TOP)/$(ST_HAL_DRIVER)/Inc
|
||||
|
||||
# Startup
|
||||
SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT)_fsbl.s
|
||||
SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
|
||||
|
||||
# Linker
|
||||
LD_FILE_GCC ?= $(ST_CMSIS)/Source/Templates/gcc/linker/$(MCU_VARIANT)_flash.ld
|
||||
LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf
|
||||
792
hw/bsp/stm32n6/partition_stm32n657xx.h
Normal file
792
hw/bsp/stm32n6/partition_stm32n657xx.h
Normal file
@@ -0,0 +1,792 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file partition_stm32n657xx.h
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS STM32N657xx Device Initial Setup for Secure / Non-Secure Zones
|
||||
* for ARMCM55 based on CMSIS CORE V5.3.1 partition_ARMCM33.h Template.
|
||||
*
|
||||
* This file contains:
|
||||
* - Initialize Security Attribution Unit (SAU) CTRL register
|
||||
* - Setup behavior of Sleep and Exception Handling
|
||||
* - Setup behavior of Floating Point Unit
|
||||
* - Setup Interrupt Target
|
||||
*
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
|
||||
* Portions Copyright (c) 2023 STMicroelectronics, all rights reserved
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef PARTITION_STM32N657XX_H
|
||||
#define PARTITION_STM32N657XX_H
|
||||
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize Security Attribution Unit (SAU) CTRL register
|
||||
*/
|
||||
#define SAU_INIT_CTRL 0
|
||||
|
||||
/*
|
||||
// <q> Enable SAU
|
||||
// <i> Value for SAU->CTRL register bit ENABLE
|
||||
*/
|
||||
#define SAU_INIT_CTRL_ENABLE 0
|
||||
|
||||
/*
|
||||
// <o> When SAU is disabled
|
||||
// <0=> All Memory is Secure
|
||||
// <1=> All Memory is Non-Secure
|
||||
// <i> Value for SAU->CTRL register bit ALLNS
|
||||
// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
|
||||
*/
|
||||
#define SAU_INIT_CTRL_ALLNS 0
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <h>Initialize Security Attribution Unit (SAU) Address Regions
|
||||
// <i>SAU configuration specifies regions to be one of:
|
||||
// <i> - Secure and Non-Secure Callable
|
||||
// <i> - Non-Secure
|
||||
// <i>Note: All memory regions not configured by SAU are Secure
|
||||
*/
|
||||
#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 0
|
||||
// <i> Setup SAU Region 0 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION0 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END0 0x00000000 /* end address of SAU region 0 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC0 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 1
|
||||
// <i> Setup SAU Region 1 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION1 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START1 0x00000000 /* start address of SAU region 1 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END1 0x00000000 /* end address of SAU region 1 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC1 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 2
|
||||
// <i> Setup SAU Region 2 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION2 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START2 0x00000000 /* start address of SAU region 2 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END2 0x00000000 /* end address of SAU region 2 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC2 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 3
|
||||
// <i> Setup SAU Region 3 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION3 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START3 0x00000000 /* start address of SAU region 3 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END3 0x00000000 /* end address of SAU region 3 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC3 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 4
|
||||
// <i> Setup SAU Region 4 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION4 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC4 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 5
|
||||
// <i> Setup SAU Region 5 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION5 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC5 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 6
|
||||
// <i> Setup SAU Region 6 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION6 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC6 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 7
|
||||
// <i> Setup SAU Region 7 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION7 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC7 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// </h>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Setup behaviour of Sleep and Exception Handling
|
||||
*/
|
||||
#define SCB_CSR_AIRCR_INIT 0
|
||||
|
||||
/*
|
||||
// <o> Deep Sleep can be enabled by
|
||||
// <0=>Secure and Non-Secure state
|
||||
// <1=>Secure state only
|
||||
// <i> Value for SCB->CSR register bit DEEPSLEEPS
|
||||
*/
|
||||
#define SCB_CSR_DEEPSLEEPS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>System reset request accessible from
|
||||
// <0=> Secure and Non-Secure state
|
||||
// <1=> Secure state only
|
||||
// <i> Value for SCB->AIRCR register bit SYSRESETREQS
|
||||
*/
|
||||
#define SCB_AIRCR_SYSRESETREQS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>Priority of Non-Secure exceptions is
|
||||
// <0=> Not altered
|
||||
// <1=> Lowered to 0x04-0x07
|
||||
// <i> Value for SCB->AIRCR register bit PRIS
|
||||
*/
|
||||
#define SCB_AIRCR_PRIS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>BusFault, HardFault, and NMI target
|
||||
// <0=> Secure state
|
||||
// <1=> Non-Secure state
|
||||
// <i> Value for SCB->AIRCR register bit BFHFNMINS
|
||||
*/
|
||||
#define SCB_AIRCR_BFHFNMINS_VAL 0
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Setup behaviour of Floating Point Unit
|
||||
*/
|
||||
#define TZ_FPU_NS_USAGE 1
|
||||
|
||||
/*
|
||||
// <o>Floating Point Unit usage
|
||||
// <0=> Secure state only
|
||||
// <3=> Secure and Non-Secure state
|
||||
// <i> Value for SCB->NSACR register bits CP10, CP11
|
||||
*/
|
||||
#define SCB_NSACR_CP10_11_VAL 3
|
||||
|
||||
/*
|
||||
// <o>Treat floating-point registers as Secure
|
||||
// <0=> Disabled
|
||||
// <1=> Enabled
|
||||
// <i> Value for FPU->FPCCR register bit TS
|
||||
*/
|
||||
#define FPU_FPCCR_TS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>Clear on return (CLRONRET) accessibility
|
||||
// <0=> Secure and Non-Secure state
|
||||
// <1=> Secure state only
|
||||
// <i> Value for FPU->FPCCR register bit CLRONRETS
|
||||
*/
|
||||
#define FPU_FPCCR_CLRONRETS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>Clear floating-point caller saved registers on exception return
|
||||
// <0=> Disabled
|
||||
// <1=> Enabled
|
||||
// <i> Value for FPU->FPCCR register bit CLRONRET
|
||||
*/
|
||||
#define FPU_FPCCR_CLRONRET_VAL 1
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <h>Setup Interrupt Target
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 0 (Interrupts 0..31)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS0 1
|
||||
|
||||
/*
|
||||
// Interrupts 0..31
|
||||
// <o.0> PVD_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> Reserved <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> DTS_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> RCC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> LOCKUP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> CACHE_ECC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> TCM_ECC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> BKP_ECC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> FPU_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> Reserved <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> RTC_S_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> TAMP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> RIFSC_TAMPER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> IAC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> RCC_S_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> Reserved <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> RTC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> Reserved <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> IWDG_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> WWDG_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> EXTI0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> EXTI1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> EXTI2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> EXTI3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> EXTI4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> EXTI5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> EXTI6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> EXTI7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> EXTI8_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> EXTI9_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> EXTI10_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> EXTI11_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS0_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 1 (Interrupts 32..63)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS1 1
|
||||
|
||||
/*
|
||||
// Interrupts 32..63
|
||||
// <o.0> EXTI12_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> EXTI13_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> EXTI14_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> EXTI15_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> SAES_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> CRYP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> PKA_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> HASH_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> RNG_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> Reserved <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> MCE1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> MCE2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> MCE3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> MCE4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> ADC1_2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> CSI_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> DCMIPP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> Reserved <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> Reserved <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> Reserved <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> PAHB_ERR_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> NPU0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> NPU1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> NPU2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> NPU3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> CACHEAXI_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> LTDC_LO_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> LTDC_LO_ERR_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> DMA2D_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> JPEG_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> VENC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> GFXMMU_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS1_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 2 (Interrupts 64..95)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS2 1
|
||||
|
||||
/*
|
||||
// Interrupts 64..95
|
||||
// <o.0> GFXTIM_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> GPU2D_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> GPU2D_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> ICACHE_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> HPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> HPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> HPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> HPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> HPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> HPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> HPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> HPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> HPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> HPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> HPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> HPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> HPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> HPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> HPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> HPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS2_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 3 (Interrupts 96..127)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS3 1
|
||||
|
||||
/*
|
||||
// Interrupts 96..127
|
||||
// <o.0> GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> I3C2_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> I3C2_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> TIM2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> TIM3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> TIM4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> TIM5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> TIM6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> TIM7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> TIM9_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> TIM10_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
|
||||
*/
|
||||
#define NVIC_INIT_ITNS3_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 4 (Interrupts 128..159)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS4 1
|
||||
|
||||
/*
|
||||
// Interrupts 128..159
|
||||
// <o.0> TIM11_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> TIM12_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> TIM13_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> TIM14_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> TIM15_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> TIM16_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> TIM17_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> TIM18_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> LPTIM5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> ADF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> SAI1_A_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> SAI1_B_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> SAI2_A_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> SAI2_B_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> SPDIFRX1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> SPI1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> SPI2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> SPI3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> SPI4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> SPI5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> SPI6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> USART1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
|
||||
*/
|
||||
#define NVIC_INIT_ITNS4_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 5 (Interrupts 160..191)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS5 1
|
||||
|
||||
/*
|
||||
// Interrupts 160..191
|
||||
// <o.0> USART2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> USART3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> UART4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> UART5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> USART6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> UART7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> UART8_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> UART9_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> USART10_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> LPUART1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> XSPI1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> XSPI2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> XSPI3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> FMC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> UCPD1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> USB1_OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> USB2_OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> ETH1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> FDCAN2_IT0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> FDCAN2_IT1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> FDCAN3_IT0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> FDCAN3_IT1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> FDCAN_CU_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> MDIOS_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> WAKEUP_PIN_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> CTI_INT0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> CTI_INT1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
|
||||
*/
|
||||
#define NVIC_INIT_ITNS5_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 6 (Interrupts 192..223)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS6 1
|
||||
|
||||
/*
|
||||
// Interrupts 192..223
|
||||
// <o.0> Reserved <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> LTDC_UP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> LTDC_UP_ERR_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
|
||||
*/
|
||||
#define NVIC_INIT_ITNS6_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// </h>
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
max 8 SAU regions.
|
||||
SAU regions are defined in partition.h
|
||||
*/
|
||||
|
||||
#define SAU_INIT_REGION(n) \
|
||||
SAU->RNR = (n & SAU_RNR_REGION_Msk); \
|
||||
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
|
||||
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
|
||||
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
|
||||
|
||||
/**
|
||||
\brief Setup a SAU Region
|
||||
\details Writes the region information contained in SAU_Region to the
|
||||
registers SAU_RNR, SAU_RBAR, and SAU_RLAR
|
||||
*/
|
||||
__STATIC_INLINE void TZ_SAU_Setup (void)
|
||||
{
|
||||
|
||||
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
|
||||
|
||||
#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
|
||||
SAU_INIT_REGION(0);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
|
||||
SAU_INIT_REGION(1);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
|
||||
SAU_INIT_REGION(2);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
|
||||
SAU_INIT_REGION(3);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
|
||||
SAU_INIT_REGION(4);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
|
||||
SAU_INIT_REGION(5);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
|
||||
SAU_INIT_REGION(6);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
|
||||
SAU_INIT_REGION(7);
|
||||
#endif
|
||||
|
||||
/* repeat this for all possible SAU regions */
|
||||
|
||||
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
|
||||
|
||||
|
||||
#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
|
||||
SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
|
||||
((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
|
||||
#endif
|
||||
|
||||
#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
|
||||
SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
|
||||
((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
|
||||
|
||||
SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
|
||||
SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) |
|
||||
((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
|
||||
((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
|
||||
((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
|
||||
((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
|
||||
#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
|
||||
|
||||
#if defined (__FPU_USED) && (__FPU_USED == 1U) && \
|
||||
defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
|
||||
|
||||
SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
|
||||
((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
|
||||
|
||||
FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
|
||||
((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
|
||||
((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
|
||||
((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
|
||||
NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
|
||||
NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
|
||||
NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
|
||||
NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
|
||||
NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
|
||||
NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
|
||||
NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
#endif /* PARTITION_STM32N657XX_H */
|
||||
504
hw/bsp/stm32n6/stm32n6xx_hal_conf.h
Normal file
504
hw/bsp/stm32n6/stm32n6xx_hal_conf.h
Normal file
@@ -0,0 +1,504 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32n6xx_hal_conf_template.h
|
||||
* @author MCD Application Team
|
||||
* @brief HAL configuration template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to stm32n6xx_hal_conf.h.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32N6xx_HAL_CONF_H
|
||||
#define STM32N6xx_HAL_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* ########################## Module Selection ############################## */
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/
|
||||
#define HAL_MODULE_ENABLED
|
||||
/*#define HAL_ADC_MODULE_ENABLED */
|
||||
/*#define HAL_BSEC_MODULE_ENABLED */
|
||||
/*#define HAL_CRC_MODULE_ENABLED */
|
||||
/*#define HAL_CRYP_MODULE_ENABLED */
|
||||
/*#define HAL_DCMI_MODULE_ENABLED */
|
||||
/*#define HAL_DCMIPP_MODULE_ENABLED */
|
||||
/*#define HAL_DMA2D_MODULE_ENABLED */
|
||||
/*#define HAL_DTS_MODULE_ENABLED */
|
||||
/*#define HAL_ETH_MODULE_ENABLED */
|
||||
/*#define HAL_EXTI_MODULE_ENABLED */
|
||||
/*#define HAL_FDCAN_MODULE_ENABLED */
|
||||
/*#define HAL_GFXMMU_MODULE_ENABLED */
|
||||
/*#define HAL_GFXTIM_MODULE_ENABLED */
|
||||
/*#define HAL_HASH_MODULE_ENABLED */
|
||||
/*#define HAL_HCD_MODULE_ENABLED */
|
||||
#define HAL_I2C_MODULE_ENABLED
|
||||
/*#define HAL_I2S_MODULE_ENABLED */
|
||||
/*#define HAL_I3C_MODULE_ENABLED */
|
||||
/*#define HAL_ICACHE_MODULE_ENABLED */
|
||||
/*#define HAL_IRDA_MODULE_ENABLED */
|
||||
/*#define HAL_IWDG_MODULE_ENABLED */
|
||||
/*#define HAL_JPEG_MODULE_ENABLED */
|
||||
/*#define HAL_LPTIM_MODULE_ENABLED */
|
||||
/*#define HAL_LTDC_MODULE_ENABLED */
|
||||
/*#define HAL_MCE_MODULE_ENABLED */
|
||||
/*#define HAL_MDF_MODULE_ENABLED */
|
||||
/*#define HAL_MMC_MODULE_ENABLED */
|
||||
/*#define HAL_NAND_MODULE_ENABLED */
|
||||
/*#define HAL_NOR_MODULE_ENABLED */
|
||||
/*#define HAL_PCD_MODULE_ENABLED */
|
||||
/*#define HAL_PKA_MODULE_ENABLED */
|
||||
/*#define HAL_PSSI_MODULE_ENABLED */
|
||||
/*#define HAL_RAMCFG_MODULE_ENABLED */
|
||||
/*#define HAL_RIF_MODULE_ENABLED */
|
||||
/*#define HAL_RNG_MODULE_ENABLED */
|
||||
/*#define HAL_RTC_MODULE_ENABLED */
|
||||
/*#define HAL_SAI_MODULE_ENABLED */
|
||||
/*#define HAL_SD_MODULE_ENABLED */
|
||||
/*#define HAL_SDIO_MODULE_ENABLED */
|
||||
/*#define HAL_SDRAM_MODULE_ENABLED */
|
||||
/*#define HAL_SMARTCARD_MODULE_ENABLED*/
|
||||
/*#define HAL_SMBUS_MODULE_ENABLED */
|
||||
/*#define HAL_SPDIFRX_MODULE_ENABLED */
|
||||
/*#define HAL_SPI_MODULE_ENABLED */
|
||||
/*#define HAL_SRAM_MODULE_ENABLED */
|
||||
/*#define HAL_TIM_MODULE_ENABLED */
|
||||
#define HAL_UART_MODULE_ENABLED
|
||||
/*#define HAL_USART_MODULE_ENABLED */
|
||||
/*#define HAL_WWDG_MODULE_ENABLED */
|
||||
/*#define HAL_XSPI_MODULE_ENABLED */
|
||||
/*#define HAL_CACHEAXI_MODULE_ENABLED */
|
||||
/*#define HAL_MDIOS_MODULE_ENABLED */
|
||||
/*#define HAL_GPU2D_MODULE_ENABLED */
|
||||
/*#define HAL_CACHEAXI_MODULE_ENABLED */
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
#define HAL_EXTI_MODULE_ENABLED
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
#define HAL_RCC_MODULE_ENABLED
|
||||
#define HAL_PWR_MODULE_ENABLED
|
||||
#define HAL_CORTEX_MODULE_ENABLED
|
||||
|
||||
/* ########################## Oscillator Values adaptation ####################*/
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE 48000000UL /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
* This value is used by the UART, RTC HAL module to compute the system frequency
|
||||
*/
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz */
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||
#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */
|
||||
#endif /* LSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal Multiple Speed oscillator (MSI) default value.
|
||||
* This value is the default MSI range value after Reset.
|
||||
*/
|
||||
#if !defined (MSI_VALUE)
|
||||
#define MSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz */
|
||||
#endif /* MSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE 64000000UL /*!< Value of the Internal oscillator in Hz */
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI) value.
|
||||
*/
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz */
|
||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz */
|
||||
/* The real value may vary depending on the variations in voltage and temperature.*/
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||
|
||||
/* ########################### System Configuration ######################### */
|
||||
/**
|
||||
* @brief This is the HAL system configuration section
|
||||
*/
|
||||
#define VDD_VALUE 3300UL /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY 15U /*!< tick interrupt priority (lowest by default) */
|
||||
#define USE_RTOS 0U
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
*/
|
||||
/* #define USE_FULL_ASSERT 1U */
|
||||
|
||||
/* ################## Register callback feature configuration ############### */
|
||||
/**
|
||||
* @brief Set below the peripheral configuration to "1U" to add the support
|
||||
* of HAL callback registration/unregistration feature for the HAL
|
||||
* driver(s). This allows user application to provide specific callback
|
||||
* functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
|
||||
* the default weak callback functions (see each stm32n6xx_hal_ppp.h file
|
||||
* for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
|
||||
* for each PPP peripheral).
|
||||
*/
|
||||
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
|
||||
#define USE_HAL_CACHEAXI_REGISTER_CALLBACKS 0U /* CACHEAXI register callback disabled */
|
||||
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
|
||||
#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
|
||||
#define USE_HAL_DCMIPP_REGISTER_CALLBACKS 0U /* DCMIPP register callback disabled */
|
||||
#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
|
||||
#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */
|
||||
#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
|
||||
#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */
|
||||
#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */
|
||||
#define USE_HAL_GFXTIM_REGISTER_CALLBACKS 0U /* GFXTIM register callback disabled */
|
||||
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
|
||||
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
|
||||
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
|
||||
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
|
||||
#define USE_HAL_I3C_REGISTER_CALLBACKS 0U /* I3C register callback disabled */
|
||||
#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */
|
||||
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
|
||||
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
|
||||
#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
|
||||
#define USE_HAL_MCE_REGISTER_CALLBACKS 0U /* MCE register callback disabled */
|
||||
#define USE_HAL_MDF_REGISTER_CALLBACKS 0U /* MDF register callback disabled */
|
||||
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
|
||||
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
|
||||
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
|
||||
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
|
||||
#define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */
|
||||
#define USE_HAL_PSSI_REGISTER_CALLBACKS 0U /* PSSI register callback disabled */
|
||||
#define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */
|
||||
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
|
||||
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
|
||||
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
|
||||
#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
|
||||
#define USE_HAL_SDIO_REGISTER_CALLBACKS 0U /* SDIO register callback disabled */
|
||||
#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
|
||||
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
|
||||
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
|
||||
#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
|
||||
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
|
||||
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
|
||||
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
|
||||
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
|
||||
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
|
||||
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
|
||||
#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U /* XSPI register callback disabled */
|
||||
|
||||
/* ################## SPI peripheral configuration ########################## */
|
||||
|
||||
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
|
||||
* Activated: CRC code is present inside driver
|
||||
* Deactivated: CRC code cleaned from driver
|
||||
*/
|
||||
#define USE_SPI_CRC 0U
|
||||
|
||||
/* ################## SDMMC peripheral configuration ######################### */
|
||||
|
||||
#define USE_SD_TRANSCEIVER 0U
|
||||
|
||||
/* ################## SDIO peripheral configuration ########################## */
|
||||
#define USE_SDIO_TRANSCEIVER 1U
|
||||
#define SDIO_MAX_IO_NUMBER 7U /*!< SDIO device support maximum IO number */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_rcc.h"
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RIF_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_rif.h"
|
||||
#endif /* HAL_RIF_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_dma.h"
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CACHEAXI_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_cacheaxi.h"
|
||||
#endif /* HAL_CACHEAXI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_cortex.h"
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_adc.h"
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_BSEC_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_bsec.h"
|
||||
#endif /* HAL_BSEC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_crc.h"
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRYP_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_cryp.h"
|
||||
#endif /* HAL_CRYP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DCMI_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_dcmi.h"
|
||||
#endif /* HAL_DCMI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DCMIPP_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_dcmipp.h"
|
||||
#endif /* HAL_DCMIPP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA2D_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_dma2d.h"
|
||||
#endif /* HAL_DMA2D_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DTS_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_dts.h"
|
||||
#endif /* HAL_DTS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ETH_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_eth.h"
|
||||
#endif /* HAL_ETH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_exti.h"
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FDCAN_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_fdcan.h"
|
||||
#endif /* HAL_FDCAN_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GFXMMU_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_gfxmmu.h"
|
||||
#endif /* HAL_GFXMMU_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GFXTIM_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_gfxtim.h"
|
||||
#endif /* HAL_GFXTIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPU2D_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_gpu2d.h"
|
||||
#endif /* HAL_GPU2D_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HASH_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_hash.h"
|
||||
#endif /* HAL_HASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HCD_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_hcd.h"
|
||||
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_i2c.h"
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_i2s.h"
|
||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I3C_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_i3c.h"
|
||||
#endif /* HAL_I3C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ICACHE_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_icache.h"
|
||||
#endif /* HAL_ICACHE_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_irda.h"
|
||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_iwdg.h"
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_JPEG_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_jpeg.h"
|
||||
#endif /* HAL_JPEG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LPTIM_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_lptim.h"
|
||||
#endif /* HAL_LPTIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LTDC_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_ltdc.h"
|
||||
#endif /* HAL_LTDC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MCE_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_mce.h"
|
||||
#endif /* HAL_MCE_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MDF_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_mdf.h"
|
||||
#endif /* HAL_MDF_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MDIOS_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_mdios.h"
|
||||
#endif /* HAL_MDIOS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MMC_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_mmc.h"
|
||||
#endif /* HAL_MMC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NAND_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_nand.h"
|
||||
#endif /* HAL_NAND_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NOR_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_nor.h"
|
||||
#endif /* HAL_NOR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NAND_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_nand.h"
|
||||
#endif /* HAL_NAND_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_pcd.h"
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PKA_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_pka.h"
|
||||
#endif /* HAL_PKA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PSSI_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_pssi.h"
|
||||
#endif /* HAL_PSSI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_pwr.h"
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RAMCFG_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_ramcfg.h"
|
||||
#endif /* HAL_RAMCFG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RNG_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_rng.h"
|
||||
#endif /* HAL_RNG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_rtc.h"
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SAI_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_sai.h"
|
||||
#endif /* HAL_SAI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SD_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_sd.h"
|
||||
#endif /* HAL_SD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SDIO_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_sdio.h"
|
||||
#endif /* HAL_SDIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SDRAM_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_sdram.h"
|
||||
#endif /* HAL_SDRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_smartcard.h"
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMBUS_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_smbus.h"
|
||||
#endif /* HAL_SMBUS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPDIFRX_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_spdifrx.h"
|
||||
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_spi.h"
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_sram.h"
|
||||
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_tim.h"
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_uart.h"
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_usart.h"
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_wwdg.h"
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_XSPI_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_xspi.h"
|
||||
#endif /* HAL_XSPI_MODULE_ENABLED */
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t *file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32N6xx_HAL_CONF_H */
|
||||
@@ -1 +1,2 @@
|
||||
set(pca10056_BOARD_ALIAS nrf52840dk/nrf52840)
|
||||
set(stm32n657nucleo_BOARD_ALIAS nucleo_n657x0_q)
|
||||
|
||||
@@ -312,7 +312,7 @@
|
||||
#define TUP_USBIP_FSDEV_STM32
|
||||
#define TUP_DCD_ENDPOINT_MAX 8
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_STM32H7RS)
|
||||
#elif TU_CHECK_MCU(OPT_MCU_STM32H7RS, OPT_MCU_STM32N6)
|
||||
#define TUP_USBIP_DWC2
|
||||
#define TUP_USBIP_DWC2_STM32
|
||||
|
||||
|
||||
@@ -425,6 +425,11 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
|
||||
// Clear A override, force B Valid
|
||||
dwc2->gotgctl = (dwc2->gotgctl & ~GOTGCTL_AVALOEN) | GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL;
|
||||
|
||||
#if CFG_TUSB_MCU == OPT_MCU_STM32N6
|
||||
// No hardware detection of Vbus B-session is available on the STM32N6
|
||||
dwc2->stm32_gccfg |= STM32_GCCFG_VBVALOVAL;
|
||||
#endif
|
||||
|
||||
// Enable required interrupts
|
||||
dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM;
|
||||
|
||||
|
||||
@@ -1,58 +1,58 @@
|
||||
| | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | ST F207/F407/411/429 FS | ST F407/429 HS | ST F412/76x FS | ST F723/L4P5 FS | ST F723 HS | ST F76x HS | ST H743/H750 | ST L476 FS | ST U5A5/H7RS HS | XMC4500 | GD32VF103 |
|
||||
|:---------------------------|:----------------|:-------------|:--------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:------------------|:-------------|:------------|
|
||||
| GUID | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00AEC000 | 0x00001000 |
|
||||
| GSNPSID | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x4F54292A | 0x00000000 |
|
||||
| - specs version | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 2.92a | 0.00W |
|
||||
| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 |
|
||||
| GHWCFG2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x228F5930 | 0x00000000 |
|
||||
| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP |
|
||||
| - arch | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | DMA internal | Slave only |
|
||||
| - single_point | hub | hub | n/a | hub | n/a | hub | n/a | n/a | hub | hub | hub | n/a | hub | n/a | hub |
|
||||
| - hs_phy_type | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a |
|
||||
| - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | Dedicated | n/a |
|
||||
| - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 |
|
||||
| - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 13 | 0 |
|
||||
| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
|
||||
| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
|
||||
| - mul_proc_intrpt | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
|
||||
| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - nptx_q_depth | 8 | 8 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 |
|
||||
| - ptx_q_depth | 8 | 8 | 8 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 |
|
||||
| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 |
|
||||
| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| GHWCFG3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x027A01E5 | 0x00000000 |
|
||||
| - xfer_size_width | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 5 | 0 |
|
||||
| - packet_size_width | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 |
|
||||
| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
|
||||
| - i2c_enable | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
|
||||
| - vendor_ctrl_itf | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 |
|
||||
| - optional_feature_removed | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - synch_reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - otg_adp_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
|
||||
| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - battery_charger_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
|
||||
| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
|
||||
| - dfifo_depth | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 634 | 0 |
|
||||
| GHWCFG4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0xDBF08030 | 0x00000000 |
|
||||
| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
|
||||
| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
|
||||
| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
|
||||
| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
|
||||
| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
|
||||
| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
|
||||
| - enhanced_lpm_support | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
|
||||
| - phy_data_width | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8/16 bit | 8 bit |
|
||||
| - ctrl_ep_num | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
|
||||
| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
|
||||
| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
|
||||
| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
|
||||
| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
|
||||
| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
|
||||
| - num_dev_in_eps | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 |
|
||||
| - dma_desc_enable | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |
|
||||
| - dma_desc_dynamic | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |
|
||||
| | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | ST F207/F407/411/429 FS | ST F407/429 HS | ST F412/76x FS | ST F723/L4P5 FS | ST F723 HS | ST F76x HS | ST H743/H750 | ST L476 FS | ST U5A5/H7RS/N6 HS | XMC4500 | GD32VF103 |
|
||||
|:---------------------------|:----------------|:-------------|:--------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:---------------------|:-------------|:------------|
|
||||
| GUID | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00AEC000 | 0x00001000 |
|
||||
| GSNPSID | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x4F54292A | 0x00000000 |
|
||||
| - specs version | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 2.92a | 0.00W |
|
||||
| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 |
|
||||
| GHWCFG2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x228F5930 | 0x00000000 |
|
||||
| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP |
|
||||
| - arch | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | DMA internal | Slave only |
|
||||
| - single_point | hub | hub | n/a | hub | n/a | hub | n/a | n/a | hub | hub | hub | n/a | hub | n/a | hub |
|
||||
| - hs_phy_type | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a |
|
||||
| - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | Dedicated | n/a |
|
||||
| - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 |
|
||||
| - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 13 | 0 |
|
||||
| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
|
||||
| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
|
||||
| - mul_proc_intrpt | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
|
||||
| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - nptx_q_depth | 8 | 8 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 |
|
||||
| - ptx_q_depth | 8 | 8 | 8 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 |
|
||||
| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 |
|
||||
| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| GHWCFG3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x027A01E5 | 0x00000000 |
|
||||
| - xfer_size_width | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 5 | 0 |
|
||||
| - packet_size_width | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 |
|
||||
| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
|
||||
| - i2c_enable | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
|
||||
| - vendor_ctrl_itf | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 |
|
||||
| - optional_feature_removed | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - synch_reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - otg_adp_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
|
||||
| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - battery_charger_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
|
||||
| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
|
||||
| - dfifo_depth | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 634 | 0 |
|
||||
| GHWCFG4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0xDBF08030 | 0x00000000 |
|
||||
| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
|
||||
| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
|
||||
| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
|
||||
| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
|
||||
| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
|
||||
| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
|
||||
| - enhanced_lpm_support | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
|
||||
| - phy_data_width | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8/16 bit | 8 bit |
|
||||
| - ctrl_ep_num | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
|
||||
| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
|
||||
| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
|
||||
| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
|
||||
| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
|
||||
| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
|
||||
| - num_dev_in_eps | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 |
|
||||
| - dma_desc_enable | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |
|
||||
| - dma_desc_dynamic | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |
|
||||
|
||||
@@ -21,7 +21,7 @@ dwc2_reg_value = {
|
||||
'ST F76x HS': [0x2100, 0x4F54320A, 0, 0x229FE190, 0x03EED2E8, 0x23F00030],
|
||||
'ST H743/H750': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x03B8D2E8, 0xE3F00030],
|
||||
'ST L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
|
||||
'ST U5A5/H7RS HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30],
|
||||
'ST U5A5/H7RS/N6 HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30],
|
||||
'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x027A01E5, 0xDBF08030],
|
||||
'GD32VF103': [0x1000, 0, 0, 0, 0, 0],
|
||||
}
|
||||
|
||||
@@ -77,6 +77,17 @@ extern "C" {
|
||||
#define EP_MAX_HS 9
|
||||
#define EP_FIFO_SIZE_HS 4096
|
||||
|
||||
#elif CFG_TUSB_MCU == OPT_MCU_STM32N6
|
||||
#include "stm32n6xx.h"
|
||||
#define EP_MAX_FS 9
|
||||
#define EP_FIFO_SIZE_FS 4096
|
||||
|
||||
#define EP_MAX_HS 9
|
||||
#define EP_FIFO_SIZE_HS 4096
|
||||
|
||||
#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_BASE
|
||||
#define OTG_HS_IRQn USB1_OTG_HS_IRQn
|
||||
|
||||
#elif CFG_TUSB_MCU == OPT_MCU_STM32F7
|
||||
#include "stm32f7xx.h"
|
||||
#define EP_MAX_FS 6
|
||||
|
||||
@@ -381,6 +381,10 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
|
||||
|
||||
// force host mode and wait for mode switch
|
||||
dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FDMOD) | GUSBCFG_FHMOD;
|
||||
#if CFG_TUSB_MCU == OPT_MCU_STM32N6
|
||||
// No hardware detection of Vbus B-session is available on the STM32N6
|
||||
dwc2->stm32_gccfg &= ~STM32_GCCFG_VBVALOVAL;
|
||||
#endif
|
||||
while ((dwc2->gintsts & GINTSTS_CMOD) != GINTSTS_CMODE_HOST) {}
|
||||
|
||||
// configure fixed-allocated fifo scheme
|
||||
|
||||
@@ -94,6 +94,7 @@
|
||||
#define OPT_MCU_STM32U0 316 ///< ST U0
|
||||
#define OPT_MCU_STM32H7RS 317 ///< ST F7RS
|
||||
#define OPT_MCU_STM32C0 318 ///< ST C0
|
||||
#define OPT_MCU_STM32N6 319 ///< ST N6
|
||||
|
||||
// Sony
|
||||
#define OPT_MCU_CXD56 400 ///< SONY CXD56
|
||||
|
||||
@@ -58,8 +58,8 @@ deps_optional = {
|
||||
'hw/mcu/nxp/mcux-sdk': ['https://github.com/nxp-mcuxpresso/mcux-sdk',
|
||||
'a1bdae309a14ec95a4f64a96d3315a4f89c397c6',
|
||||
'kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt'],
|
||||
'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/hathach/Pico-PIO-USB.git',
|
||||
'032a469e79f6a4ba40760d7868e6db26e15002d7',
|
||||
'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git',
|
||||
'3c1eec341a5232640e4c00628b889b641af34b28',
|
||||
'rp2040'],
|
||||
'hw/mcu/renesas/fsp': ['https://github.com/renesas/fsp.git',
|
||||
'edcc97d684b6f716728a60d7a6fea049d9870bd6',
|
||||
@@ -121,6 +121,9 @@ deps_optional = {
|
||||
'hw/mcu/st/cmsis_device_l5': ['https://github.com/STMicroelectronics/cmsis_device_l5.git',
|
||||
'd922865fc0326a102c26211c44b8e42f52c1e53d',
|
||||
'stm32l5'],
|
||||
'hw/mcu/st/cmsis_device_n6': ['https://github.com/STMicroelectronics/cmsis-device-n6.git',
|
||||
'f818b00f775444e8d19ef6cad822534c345e054f',
|
||||
'stm32n6'],
|
||||
'hw/mcu/st/cmsis_device_u5': ['https://github.com/STMicroelectronics/cmsis_device_u5.git',
|
||||
'5ad9797c54ec3e55eff770fc9b3cd4a1aefc1309',
|
||||
'stm32u5'],
|
||||
@@ -130,6 +133,9 @@ deps_optional = {
|
||||
'hw/mcu/st/stm32-mfxstm32l152': ['https://github.com/STMicroelectronics/stm32-mfxstm32l152.git',
|
||||
'7f4389efee9c6a655b55e5df3fceef5586b35f9b',
|
||||
'stm32h7'],
|
||||
'hw/mcu/st/stm32-tcpp0203': ['https://github.com/STMicroelectronics/stm32-tcpp0203.git',
|
||||
'9918655bff176ac3046ccf378b5c7bbbc6a38d15',
|
||||
'stm32h7rs stm32n6'],
|
||||
'hw/mcu/st/stm32c0xx_hal_driver': ['https://github.com/STMicroelectronics/stm32c0xx_hal_driver.git',
|
||||
'41253e2f1d7ae4a4d0c379cf63f5bcf71fcf8eb3',
|
||||
'stm32c0'],
|
||||
@@ -178,6 +184,9 @@ deps_optional = {
|
||||
'hw/mcu/st/stm32l5xx_hal_driver': ['https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git',
|
||||
'675c32a75df37f39d50d61f51cb0dcf53f07e1cb',
|
||||
'stm32l5'],
|
||||
'hw/mcu/st/stm32n6xx_hal_driver': ['https://github.com/STMicroelectronics/stm32n6xx-hal-driver.git',
|
||||
'49f9989d10cf6817d4b07ac01848956b46bd0fd6',
|
||||
'stm32n6'],
|
||||
'hw/mcu/st/stm32u5xx_hal_driver': ['https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git',
|
||||
'4d93097a67928e9377e655ddd14622adc31b9770',
|
||||
'stm32u5'],
|
||||
@@ -204,7 +213,7 @@ deps_optional = {
|
||||
'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf saml2x '
|
||||
'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43 '
|
||||
'stm32c0 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5 '
|
||||
'stm32h7 stm32h7rs stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb '
|
||||
'stm32h7 stm32h7rs stm32l0 stm32l1 stm32l4 stm32l5 stm32n6 stm32u5 stm32wb '
|
||||
'sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg '
|
||||
'tm4c '],
|
||||
'lib/CMSIS_6': ['https://github.com/ARM-software/CMSIS_6.git',
|
||||
|
||||
Reference in New Issue
Block a user