dwc2 only enter critical in isr with multiple core CPUs
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@@ -369,6 +369,10 @@
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#define TUP_DCD_ENDPOINT_MAX 7 // only 5 TX FIFO for endpoint IN
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#define CFG_TUSB_OS_INC_PATH_DEFAULT freertos/
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#if CFG_TUSB_MCU == OPT_MCU_ESP32S3
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#define TUP_MCU_MULTIPLE_CORE 1
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#endif
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// Disable slave if DMA is enabled
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#define CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUD_DWC2_DMA_ENABLE
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#define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUH_DWC2_DMA_ENABLE
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@@ -381,6 +385,8 @@
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#define CFG_TUSB_OS_INC_PATH_DEFAULT freertos/
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#define TUP_MCU_MULTIPLE_CORE 1
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// Disable slave if DMA is enabled
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#define CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUD_DWC2_DMA_ENABLE
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#define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUH_DWC2_DMA_ENABLE
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@@ -410,6 +416,7 @@
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#elif TU_CHECK_MCU(OPT_MCU_RP2040)
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#define TUP_DCD_EDPT_ISO_ALLOC
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#define TUP_DCD_ENDPOINT_MAX 16
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#define TUP_MCU_MULTIPLE_CORE 1
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#define TU_ATTR_FAST_FUNC __attribute__((section(".time_critical.tinyusb")))
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@@ -539,6 +539,7 @@ void dcd_edpt_close_all(uint8_t rhport) {
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uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
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osal_critical_enter(&_dcd_critical);
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_dcd_data.allocated_epin_count = 0;
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// Disable non-control interrupt
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@@ -556,8 +557,8 @@ void dcd_edpt_close_all(uint8_t rhport) {
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dfifo_flush_tx(dwc2, 0x10); // all tx fifo
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dfifo_flush_rx(dwc2);
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dfifo_device_init(rhport); // re-init dfifo
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osal_critical_exit(&_dcd_critical);
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}
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@@ -577,7 +578,6 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
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bool ret;
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osal_critical_enter(&_dcd_critical);
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@@ -596,7 +596,6 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
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// Schedule packets to be sent within interrupt
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edpt_schedule_packets(rhport, epnum, dir);
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ret = true;
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}
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@@ -616,7 +615,6 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
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bool ret;
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osal_critical_enter(&_dcd_critical);
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@@ -631,7 +629,6 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t
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// Schedule packets to be sent within interrupt
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// TODO xfer fifo may only available for slave mode
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edpt_schedule_packets(rhport, epnum, dir);
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ret = true;
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}
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@@ -1017,16 +1014,21 @@ static void handle_ep_irq(uint8_t rhport, uint8_t dir) {
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*/
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void dcd_int_handler(uint8_t rhport) {
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dwc2_regs_t* dwc2 = DWC2_REG(rhport);
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const uint32_t gintmask = dwc2->gintmsk;
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const uint32_t gintsts = dwc2->gintsts & gintmask;
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if (gintsts & GINTSTS_USBRST) {
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// USBRST is start of reset.
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#if TUP_MCU_MULTIPLE_CORE
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osal_critical_enter(&_dcd_critical);
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#endif
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dwc2->gintsts = GINTSTS_USBRST;
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handle_bus_reset(rhport);
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#if TUP_MCU_MULTIPLE_CORE
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osal_critical_exit(&_dcd_critical);
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#endif
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}
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if (gintsts & GINTSTS_ENUMDNE) {
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