dwc2 only enter critical in isr with multiple core CPUs
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@@ -369,6 +369,10 @@
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#define TUP_DCD_ENDPOINT_MAX 7 // only 5 TX FIFO for endpoint IN
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#define CFG_TUSB_OS_INC_PATH_DEFAULT freertos/
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#if CFG_TUSB_MCU == OPT_MCU_ESP32S3
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#define TUP_MCU_MULTIPLE_CORE 1
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#endif
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// Disable slave if DMA is enabled
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#define CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUD_DWC2_DMA_ENABLE
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#define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUH_DWC2_DMA_ENABLE
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@@ -381,6 +385,8 @@
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#define CFG_TUSB_OS_INC_PATH_DEFAULT freertos/
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#define TUP_MCU_MULTIPLE_CORE 1
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// Disable slave if DMA is enabled
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#define CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUD_DWC2_DMA_ENABLE
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#define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUH_DWC2_DMA_ENABLE
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@@ -410,6 +416,7 @@
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#elif TU_CHECK_MCU(OPT_MCU_RP2040)
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#define TUP_DCD_EDPT_ISO_ALLOC
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#define TUP_DCD_ENDPOINT_MAX 16
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#define TUP_MCU_MULTIPLE_CORE 1
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#define TU_ATTR_FAST_FUNC __attribute__((section(".time_critical.tinyusb")))
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