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dwc2 only enter critical in isr with multiple core CPUs

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hathach
2025-05-19 18:57:39 +07:00
parent 72ee742761
commit 9aea7751f2
2 changed files with 15 additions and 6 deletions
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7
src/common/tusb_mcu.h
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@@ -369,6 +369,10 @@
#define TUP_DCD_ENDPOINT_MAX 7 // only 5 TX FIFO for endpoint IN
#define CFG_TUSB_OS_INC_PATH_DEFAULT freertos/
#if CFG_TUSB_MCU == OPT_MCU_ESP32S3
#define TUP_MCU_MULTIPLE_CORE 1
#endif
// Disable slave if DMA is enabled
#define CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUH_DWC2_DMA_ENABLE
@@ -381,6 +385,8 @@
#define CFG_TUSB_OS_INC_PATH_DEFAULT freertos/
#define TUP_MCU_MULTIPLE_CORE 1
// Disable slave if DMA is enabled
#define CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUH_DWC2_DMA_ENABLE
@@ -410,6 +416,7 @@
#elif TU_CHECK_MCU(OPT_MCU_RP2040)
#define TUP_DCD_EDPT_ISO_ALLOC
#define TUP_DCD_ENDPOINT_MAX 16
#define TUP_MCU_MULTIPLE_CORE 1
#define TU_ATTR_FAST_FUNC __attribute__((section(".time_critical.tinyusb")))