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dma rx works well

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This commit is contained in:
hathach
2023-06-08 13:37:37 +07:00
parent fc761953b3
commit 9c2a8490af
3 changed files with 267 additions and 14 deletions
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80
src/portable/st/typec/typec_stm32.c
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@@ -31,6 +31,7 @@
#if CFG_TUSB_MCU == OPT_MCU_STM32G4
#include "stm32g4xx.h"
#include "stm32g4xx_hal_dma.h"
#else
#error "Unsupported STM32 family"
#endif
@@ -61,13 +62,46 @@ static uint32_t rx_count = 0;
static uint8_t tx_buf[262] TU_ATTR_ALIGNED(4);
static uint32_t tx_count;
#define CFG_TUC_STM32_DMA_RX { DMA1_Channel1 }
//#define CFG_TUC_STM32_DMA_TX { DMA1_Channel2 }
#ifdef CFG_TUC_STM32_DMA_RX
static DMA_Channel_TypeDef* dma_rx_arr[TUP_TYPEC_RHPORTS_NUM] = CFG_TUC_STM32_DMA_RX;
TU_ATTR_ALWAYS_INLINE static inline
void dma_rx_start(uint8_t rhport)
{
DMA_Channel_TypeDef* dma_rx_ch = dma_rx_arr[rhport];
dma_rx_ch->CMAR = (uint32_t) rx_buf;
dma_rx_ch->CNDTR = sizeof(rx_buf);
dma_rx_ch->CCR |= DMA_CCR_EN;
}
#endif
#ifdef CFG_TUC_STM32_DMA_TX
static DMA_Channel_TypeDef* dma_tx_arr[TUP_TYPEC_RHPORTS_NUM] = CFG_TUC_STM32_DMA_TX;
#endif
//--------------------------------------------------------------------+
//
//--------------------------------------------------------------------+
#include "stm32g4xx_ll_dma.h"
bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
(void) rhport;
#ifdef CFG_TUC_STM32_DMA_RX
// Init DMA
DMA_Channel_TypeDef* dma_rx_ch = dma_rx_arr[rhport];
// Peripheral -> Memory, Memory inc, 8-bit, High priority
dma_rx_ch->CCR = DMA_CCR_MINC | DMA_CCR_PL_1;
dma_rx_ch->CPAR = (uint32_t) &UCPD1->RXDR;
LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_1, LL_DMAMUX_REQ_UCPD1_RX);
#endif
// Initialization phase: CFG1
UCPD1->CFG1 = (0x0d << UCPD_CFG1_HBITCLKDIV_Pos) | (0x10 << UCPD_CFG1_IFRGAP_Pos) | (0x07 << UCPD_CFG1_TRANSWIN_Pos) |
(0x01 << UCPD_CFG1_PSC_UCPDCLK_Pos) | (0x1f << UCPD_CFG1_RXORDSETEN_Pos) |
@@ -77,7 +111,7 @@ bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
// General programming sequence (with UCPD configured then enabled)
if (port_type == TUSB_TYPEC_PORT_SNK) {
// Enable both CC Phy
UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | (0x03 << UCPD_CR_CCENABLE_Pos);
UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1;
// Read Voltage State on CC1 & CC2 fore initial state
uint32_t vstate_cc[2];
@@ -135,30 +169,48 @@ void tcd_int_handler(uint8_t rhport) {
TU_LOG1("VState CC1 = %u, CC2 = %u\n", vstate_cc[0], vstate_cc[1]);
uint32_t cr = UCPD1->CR;
uint32_t cfg1 = UCPD1->CFG1;
// TODO only support SNK for now, required highest voltage for now
// Enable PHY on correct CC and disable Rd on other CC
if ((sr & UCPD_SR_TYPECEVT1) && (vstate_cc[0] == 3)) {
TU_LOG1("Attach CC1\n");
cr &= ~UCPD_CR_PHYCCSEL;
cr |= UCPD_CR_PHYRXEN;
cr &= ~(UCPD_CR_PHYCCSEL | UCPD_CR_CCENABLE);
cr |= UCPD_CR_PHYRXEN | UCPD_CR_CCENABLE_0;
} else if ((sr & UCPD_SR_TYPECEVT2) && (vstate_cc[1] == 3)) {
TU_LOG1("Attach CC2\n");
cr |= UCPD_CR_PHYCCSEL;
cr |= UCPD_CR_PHYRXEN;
cr &= ~UCPD_CR_CCENABLE;
cr |= (UCPD_CR_PHYCCSEL | UCPD_CR_PHYRXEN | UCPD_CR_CCENABLE_1);
} else {
TU_LOG1("Detach\n");
cr &= ~UCPD_CR_PHYRXEN;
cr |= UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1;
}
if (cr & UCPD_CR_PHYRXEN) {
// Enable Interrupt
UCPD1->IMR |= UCPD_IMR_TXISIE | UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
UCPD_IMR_RXNEIE | UCPD_IMR_RXORDDETIE | UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE |
UCPD_IMR_RXMSGENDIE | UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE;
uint32_t imr = UCPD1->IMR;
imr |= UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | UCPD_IMR_RXMSGENDIE | UCPD_IMR_RXORDDETIE |
UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE | UCPD_IMR_FRSEVTIE;
#ifdef CFG_TUC_STM32_DMA_RX
cfg1 |= UCPD_CFG1_RXDMAEN;
dma_rx_start(rhport);
#else
imr |= UCPD_IMR_RXNEIE | UCPD_IMR_RXORDDETIE;
#endif
#ifndef CFG_TUC_STM32_DMA_TX
imr |= UCPD_IMR_TXISIE;
#endif
UCPD1->IMR = imr;
}
// Enable PD RX
UCPD1->CR = cr;
UCPD1->CFG1 = cfg1;
// ack
UCPD1->ICR = UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF;
@@ -176,6 +228,7 @@ void tcd_int_handler(uint8_t rhport) {
UCPD1->ICR = UCPD_ICR_RXORDDETCF;
}
#ifndef CFG_TUC_STM32_DMA_RX
if (sr & UCPD_SR_RXNE) {
// TODO DMA later
do {
@@ -184,8 +237,9 @@ void tcd_int_handler(uint8_t rhport) {
// no ack needed
}
#endif
// End of message
// Received full message
if (sr & UCPD_SR_RXMSGEND) {
// Skip if CRC failed
@@ -213,13 +267,17 @@ void tcd_int_handler(uint8_t rhport) {
// notify stack after good crc ?
}
#ifdef CFG_TUC_STM32_DMA_RX
// prepare next receive
dma_rx_start(rhport);
#endif
// ack
UCPD1->ICR = UCPD_ICR_RXMSGENDCF;
}
if (sr & UCPD_SR_RXOVR) {
TU_LOG1("RXOVR\n");
TU_LOG1_HEX(rx_count);
// ack
UCPD1->ICR = UCPD_ICR_RXOVRCF;
}