revert (unverified) second race condition
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		@@ -77,18 +77,6 @@
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  #endif
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					  #endif
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#endif
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					#endif
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/** disable interrupts */
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#define DISABLE_IRQ()                \
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    uint32_t prim = __get_PRIMASK(); \
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    __disable_irq();
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/** (re)enable interrupts */
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#define ENABLE_IRQ()    \
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    if (!prim)          \
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    {                   \
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      __enable_irq();   \
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    }
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/*------------------------------------------------------------------*/
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					/*------------------------------------------------------------------*/
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/* MACRO TYPEDEF CONSTANT ENUM
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					/* MACRO TYPEDEF CONSTANT ENUM
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 *------------------------------------------------------------------*/
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					 *------------------------------------------------------------------*/
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@@ -446,15 +434,11 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
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  bool const control_status = (epnum == 0 && total_bytes == 0 && dir != tu_edpt_dir(NRF_USBD->BMREQUESTTYPE));
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					  bool const control_status = (epnum == 0 && total_bytes == 0 && dir != tu_edpt_dir(NRF_USBD->BMREQUESTTYPE));
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  if (control_status) {
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					  if (control_status) {
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    DISABLE_IRQ();
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    // Status Phase also requires EasyDMA has to be available as well !!!!
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					    // Status Phase also requires EasyDMA has to be available as well !!!!
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    edpt_dma_start(&NRF_USBD->TASKS_EP0STATUS);
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					    edpt_dma_start(&NRF_USBD->TASKS_EP0STATUS);
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    // The nRF doesn't interrupt on status transmit so we queue up a success response.
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					    // The nRF doesn't interrupt on status transmit so we queue up a success response.
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    dcd_event_xfer_complete(0, ep_addr, 0, XFER_RESULT_SUCCESS, is_in_isr());
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					    dcd_event_xfer_complete(0, ep_addr, 0, XFER_RESULT_SUCCESS, is_in_isr());
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    ENABLE_IRQ();
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  } else if (dir == TUSB_DIR_OUT) {
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					  } else if (dir == TUSB_DIR_OUT) {
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    xfer->started = true;
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					    xfer->started = true;
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    if (epnum == 0) {
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					    if (epnum == 0) {
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