Merge pull request #2881 from hathach/enhance-dwc2-dcd

This commit is contained in:
Ha Thach
2024-11-19 05:08:07 +07:00
committed by GitHub
9 changed files with 561 additions and 409 deletions

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@@ -248,13 +248,17 @@
// USBIP
//--------------------------------------------------------------------+
#ifndef CFG_TUD_DWC2_SLAVE_ENABLE
#define CFG_TUD_DWC2_SLAVE_ENABLE 1
#endif
// DWC2 controller: use DMA for data transfer
// For processors with data cache enabled, USB endpoint buffer region
// (defined by CFG_TUSB_MEM_SECTION) must be declared as non-cacheable.
// For example, on Cortex-M7 the MPU region can be configured as normal
// non-cacheable, with RASR register value: TEX=1 C=0 B=0 S=0.
#ifndef CFG_TUD_DWC2_DMA
#define CFG_TUD_DWC2_DMA 0
#ifndef CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUD_DWC2_DMA_ENABLE 0
#endif
// Enable DWC2 Slave mode for host