@@ -208,6 +208,27 @@ deps_optional = {
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'hw/mcu/wch/ch32f20x': ['https://github.com/openwch/ch32f20x.git',
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'77c4095087e5ed2c548ec9058e655d0b8757663b',
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'ch32f20x'],
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'hw/mcu/artery/at32f403a_407': ['https://github.com/ArteryTek/AT32F403A_407_Firmware_Library.git',
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'f2cb360c3d28fada76b374308b8c4c61d37a090b',
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'at32f403a_407'],
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||||
'hw/mcu/artery/at32f415': ['https://github.com/ArteryTek/AT32F415_Firmware_Library.git',
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||||
'716f545aa1290ff144ccf023a8e797b951e1bc8e',
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||||
'at32f415'],
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||||
'hw/mcu/artery/at32f435_437': ['https://github.com/ArteryTek/AT32F435_437_Firmware_Library.git',
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||||
'25439cc6650a8ae0345934e8707a5f38c7ae41f8',
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'at32f435_437'],
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||||
'hw/mcu/artery/at32f423': ['https://github.com/ArteryTek/AT32F423_Firmware_Library.git',
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||||
'2afa7f12852e57a9e8aab3a892c641e1a8635a18',
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'at32f423'],
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||||
'hw/mcu/artery/at32f402_405': ['https://github.com/ArteryTek/AT32F402_405_Firmware_Library.git',
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||||
'4424515c2663e82438654e0947695295df2abdfe',
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||||
'at32f402_405'],
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||||
'hw/mcu/artery/at32f425': ['https://github.com/ArteryTek/AT32F425_Firmware_Library.git',
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||||
'620233e1357d5c1b7e2bde6b9dd5196822b91817',
|
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'at32f425'],
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||||
'hw/mcu/artery/at32f413': ['https://github.com/ArteryTek/AT32F413_Firmware_Library.git',
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||||
'f6fe62dfec9fd40c5b63d92fc5ef2c2b5e77a450',
|
||||
'at32f413'],
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||||
'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git',
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||||
'2b7495b8535bdcb306dac29b9ded4cfb679d7e5c',
|
||||
'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf saml2x '
|
||||
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