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add lpc40 to cmake

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This commit is contained in:
hathach
2023-07-24 15:18:41 +07:00
parent 8fa0b74d80
commit a268e0b7a3
10 changed files with 179 additions and 20 deletions
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9
hw/bsp/lpc40/boards/ea4088_quickstart/board.cmake Normal file
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set(JLINK_DEVICE LPC4088)
set(PYOCD_TARGET LPC4088)
set(NXPLINK_DEVICE LPC4088:LPC4088)
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc4088.ld)
function(update_board TARGET)
# nothing to do
endfunction()

39
hw/bsp/lpc40/boards/ea4088_quickstart/board.h Normal file
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/*
* The MIT License (MIT)
*
* Copyright (c) 2023 Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#ifndef EA4088QS__BOARD_H
#define EA4088QS__BOARD_H
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif

8
hw/bsp/lpc40/boards/ea4088_quickstart/board.mk Normal file
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LD_FILE = $(BOARD_PATH)/lpc4088.ld
# For flash-jlink target
JLINK_DEVICE = LPC4088
# flash using jlink
flash: flash-jlink

184
hw/bsp/lpc40/boards/ea4088_quickstart/lpc4088.ld Normal file
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/*
* GENERATED FILE - DO NOT EDIT
* (c) Code Red Technologies Ltd, 2008-2013
* (c) NXP Semiconductors 2013-2019
* Generated linker script file for LPC4088
* Created from linkscript.ldt by FMCreateLinkLibraries
* Using Freemarker v2.3.23
* MCUXpresso IDE v10.2.1 [Build 795] [2018-07-25] on May 15, 2019 5:16:07 PM
*/
MEMORY
{
/* Define each memory region */
MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
RamLoc64 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x10000 /* 64K bytes (alias RAM) */
RamPeriph32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */
}
/* Define a symbol for the top of each memory region */
__base_MFlash512 = 0x0 ; /* MFlash512 */
__base_Flash = 0x0 ; /* Flash */
__top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */
__top_Flash = 0x0 + 0x80000 ; /* 512K bytes */
__base_RamLoc64 = 0x10000000 ; /* RamLoc64 */
__base_RAM = 0x10000000 ; /* RAM */
__top_RamLoc64 = 0x10000000 + 0x10000 ; /* 64K bytes */
__top_RAM = 0x10000000 + 0x10000 ; /* 64K bytes */
__base_RamPeriph32 = 0x20000000 ; /* RamPeriph32 */
__base_RAM2 = 0x20000000 ; /* RAM2 */
__top_RamPeriph32 = 0x20000000 + 0x8000 ; /* 32K bytes */
__top_RAM2 = 0x20000000 + 0x8000 ; /* 32K bytes */
ENTRY(ResetISR)
SECTIONS
{
/* MAIN TEXT SECTION */
.text : ALIGN(4)
{
FILL(0xff)
__vectors_start__ = ABSOLUTE(.) ;
KEEP(*(.isr_vector))
/* Global Section Table */
. = ALIGN(4) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
LONG( ADDR(.data));
LONG( SIZEOF(.data));
LONG(LOADADDR(.data_RAM2));
LONG( ADDR(.data_RAM2));
LONG( SIZEOF(.data_RAM2));
__data_section_table_end = .;
__bss_section_table = .;
LONG( ADDR(.bss));
LONG( SIZEOF(.bss));
LONG( ADDR(.bss_RAM2));
LONG( SIZEOF(.bss_RAM2));
__bss_section_table_end = .;
__section_table_end = . ;
/* End of Global Section Table */
*(.after_vectors*)
} > MFlash512
.text : ALIGN(4)
{
*(.text*)
*(.rodata .rodata.* .constdata .constdata.*)
. = ALIGN(4);
} > MFlash512
/*
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
.ARM.extab : ALIGN(4)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash512
__exidx_start = .;
.ARM.exidx : ALIGN(4)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash512
__exidx_end = .;
_etext = .;
/* DATA section for RamPeriph32 */
.data_RAM2 : ALIGN(4)
{
FILL(0xff)
PROVIDE(__start_data_RAM2 = .) ;
*(.ramfunc.$RAM2)
*(.ramfunc.$RamPeriph32)
*(.data.$RAM2*)
*(.data.$RamPeriph32*)
. = ALIGN(4) ;
PROVIDE(__end_data_RAM2 = .) ;
} > RamPeriph32 AT>MFlash512
/* MAIN DATA SECTION */
.uninit_RESERVED : ALIGN(4)
{
KEEP(*(.bss.$RESERVED*))
. = ALIGN(4) ;
_end_uninit_RESERVED = .;
} > RamLoc64
/* Main DATA section (RamLoc64) */
.data : ALIGN(4)
{
FILL(0xff)
_data = . ;
*(vtable)
*(.ramfunc*)
*(.data*)
. = ALIGN(4) ;
_edata = . ;
} > RamLoc64 AT>MFlash512
/* BSS section for RamPeriph32 */
.bss_RAM2 : ALIGN(4)
{
PROVIDE(__start_bss_RAM2 = .) ;
*(.bss.$RAM2*)
*(.bss.$RamPeriph32*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM2 = .) ;
} > RamPeriph32
/* MAIN BSS SECTION */
.bss : ALIGN(4)
{
_bss = .;
*(.bss*)
*(COMMON)
. = ALIGN(4) ;
_ebss = .;
PROVIDE(end = .);
} > RamLoc64
/* NOINIT section for RamPeriph32 */
.noinit_RAM2 (NOLOAD) : ALIGN(4)
{
*(.noinit.$RAM2*)
*(.noinit.$RamPeriph32*)
. = ALIGN(4) ;
} > RamPeriph32
/* DEFAULT NOINIT SECTION */
.noinit (NOLOAD): ALIGN(4)
{
_noinit = .;
*(.noinit*)
. = ALIGN(4) ;
_end_noinit = .;
} > RamLoc64
PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc64 - 0);
/* ## Create checksum value (used in startup) ## */
PROVIDE(__valid_user_code_checksum = 0 -
(_vStackTop
+ (ResetISR + 1)
+ (NMI_Handler + 1)
+ (HardFault_Handler + 1)
+ (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
+ (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
+ (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
) );
/* Provide basic symbols giving location and size of main text
* block, including initial values of RW data sections. Note that
* these will need extending to give a complete picture with
* complex images (e.g multiple Flash banks).
*/
_image_start = LOADADDR(.text);
_image_end = LOADADDR(.data) + SIZEOF(.data);
_image_size = _image_end - _image_start;
}

193
hw/bsp/lpc40/family.c Normal file
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/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#include "chip.h"
#include "bsp/board.h"
#include "board.h"
//--------------------------------------------------------------------+
// USB Interrupt Handler
//--------------------------------------------------------------------+
void USB_IRQHandler(void)
{
#if CFG_TUD_ENABLED
tud_int_handler(0);
#endif
#if CFG_TUH_ENABLED
tuh_int_handler(0);
#endif
}
//--------------------------------------------------------------------+
// MACRO TYPEDEF CONSTANT ENUM DECLARATION
//--------------------------------------------------------------------+
#define LED_PORT 2
#define LED_PIN 19
#define BUTTON_PORT 2
#define BUTTON_PIN 10
#define BUTTON_ACTIV_STATE 0
/* System oscillator rate and RTC oscillator rate */
const uint32_t OscRateIn = 12000000;
const uint32_t RTCOscRateIn = 32768;
/* Pin muxing configuration */
static const PINMUX_GRP_T pinmuxing[] =
{
// LED
{2, 19, (IOCON_FUNC0 | IOCON_MODE_INACT)},
// Button
{2, 10, (IOCON_FUNC0 | IOCON_MODE_INACT | IOCON_MODE_PULLUP)},
};
static const PINMUX_GRP_T pin_usb_mux[] =
{
// USB1 as Host
{0, 29, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // D+1
{0, 30, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // D-1
{1, 18, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // UP LED1
{1, 19, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // PPWR1
// {2, 14, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // VBUS1
// {2, 15, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // OVRCR1
// USB2 as Device
{0, 31, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // D+2
{0, 13, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // UP LED
{0, 14, (IOCON_FUNC3 | IOCON_MODE_INACT)}, // CONNECT2
/* VBUS is not connected on this board, so leave the pin at default setting. */
/*Chip_IOCON_PinMux(LPC_IOCON, 1, 30, IOCON_MODE_INACT, IOCON_FUNC2);*/ /* USB VBUS */
};
// Invoked by startup code
void SystemInit(void)
{
#ifdef __USE_LPCOPEN
extern void (* const g_pfnVectors[])(void);
unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
*pSCB_VTOR = (unsigned int) g_pfnVectors;
#if __FPU_USED == 1
fpuInit();
#endif
#endif // __USE_LPCOPEN
Chip_IOCON_Init(LPC_IOCON);
Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
/* CPU clock source starts with IRC */
/* Enable PBOOST for CPU clock over 100MHz */
Chip_SYSCTL_EnableBoost();
Chip_SetupXtalClocking();
}
void board_init(void)
{
SystemCoreClockUpdate();
#if CFG_TUSB_OS == OPT_OS_NONE
// 1ms tick timer
SysTick_Config(SystemCoreClock / 1000);
#elif CFG_TUSB_OS == OPT_OS_FREERTOS
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
#endif
Chip_GPIO_Init(LPC_GPIO);
// LED
Chip_GPIO_SetPinDIROutput(LPC_GPIO, LED_PORT, LED_PIN);
// Button
Chip_GPIO_SetPinDIRInput(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
// UART
//------------- USB -------------//
Chip_IOCON_SetPinMuxing(LPC_IOCON, pin_usb_mux, sizeof(pin_usb_mux) / sizeof(PINMUX_GRP_T));
// Port1 as Host, Port2: Device
Chip_USB_Init();
enum {
USBCLK_DEVCIE = 0x12, // AHB + Device
USBCLK_HOST = 0x19 , // AHB + OTG + Host
USBCLK_ALL = 0x1B // Host + Device + OTG + AHB
};
LPC_USB->OTGClkCtrl = USBCLK_ALL;
while ( (LPC_USB->OTGClkSt & USBCLK_ALL) != USBCLK_ALL ) {}
// set portfunc: USB1 = host, USB2 = device
LPC_USB->StCtrl = 0x3;
}
//--------------------------------------------------------------------+
// Board porting API
//--------------------------------------------------------------------+
void board_led_write(bool state)
{
Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state);
}
uint32_t board_button_read(void)
{
// active low
return BUTTON_ACTIV_STATE == Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
}
int board_uart_read(uint8_t* buf, int len)
{
//return UART_ReceiveByte(BOARD_UART_PORT);
(void) buf; (void) len;
return 0;
}
int board_uart_write(void const * buf, int len)
{
//UART_Send(BOARD_UART_PORT, &c, 1, BLOCKING);
(void) buf; (void) len;
return 0;
}
#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
void SysTick_Handler (void)
{
system_ticks++;
}
uint32_t board_millis(void)
{
return system_ticks;
}
#endif

99
hw/bsp/lpc40/family.cmake Normal file
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include_guard()
set(SDK_DIR ${TOP}/hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx)
# include board specific
include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
# toolchain set up
set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS LPC18XX CACHE INTERNAL "")
#------------------------------------
# BOARD_TARGET
#------------------------------------
# only need to be built ONCE for all examples
function(add_board_target BOARD_TARGET)
if (TARGET ${BOARD_TARGET})
return()
endif ()
add_library(${BOARD_TARGET} STATIC
${SDK_DIR}/../gcc/cr_startup_lpc40xx.c
${SDK_DIR}/src/chip_17xx_40xx.c
${SDK_DIR}/src/clock_17xx_40xx.c
${SDK_DIR}/src/fpu_init.c
${SDK_DIR}/src/gpio_17xx_40xx.c
${SDK_DIR}/src/iocon_17xx_40xx.c
${SDK_DIR}/src/sysctl_17xx_40xx.c
${SDK_DIR}/src/sysinit_17xx_40xx.c
${SDK_DIR}/src/uart_17xx_40xx.c
)
target_compile_options(${BOARD_TARGET} PUBLIC
-nostdlib
)
target_compile_definitions(${BOARD_TARGET} PUBLIC
__USE_LPCOPEN
CORE_M4
)
target_include_directories(${BOARD_TARGET} PUBLIC
${SDK_DIR}/inc
)
update_board(${BOARD_TARGET})
if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
target_link_options(${BOARD_TARGET} PUBLIC
"LINKER:--script=${LD_FILE_GNU}"
# nanolib
--specs=nosys.specs
--specs=nano.specs
)
elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
target_link_options(${BOARD_TARGET} PUBLIC
"LINKER:--config=${LD_FILE_IAR}"
)
endif ()
endfunction()
#------------------------------------
# Functions
#------------------------------------
function(family_configure_example TARGET RTOS)
family_configure_common(${TARGET} ${RTOS})
# Board target
add_board_target(board_${BOARD})
#---------- Port Specific ----------
# These files are built for each example since it depends on example's tusb_config.h
target_sources(${TARGET} PUBLIC
# BSP
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
)
target_include_directories(${TARGET} PUBLIC
# family, hw, board
${CMAKE_CURRENT_FUNCTION_LIST_DIR}
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
)
# Add TinyUSB target and port source
family_add_tinyusb(${TARGET} OPT_MCU_LPC40XX ${RTOS})
target_sources(${TARGET}-tinyusb PUBLIC
${TOP}/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
)
target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
# Link dependencies
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
# Flashing
family_flash_jlink(${TARGET})
#family_flash_nxplink(${TARGET})
endfunction()

37
hw/bsp/lpc40/family.mk Normal file
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DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
MCU_DIR = hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m4
CFLAGS += \
-flto \
-nostdlib \
-DCORE_M4 \
-D__USE_LPCOPEN \
-DCFG_TUD_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
-DCFG_TUH_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
-DCFG_TUSB_MCU=OPT_MCU_LPC40XX
# mcu driver cause following warnings
CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=cast-qual
# All source paths should be relative to the top level.
SRC_C += \
src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
$(MCU_DIR)/../gcc/cr_startup_lpc40xx.c \
$(MCU_DIR)/src/chip_17xx_40xx.c \
$(MCU_DIR)/src/clock_17xx_40xx.c \
$(MCU_DIR)/src/fpu_init.c \
$(MCU_DIR)/src/gpio_17xx_40xx.c \
$(MCU_DIR)/src/iocon_17xx_40xx.c \
$(MCU_DIR)/src/sysctl_17xx_40xx.c \
$(MCU_DIR)/src/sysinit_17xx_40xx.c \
$(MCU_DIR)/src/uart_17xx_40xx.c \
INC += \
$(TOP)/$(MCU_DIR)/inc \
$(TOP)/$(BOARD_PATH)
# For freeRTOS port source
FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F