rename osal_critcal to osal_spinlock
add spinlock implementation for most rtos
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@@ -57,7 +57,7 @@ typedef struct {
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static xfer_ctl_t xfer_status[DWC2_EP_MAX][2];
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#define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir])
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static OSAL_CRITIAL_DEF(_dcd_critical, usbd_int_set);
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static OSAL_SPINLOCK_DEF(_dcd_spinlock, usbd_int_set);
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typedef struct {
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// EP0 transfers are limited to 1 packet - larger sizes has to be split
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@@ -394,7 +394,7 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
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dwc2_regs_t* dwc2 = DWC2_REG(rhport);
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tu_memclr(&_dcd_data, sizeof(_dcd_data));
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osal_critical_init(&_dcd_critical);
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osal_spin_init(&_dcd_spinlock);
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// Core Initialization
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const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_DEVICE);
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@@ -539,7 +539,7 @@ void dcd_edpt_close_all(uint8_t rhport) {
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dwc2_regs_t* dwc2 = DWC2_REG(rhport);
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uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
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osal_critical_enter(&_dcd_critical, false);
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osal_spin_lock(&_dcd_spinlock, false);
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_dcd_data.allocated_epin_count = 0;
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@@ -560,7 +560,7 @@ void dcd_edpt_close_all(uint8_t rhport) {
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dfifo_flush_rx(dwc2);
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dfifo_device_init(rhport); // re-init dfifo
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osal_critical_exit(&_dcd_critical, false);
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osal_spin_unlock(&_dcd_spinlock, false);
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}
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bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
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@@ -581,7 +581,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
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xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
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bool ret;
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osal_critical_enter(&_dcd_critical, false);
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osal_spin_lock(&_dcd_spinlock, false);
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if (xfer->max_size == 0) {
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ret = false; // Endpoint is closed
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@@ -600,7 +600,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
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ret = true;
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}
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osal_critical_exit(&_dcd_critical, false);
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osal_spin_unlock(&_dcd_spinlock, false);
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return ret;
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}
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@@ -618,7 +618,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t
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xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
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bool ret;
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osal_critical_enter(&_dcd_critical, false);
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osal_spin_lock(&_dcd_spinlock, false);
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if (xfer->max_size == 0) {
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ret = false; // Endpoint is closed
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@@ -633,7 +633,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t
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ret = true;
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}
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osal_critical_exit(&_dcd_critical, false);
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osal_spin_unlock(&_dcd_spinlock, false);
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return ret;
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}
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@@ -1021,14 +1021,14 @@ void dcd_int_handler(uint8_t rhport) {
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if (gintsts & GINTSTS_USBRST) {
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// USBRST is start of reset.
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#if TUP_MCU_MULTIPLE_CORE
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osal_critical_enter(&_dcd_critical, true);
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osal_spin_lock(&_dcd_spinlock, true);
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#endif
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dwc2->gintsts = GINTSTS_USBRST;
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handle_bus_reset(rhport);
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#if TUP_MCU_MULTIPLE_CORE
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osal_critical_exit(&_dcd_critical, true);
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osal_spin_unlock(&_dcd_spinlock, true);
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#endif
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}
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