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addd dwc2_info.py/md update stm32u5a5 board clock & power configure, able to get passed otg clock reset

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hathach
2023-10-30 22:21:58 +07:00
parent 27a2c8cba4
commit a4c542a7b4
6 changed files with 277 additions and 52 deletions
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12
hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h
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@@ -99,6 +99,18 @@ static void SystemClock_Config(void) {
RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
// USB Clock
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USBPHY;
PeriphClkInit.UsbPhyClockSelection = RCC_USBPHYCLKSOURCE_HSE;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
Error_Handler();
}
/** Set the OTG PHY reference clock selection
*/
HAL_SYSCFG_SetOTGPHYReferenceClockSelection(SYSCFG_OTG_HS_PHY_CLK_SELECT_1);
}
static void SystemPower_Config(void) {

11
hw/bsp/stm32u5/family.c
View File

@@ -177,7 +177,6 @@ void board_init(void) {
NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
#endif
// Disable VBUS sense (B device)
USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
@@ -185,11 +184,17 @@ void board_init(void) {
USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
/* USB clock enable */
__HAL_RCC_SYSCFG_CLK_ENABLE();
__HAL_RCC_USB_OTG_HS_CLK_ENABLE();
__HAL_RCC_USBPHYC_CLK_ENABLE();
/* Enable USB power on Pwrctrl CR2 register */
HAL_PWREx_EnableVddUSB();
HAL_PWREx_EnableUSBHSTranceiverSupply();
/* USB clock enable */
__HAL_RCC_USB_OTG_HS_CLK_ENABLE();
/*Configuring the SYSCFG registers OTG_HS PHY*/
HAL_SYSCFG_EnableOTGPHY(SYSCFG_OTG_HS_PHY_ENABLE);
#endif // USB_OTG_FS