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addd dwc2_info.py/md update stm32u5a5 board clock & power configure, able to get passed otg clock reset

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This commit is contained in:
hathach
2023-10-30 22:21:58 +07:00
parent 27a2c8cba4
commit a4c542a7b4
6 changed files with 277 additions and 52 deletions
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93
src/portable/synopsys/dwc2/dwc2_stm32.h
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@@ -28,7 +28,7 @@
#define _DWC2_STM32_H_
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
// EP_MAX : Max number of bi-directional endpoints including EP0
@@ -84,17 +84,15 @@
#elif CFG_TUSB_MCU == OPT_MCU_STM32U5
#include "stm32u5xx.h"
// NOTE: STM595/5A5/599/5A9 only have 1 USB port (with integrated HS PHY)
// USB_OTG_FS_BASE and OTG_FS_IRQn not defined
#if !defined(USB_OTG_FS)
// U59x/5Ax/5Fx/5Gx are highspeed with built-in HS PHY
#ifdef USB_OTG_FS
#define USB_OTG_FS_PERIPH_BASE USB_OTG_FS_BASE
#define EP_MAX_FS 6
#define EP_FIFO_SIZE_FS 1280
#else
#define USB_OTG_HS_PERIPH_BASE USB_OTG_HS_BASE
#define EP_MAX_HS 9
#define EP_FIFO_SIZE_HS 4096
//#define OTG_FS_IRQn OTG_HS_IRQn
#else
#define USB_OTG_FS_PERIPH_BASE USB_OTG_FS_BASE
#define EP_MAX_FS 6
#define EP_FIFO_SIZE_FS 1280
#endif
#else
#error "Unsupported MCUs"
@@ -109,15 +107,14 @@
// On STM32 for consistency we associate
// - Port0 to OTG_FS, and Port1 to OTG_HS
static const dwc2_controller_t _dwc2_controller[] =
{
#ifdef USB_OTG_FS_PERIPH_BASE
{ .reg_base = USB_OTG_FS_PERIPH_BASE, .irqnum = OTG_FS_IRQn, .ep_count = EP_MAX_FS, .ep_fifo_size = EP_FIFO_SIZE_FS },
#endif
static const dwc2_controller_t _dwc2_controller[] = {
#ifdef USB_OTG_FS_PERIPH_BASE
{ .reg_base = USB_OTG_FS_PERIPH_BASE, .irqnum = OTG_FS_IRQn, .ep_count = EP_MAX_FS, .ep_fifo_size = EP_FIFO_SIZE_FS },
#endif
#ifdef USB_OTG_HS_PERIPH_BASE
{ .reg_base = USB_OTG_HS_PERIPH_BASE, .irqnum = OTG_HS_IRQn, .ep_count = EP_MAX_HS, .ep_fifo_size = EP_FIFO_SIZE_HS },
#endif
#ifdef USB_OTG_HS_PERIPH_BASE
{ .reg_base = USB_OTG_HS_PERIPH_BASE, .irqnum = OTG_HS_IRQn, .ep_count = EP_MAX_HS, .ep_fifo_size = EP_FIFO_SIZE_HS },
#endif
};
//--------------------------------------------------------------------+
@@ -128,40 +125,33 @@ static const dwc2_controller_t _dwc2_controller[] =
// extern uint32_t SystemCoreClock;
TU_ATTR_ALWAYS_INLINE
static inline void dwc2_dcd_int_enable(uint8_t rhport)
{
NVIC_EnableIRQ((IRQn_Type)_dwc2_controller[rhport].irqnum);
static inline void dwc2_dcd_int_enable(uint8_t rhport) {
NVIC_EnableIRQ((IRQn_Type) _dwc2_controller[rhport].irqnum);
}
TU_ATTR_ALWAYS_INLINE
static inline void dwc2_dcd_int_disable (uint8_t rhport)
{
NVIC_DisableIRQ((IRQn_Type)_dwc2_controller[rhport].irqnum);
static inline void dwc2_dcd_int_disable(uint8_t rhport) {
NVIC_DisableIRQ((IRQn_Type) _dwc2_controller[rhport].irqnum);
}
TU_ATTR_ALWAYS_INLINE
static inline void dwc2_remote_wakeup_delay(void)
{
static inline void dwc2_remote_wakeup_delay(void) {
// try to delay for 1 ms
uint32_t count = SystemCoreClock / 1000;
while ( count-- ) __NOP();
while (count--) __NOP();
}
// MCU specific PHY init, called BEFORE core reset
static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
{
if ( hs_phy_type == HS_PHY_TYPE_NONE )
{
static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
if (hs_phy_type == HS_PHY_TYPE_NONE) {
// Enable on-chip FS PHY
dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
}else
{
// Disable FS PHY
} else {
// Disable FS PHY, TODO on U5A5 (dwc2 4.11a) 16th bit is 'Host CDP behavior enable'
dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN;
// Enable on-chip HS PHY
if (hs_phy_type == HS_PHY_TYPE_UTMI || hs_phy_type == HS_PHY_TYPE_UTMI_ULPI)
{
if (hs_phy_type == HS_PHY_TYPE_UTMI || hs_phy_type == HS_PHY_TYPE_UTMI_ULPI) {
#ifdef USB_HS_PHYC
// Enable UTMI HS PHY
dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN;
@@ -200,34 +190,39 @@ static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
}
// MCU specific PHY update, it is called AFTER init() and core reset
static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
{
static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
// used to set turnaround time for fullspeed, nothing to do in highspeed mode
if ( hs_phy_type == HS_PHY_TYPE_NONE )
{
if (hs_phy_type == HS_PHY_TYPE_NONE) {
// Turnaround timeout depends on the AHB clock dictated by STM32 Reference Manual
uint32_t turnaround;
if ( SystemCoreClock >= 32000000u )
if (SystemCoreClock >= 32000000u) {
turnaround = 0x6u;
else if ( SystemCoreClock >= 27500000u )
} else if (SystemCoreClock >= 27500000u) {
turnaround = 0x7u;
else if ( SystemCoreClock >= 24000000u )
} else if (SystemCoreClock >= 24000000u) {
turnaround = 0x8u;
else if ( SystemCoreClock >= 21800000u )
} else if (SystemCoreClock >= 21800000u) {
turnaround = 0x9u;
else if ( SystemCoreClock >= 20000000u )
}
else if (SystemCoreClock >= 20000000u) {
turnaround = 0xAu;
else if ( SystemCoreClock >= 18500000u )
}
else if (SystemCoreClock >= 18500000u) {
turnaround = 0xBu;
else if ( SystemCoreClock >= 17200000u )
}
else if (SystemCoreClock >= 17200000u) {
turnaround = 0xCu;
else if ( SystemCoreClock >= 16000000u )
}
else if (SystemCoreClock >= 16000000u) {
turnaround = 0xDu;
else if ( SystemCoreClock >= 15000000u )
}
else if (SystemCoreClock >= 15000000u) {
turnaround = 0xEu;
else
}
else {
turnaround = 0xFu;
}
dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (turnaround << GUSBCFG_TRDT_Pos);
}