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Merge remote-tracking branch 'origin/master' into xfer_isr

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# Conflicts:
#	examples/device/audio_4_channel_mic_freertos/src/main.c
#	examples/device/audio_test_freertos/src/main.c
#	src/class/audio/audio_device.c
This commit is contained in:
hathach
2025-07-08 10:09:24 +07:00
parent 545690c834 ea64300a9a
commit a56f55c10b
133 changed files with 4256 additions and 2053 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
hw/bsp/board.c
View File

@@ -60,13 +60,11 @@ int sys_read(int fhdl, char *buf, size_t count) {
int rd = (int) SEGGER_RTT_Read(0, buf, count);
return (rd > 0) ? rd : -1;
}
#endif
#elif defined(LOGGER_SWO)
#define ITM_BASE 0xE0000000
#define ITM_STIM0 (*((volatile uint8_t*)(ITM_BASE + 0)))
#define ITM_TER *((volatile uint32_t*)(ITM_BASE + 0xE00))
#define ITM_TCR *((volatile uint32_t*)(ITM_BASE + 0xE80))
@@ -150,6 +148,9 @@ int board_getchar(void) {
return (sys_read(0, &c, 1) > 0) ? (int) c : (-1);
}
void board_putchar(int c) {
sys_write(0, (const char*)&c, 1);
}
uint32_t tusb_time_millis_api(void) {
return board_millis();
@@ -158,7 +159,7 @@ uint32_t tusb_time_millis_api(void) {
//--------------------------------------------------------------------
// FreeRTOS hooks
//--------------------------------------------------------------------
#if CFG_TUSB_OS == OPT_OS_FREERTOS && !TUSB_MCU_VENDOR_ESPRESSIF
#if CFG_TUSB_OS == OPT_OS_FREERTOS && !defined(ESP_PLATFORM)
#include "FreeRTOS.h"
#include "task.h"
@@ -240,5 +241,4 @@ void vApplicationSetupTimerInterrupt(void) {
}
#endif
#endif

3
hw/bsp/board_api.h
View File

@@ -41,7 +41,7 @@ extern "C" {
#if CFG_TUSB_OS == OPT_OS_ZEPHYR
#include <zephyr/kernel.h>
#elif CFG_TUSB_OS == OPT_OS_FREERTOS
#if TUSB_MCU_VENDOR_ESPRESSIF
#ifdef ESP_PLATFORM
// ESP-IDF need "freertos/" prefix in include path.
// CFG_TUSB_OS_INC_PATH should be defined accordingly.
#include "freertos/FreeRTOS.h"
@@ -195,6 +195,7 @@ static inline void board_delay(uint32_t ms) {
// stdio getchar() is blocking, this is non-blocking version
int board_getchar(void);
void board_putchar(int c);
#ifdef __cplusplus
}

1
hw/bsp/brtmm90x/family.mk
View File

@@ -13,7 +13,6 @@ else
# The submodule BRTSG-FOSS/ft90x-sdk contains header files and source
# code for the Bridgetek SDK. This can be used instead of the prebuilt
# library.
DEPS_SUBMODULES += hw/mcu/bridgetek/ft9xx/ft90x-sdk
# The SDK can be used to load specific files from the Bridgetek SDK.
FT9XX_SDK = hw/mcu/bridgetek/ft9xx/ft90x-sdk/Source
INC += "$(TOP)/$(FT9XX_SDK)/include"

1
hw/bsp/ch32f20x/family.mk
View File

@@ -1,6 +1,5 @@
# Submodules
CH32F20X_SDK = hw/mcu/wch/ch32f20x
DEPS_SUBMODULES += $(CH32F20X_SDK)
# WCH-SDK paths
CH32F20X_SDK_SRC = $(CH32F20X_SDK)/EVT/EXAM/SRC

96
hw/bsp/ch32v20x/family.c
View File

@@ -20,56 +20,56 @@ manufacturer: WCH
#include "bsp/board_api.h"
#include "board.h"
/* CH32v203 depending on variants can support 2 USB IPs: FSDEV and USBFS.
/* CH32v203 depending on variants can support 2 USB IPs: FSDEV (port0) and USBFS (port1).
* By default, we use FSDEV, but you can explicitly select by define:
* - CFG_TUD_WCH_USBIP_FSDEV
* - CFG_TUD_WCH_USBIP_USBFS
*/
// USBFS
__attribute__((interrupt)) __attribute__((used))
void USBHD_IRQHandler(void) {
// Port0: USBD (fsdev)
__attribute__((interrupt)) __attribute__((used)) void USB_LP_CAN1_RX0_IRQHandler(void) {
#if CFG_TUD_WCH_USBIP_FSDEV
tud_int_handler(0);
#endif
}
__attribute__((interrupt)) __attribute__((used)) void USB_HP_CAN1_TX_IRQHandler(void) {
#if CFG_TUD_WCH_USBIP_FSDEV
tud_int_handler(0);
#endif
}
__attribute__((interrupt)) __attribute__((used)) void USBWakeUp_IRQHandler(void) {
#if CFG_TUD_WCH_USBIP_FSDEV
tud_int_handler(0);
#endif
}
// Port1: USBFS
__attribute__((interrupt)) __attribute__((used)) void USBHD_IRQHandler(void) {
#if CFG_TUD_ENABLED && CFG_TUD_WCH_USBIP_USBFS
tud_int_handler(1);
#endif
#if CFG_TUH_ENABLED
tuh_int_handler(1);
#endif
}
__attribute__((interrupt)) __attribute__((used)) void USBHDWakeUp_IRQHandler(void) {
#if CFG_TUD_WCH_USBIP_USBFS
tud_int_handler(0);
#endif
}
__attribute__((interrupt)) __attribute__((used))
void USBHDWakeUp_IRQHandler(void) {
#if CFG_TUD_WCH_USBIP_USBFS
tud_int_handler(0);
#endif
}
// USBD (fsdev)
__attribute__((interrupt)) __attribute__((used))
void USB_LP_CAN1_RX0_IRQHandler(void) {
#if CFG_TUD_WCH_USBIP_FSDEV
tud_int_handler(0);
#endif
}
__attribute__((interrupt)) __attribute__((used))
void USB_HP_CAN1_TX_IRQHandler(void) {
#if CFG_TUD_WCH_USBIP_FSDEV
tud_int_handler(0);
#endif
}
__attribute__((interrupt)) __attribute__((used))
void USBWakeUp_IRQHandler(void) {
#if CFG_TUD_WCH_USBIP_FSDEV
tud_int_handler(0);
#endif
}
//--------------------------------------------------------------------+
// Board API
//--------------------------------------------------------------------+
#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
__attribute__((interrupt))
void SysTick_Handler(void) {
__attribute__((interrupt)) void SysTick_Handler(void) {
SysTick->SR = 0;
system_ticks++;
}
@@ -108,7 +108,7 @@ void board_init(void) {
#ifdef UART_DEV
UART_CLOCK_EN();
GPIO_InitTypeDef usart_init = {
.GPIO_Pin = UART_TX_PIN,
.GPIO_Pin = UART_TX_PIN | UART_RX_PIN,
.GPIO_Speed = GPIO_Speed_50MHz,
.GPIO_Mode = GPIO_Mode_AF_PP,
};
@@ -119,7 +119,7 @@ void board_init(void) {
.USART_WordLength = USART_WordLength_8b,
.USART_StopBits = USART_StopBits_1,
.USART_Parity = USART_Parity_No,
.USART_Mode = USART_Mode_Tx,
.USART_Mode = USART_Mode_Tx | USART_Mode_Rx,
.USART_HardwareFlowControl = USART_HardwareFlowControl_None,
};
USART_Init(UART_DEV, &usart);
@@ -189,9 +189,19 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) {
}
int board_uart_read(uint8_t *buf, int len) {
(void) buf;
(void) len;
#ifdef UART_DEV
int count;
for (count = 0; count < len; count++) {
if (USART_GetFlagStatus(UART_DEV, USART_FLAG_RXNE) == RESET) {
break;
}
buf[count] = USART_ReceiveData(UART_DEV);
}
return count;
#else
(void) buf; (void) len;
return 0;
#endif
}
int board_uart_write(void const *buf, int len) {
@@ -207,7 +217,3 @@ int board_uart_write(void const *buf, int len) {
return len;
}
//--------------------------------------------------------------------
// Neopixel
//--------------------------------------------------------------------

28
hw/bsp/ch32v20x/family.cmake
View File

@@ -16,9 +16,12 @@ set(FAMILY_MCUS CH32V20X CACHE INTERNAL "")
set(OPENOCD_OPTION "-f ${CMAKE_CURRENT_LIST_DIR}/wch-riscv.cfg")
# Port0 use FSDev, Port1 use USBFS
if (NOT DEFINED PORT)
set(PORT 0)
endif()
if (NOT DEFINED RHPORT_DEVICE)
set(RHPORT_DEVICE 0)
endif ()
# only port1 support host mode
set(RHPORT_HOST 1)
#------------------------------------
# BOARD_TARGET
@@ -56,18 +59,16 @@ function(add_board_target BOARD_TARGET)
)
target_compile_definitions(${BOARD_TARGET} PUBLIC
CH32V20x_${MCU_VARIANT}
BOARD_TUD_RHPORT=${RHPORT_DEVICE}
BOARD_TUH_RHPORT=${RHPORT_HOST}
)
if (PORT EQUAL 0)
target_compile_definitions(${BOARD_TARGET} PUBLIC
CFG_TUD_WCH_USBIP_FSDEV=1
)
elseif (PORT EQUAL 1)
target_compile_definitions(${BOARD_TARGET} PUBLIC
CFG_TUD_WCH_USBIP_USBFS=1
)
if (RHPORT_DEVICE EQUAL 0)
target_compile_definitions(${BOARD_TARGET} PUBLIC CFG_TUD_WCH_USBIP_FSDEV=1)
elseif (RHPORT_DEVICE EQUAL 1)
target_compile_definitions(${BOARD_TARGET} PUBLIC CFG_TUH_WCH_USBIP_USBFS=1)
else()
message(FATAL_ERROR "Invalid PORT ${PORT}")
message(FATAL_ERROR "Invalid RHPORT_DEVICE ${RHPORT_DEVICE}")
endif()
update_board(${BOARD_TARGET})
@@ -127,12 +128,11 @@ function(family_configure_example TARGET RTOS)
target_sources(${TARGET} PUBLIC
${TOP}/src/portable/wch/dcd_ch32_usbfs.c
${TOP}/src/portable/wch/hcd_ch32_usbfs.c
${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
)
target_link_libraries(${TARGET} PUBLIC board_${BOARD})
# Flashing
family_add_bin_hex(${TARGET})
family_flash_openocd_wch(${TARGET})

3
hw/bsp/ch32v20x/family.mk
View File

@@ -30,6 +30,8 @@ CFLAGS += -Wno-error=strict-prototypes
ifeq ($(PORT),0)
$(info "Using FSDEV driver")
CFLAGS += -DCFG_TUD_WCH_USBIP_FSDEV=1
$(info "Using USBFS Host driver")
CFLAGS += -DCFG_TUH_WCH_USBIP_USBFS=1
else
$(info "Using USBFS driver")
CFLAGS += -DCFG_TUD_WCH_USBIP_USBFS=1
@@ -43,6 +45,7 @@ LD_FILE = $(FAMILY_PATH)/linker/${CH32_FAMILY}.ld
SRC_C += \
src/portable/wch/dcd_ch32_usbfs.c \
src/portable/wch/hcd_ch32_usbfs.c \
src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
$(SDK_SRC_DIR)/Core/core_riscv.c \
$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_gpio.c \

4
hw/bsp/espressif/boards/family.c
View File

@@ -156,6 +156,10 @@ int board_getchar(void) {
return getchar();
}
void board_putchar(int c) {
putchar(c);
}
//--------------------------------------------------------------------
// PHY Init
//--------------------------------------------------------------------

2
hw/bsp/espressif/family.cmake
View File

@@ -1,5 +1,3 @@
cmake_minimum_required(VERSION 3.5)
# Apply board specific content i.e IDF_TARGET must be set before project.cmake is included
include("${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake")
string(TOUPPER ${IDF_TARGET} FAMILY_MCUS)

34
hw/bsp/espressif/family.mk
View File

@@ -1,34 +0,0 @@
#DEPS_SUBMODULES +=
UF2_FAMILY_ID_esp32s2 = 0xbfdd4eee
UF2_FAMILY_ID_esp32s3 = 0xc47e5767
BOARD_CMAKE := $(file < $(TOP)/$(BOARD_PATH)/board.cmake)
ifneq ($(findstring esp32s2,$(BOARD_CMAKE)),)
IDF_TARGET = esp32s2
else
ifneq ($(findstring esp32s3,$(BOARD_CMAKE)),)
IDF_TARGET = esp32s3
endif
endif
.PHONY: all clean flash bootloader-flash app-flash erase monitor dfu-flash dfu
all:
idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) build
build: all
fullclean:
if test -f sdkconfig; then $(RM) -f sdkconfig ; fi
if test -d $(BUILD); then $(RM) -rf $(BUILD) ; fi
idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) $@
clean flash bootloader-flash app-flash erase monitor dfu-flash dfu size size-components size-files:
idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) $@
uf2: $(BUILD)/$(PROJECT).uf2
$(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).bin
@echo CREATE $@
$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID_$(IDF_TARGET)) -b 0x0 -c -o $@ $^

2
hw/bsp/family_support.cmake
View File

@@ -221,6 +221,8 @@ function(family_configure_common TARGET RTOS)
target_include_directories(${TARGET} PUBLIC ${TOP}/lib/SEGGER_RTT/RTT)
# target_compile_definitions(${TARGET} PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL)
endif ()
else ()
target_compile_definitions(${TARGET} PUBLIC LOGGER_UART)
endif ()
if (CMAKE_C_COMPILER_ID STREQUAL "GNU" OR CMAKE_C_COMPILER_ID STREQUAL "Clang")

1
hw/bsp/imxrt/family.mk
View File

@@ -1,6 +1,5 @@
UF2_FAMILY_ID = 0x4fb2d5bd
SDK_DIR = hw/mcu/nxp/mcux-sdk
DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
include $(TOP)/$(BOARD_PATH)/board.mk

1
hw/bsp/kinetis_k/family.mk
View File

@@ -1,5 +1,4 @@
SDK_DIR = hw/mcu/nxp/mcux-sdk
DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
MCU_DIR = $(SDK_DIR)/devices/${MCU_VARIANT}
include $(TOP)/$(BOARD_PATH)/board.mk

1
hw/bsp/kinetis_kl/family.mk
View File

@@ -1,5 +1,4 @@
SDK_DIR = hw/mcu/nxp/mcux-sdk
DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
MCU_DIR = $(SDK_DIR)/devices/$(MCU)
include $(TOP)/$(BOARD_PATH)/board.mk

2
hw/bsp/lpc13/boards/lpcxpresso1347/board.mk
View File

@@ -1,5 +1,3 @@
DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
CFLAGS += \
-DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))'

2
hw/bsp/lpc13/family.mk
View File

@@ -1,5 +1,3 @@
DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
MCU_DIR = hw/mcu/nxp/lpcopen/lpc13xx/lpc_chip_13xx
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m3

2
hw/bsp/lpc15/family.mk
View File

@@ -1,5 +1,3 @@
DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m3

2
hw/bsp/lpc17/family.mk
View File

@@ -1,5 +1,3 @@
DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m3

1
hw/bsp/lpc18/family.mk
View File

@@ -1,4 +1,3 @@
DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
MCU_DIR = hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx
include $(TOP)/$(BOARD_PATH)/board.mk

2
hw/bsp/lpc40/family.mk
View File

@@ -1,5 +1,3 @@
DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
MCU_DIR = hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m4

1
hw/bsp/lpc43/family.mk
View File

@@ -1,4 +1,3 @@
DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
SDK_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
include ${TOP}/${BOARD_PATH}/board.mk

1
hw/bsp/lpc54/family.mk
View File

@@ -1,5 +1,4 @@
SDK_DIR = hw/mcu/nxp/mcux-sdk
DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m4

1
hw/bsp/lpc55/family.mk
View File

@@ -1,6 +1,5 @@
UF2_FAMILY_ID = 0x2abc77ec
SDK_DIR = hw/mcu/nxp/mcux-sdk
DEPS_SUBMODULES += lib/CMSIS_5 lib/sct_neopixel $(SDK_DIR)
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m33

2
hw/bsp/mcx/family.mk
View File

@@ -1,8 +1,6 @@
UF2_FAMILY_ID = 0x2abc77ec
SDK_DIR = hw/mcu/nxp/mcux-sdk
DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
include $(TOP)/$(BOARD_PATH)/board.mk
# Default to Highspeed PORT1

48
hw/bsp/msp430/family.cmake
View File

@@ -11,36 +11,37 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/msp430_${T
set(FAMILY_MCUS MSP430x5xx CACHE INTERNAL "")
#------------------------------------
# BOARD_TARGET
#------------------------------------
# only need to be built ONCE for all examples
function(add_board_target BOARD_TARGET)
if (NOT TARGET ${BOARD_TARGET})
add_library(${BOARD_TARGET} INTERFACE)
target_compile_definitions(${BOARD_TARGET} INTERFACE
CFG_TUD_ENDPOINT0_SIZE=8
CFG_EXAMPLE_VIDEO_READONLY
CFG_EXAMPLE_MSC_READONLY
)
target_include_directories(${BOARD_TARGET} INTERFACE
${CMAKE_CURRENT_FUNCTION_LIST_DIR}
${SDK_DIR}
)
if (TARGET ${BOARD_TARGET})
return()
endif ()
update_board(${BOARD_TARGET})
add_library(${BOARD_TARGET} INTERFACE)
target_compile_definitions(${BOARD_TARGET} INTERFACE
CFG_TUD_ENDPOINT0_SIZE=8
CFG_EXAMPLE_VIDEO_READONLY
CFG_EXAMPLE_MSC_READONLY
)
target_include_directories(${BOARD_TARGET} INTERFACE
${CMAKE_CURRENT_FUNCTION_LIST_DIR}
${SDK_DIR}
)
if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
target_link_options(${BOARD_TARGET} INTERFACE
"LINKER:--script=${LD_FILE_GNU}"
-L${SDK_DIR}
)
elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
target_link_options(${BOARD_TARGET} INTERFACE
"LINKER:--config=${LD_FILE_IAR}"
)
endif ()
update_board(${BOARD_TARGET})
if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
target_link_options(${BOARD_TARGET} INTERFACE
"LINKER:--script=${LD_FILE_GNU}"
-L${SDK_DIR}
)
elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
target_link_options(${BOARD_TARGET} INTERFACE
"LINKER:--config=${LD_FILE_IAR}"
)
endif ()
endfunction()
@@ -75,7 +76,6 @@ function(family_configure_example TARGET RTOS)
)
target_link_libraries(${TARGET} PUBLIC board_${BOARD})
# Flashing
family_add_bin_hex(${TARGET})
family_flash_msp430flasher(${TARGET})

1
hw/bsp/msp430/family.mk
View File

@@ -1,5 +1,4 @@
CROSS_COMPILE = msp430-elf-
DEPS_SUBMODULES += hw/mcu/ti
SKIP_NANOLIB = 1
SDK_DIR = hw/mcu/ti/msp430/msp430-gcc-support-files/include

2
hw/bsp/nutiny_nuc121s/board.mk
View File

@@ -1,5 +1,3 @@
DEPS_SUBMODULES += hw/mcu/nuvoton
CFLAGS += \
-flto \
-mthumb \

2
hw/bsp/nutiny_nuc125s/board.mk
View File

@@ -1,5 +1,3 @@
DEPS_SUBMODULES += hw/mcu/nuvoton
CFLAGS += \
-flto \
-mthumb \

2
hw/bsp/nutiny_nuc126v/board.mk
View File

@@ -1,5 +1,3 @@
DEPS_SUBMODULES += hw/mcu/nuvoton
CFLAGS += \
-flto \
-mthumb \

2
hw/bsp/nutiny_sdk_nuc120/board.mk
View File

@@ -1,5 +1,3 @@
DEPS_SUBMODULES += hw/mcu/nuvoton
CFLAGS += \
-flto \
-mthumb \

2
hw/bsp/nutiny_sdk_nuc505/board.mk
View File

@@ -1,5 +1,3 @@
DEPS_SUBMODULES += hw/mcu/nuvoton
CFLAGS += \
-flto \
-mthumb \

6
hw/bsp/rp2040/family.c
View File

@@ -254,7 +254,7 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) {
int board_uart_read(uint8_t *buf, int len) {
#ifdef UART_DEV
int count = 0;
while ( (count < len) && uart_is_readable(uart_inst) ) {
while ((count < len) && uart_is_readable(uart_inst)) {
buf[count] = uart_getc(uart_inst);
count++;
}
@@ -282,6 +282,10 @@ int board_getchar(void) {
return getchar_timeout_us(0);
}
void board_putchar(int c) {
stdio_putchar(c);
}
//--------------------------------------------------------------------+
// USB Interrupt Handler
// rp2040 implementation will install appropriate handler when initializing

18
hw/bsp/rp2040/family.mk
View File

@@ -1,18 +0,0 @@
JLINK_DEVICE = rp2040_m0_0
PYOCD_TARGET = rp2040
DEPS_SUBMODULES += hw/mcu/raspberry_pi/Pico-PIO-USB
ifeq ($(DEBUG), 1)
CMAKE_DEFSYM += -DCMAKE_BUILD_TYPE=Debug
endif
$(BUILD):
cmake -S . -B $(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) -DPICO_BUILD_DOCS=0 $(CMAKE_DEFSYM)
all: $(BUILD)
$(MAKE) -C $(BUILD)
flash: flash-pyocd
flash-uf2:
@$(CP) $(BUILD)/$(PROJECT).uf2 /media/$(USER)/RPI-RP2

2
hw/bsp/rx/family.mk
View File

@@ -1,5 +1,3 @@
DEPS_SUBMODULES += hw/mcu/renesas/rx
# Cross Compiler for RX
CROSS_COMPILE = rx-elf-

1
hw/bsp/same70_qmtech/board.mk
View File

@@ -1,4 +1,3 @@
DEPS_SUBMODULES += hw/mcu/microchip
ASF_DIR = hw/mcu/microchip/same70
CFLAGS += \

1
hw/bsp/same70_xplained/board.mk
View File

@@ -1,4 +1,3 @@
DEPS_SUBMODULES += hw/mcu/microchip
ASF_DIR = hw/mcu/microchip/same70
CFLAGS += \

3
hw/bsp/sltb009a/board.mk
View File

@@ -16,9 +16,6 @@ CFLAGS += \
SILABS_FAMILY = efm32gg12b
SILABS_CMSIS = hw/mcu/silabs/cmsis-dfp-$(SILABS_FAMILY)/Device/SiliconLabs/$(shell echo $(SILABS_FAMILY) | tr a-z A-Z)
DEPS_SUBMODULES += hw/mcu/silabs/cmsis-dfp-$(SILABS_FAMILY)
DEPS_SUBMODULES += lib/CMSIS_5
LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
# All source paths should be relative to the top level.

2
hw/bsp/spresense/board.mk
View File

@@ -1,5 +1,3 @@
DEPS_SUBMODULES += hw/mcu/sony/cxd56/spresense-exported-sdk
# Platforms are: Linux, Darwin, MSYS, CYGWIN
PLATFORM := $(firstword $(subst _, ,$(shell uname -s 2>/dev/null)))

2
hw/bsp/stm32c0/family.mk
View File

@@ -1,6 +1,4 @@
ST_FAMILY = c0
DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver

2
hw/bsp/stm32f0/family.mk
View File

@@ -1,7 +1,5 @@
UF2_FAMILY_ID = 0x647824b6
ST_FAMILY = f0
DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver

2
hw/bsp/stm32f1/family.mk
View File

@@ -1,6 +1,4 @@
ST_FAMILY = f1
DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_${ST_FAMILY} hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver
ST_CMSIS = hw/mcu/st/cmsis_device_${ST_FAMILY}
ST_HAL_DRIVER = hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver

5
hw/bsp/stm32f2/family.mk
View File

@@ -2,11 +2,6 @@ ST_FAMILY = f2
ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
DEPS_SUBMODULES += \
lib/CMSIS_5 \
$(ST_CMSIS) \
$(ST_HAL_DRIVER)
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m3

4
hw/bsp/stm32f7/family.c
View File

@@ -78,6 +78,10 @@ void OTG_HS_IRQHandler(void) {
//--------------------------------------------------------------------+
void board_init(void) {
SCB_EnableICache();
HAL_Init();
board_clock_init();
// Enable All GPIOs clocks

1
hw/bsp/stm32f7/family.mk
View File

@@ -1,6 +1,5 @@
UF2_FAMILY_ID = 0x53b80f00
ST_FAMILY = f7
DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver

1
hw/bsp/stm32g0/family.mk
View File

@@ -1,5 +1,4 @@
ST_FAMILY = g0
DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver

4
hw/bsp/stm32h7/family.c
View File

@@ -98,6 +98,10 @@ static void trace_etm_init(void) {
#endif
void board_init(void) {
SCB_EnableICache();
HAL_Init();
// Implemented in board.h
SystemClock_Config();

2
hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake
View File

@@ -1,9 +1,7 @@
set(MCU_VARIANT stm32h7s3xx)
set(JLINK_DEVICE stm32h7s3xx)
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/stm32h7s3xx_flash.ld)
set(LD_FILE_Clang ${LD_FILE_GNU})
set(LD_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/stm32h7s3xx_flash.icf)
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC

4
hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.mk
View File

@@ -7,10 +7,6 @@ JLINK_DEVICE = stm32h7s3xx
# flash target using on-board stlink
flash: flash-stlink
# Linker
LD_FILE_GCC = $(BOARD_PATH)/stm32h7s3xx_flash.ld
LD_FILE_IAR = $(BOARD_PATH)/stm32h7s3xx_flash.icf
SRC_C += \
$(ST_TCPP0203)/tcpp0203.c \
$(ST_TCPP0203)/tcpp0203_reg.c \

55
hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/stm32h7s3xx_flash.icf
View File

@@ -1,55 +0,0 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol NONCACHEABLEBUFFER_size = 0x4000;
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF - NONCACHEABLEBUFFER_size;
define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1;
define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x800;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define symbol __region_ITCM_start__ = 0x00000000;
define symbol __region_ITCM_end__ = 0x0000FFFF;
define symbol __region_DTCM_start__ = 0x20000000;
define symbol __region_DTCM_end__ = 0x2000FFFF;
define symbol __region_SRAMAHB_start__ = 0x30000000;
define symbol __region_SRAMAHB_end__ = 0x30007FFF;
define symbol __region_BKPSRAM_start__ = 0x38800000;
define symbol __region_BKPSRAM_end__ = 0x38800FFF;
export symbol NONCACHEABLEBUFFER_start;
export symbol NONCACHEABLEBUFFER_size;
export symbol __ICFEDIT_region_ROM_start__;
export symbol __ICFEDIT_region_ROM_end__;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite };
place in NONCACHEABLE_region { section noncacheable_buffer };
place in DTCM_region { block CSTACK, block HEAP };

149
hw/bsp/stm32h7rs/family.c
View File

@@ -123,10 +123,159 @@ void log_swo_init(void)
#define log_swo_init()
#endif
static void MPU_AdjustRegionAddressSize(uint32_t Address, uint32_t Size, MPU_Region_InitTypeDef* pInit);
static void MPU_Config(void)
{
MPU_Region_InitTypeDef MPU_InitStruct = {0};
uint32_t index = MPU_REGION_NUMBER0;
uint32_t address;
uint32_t size;
/* Disable the MPU */
HAL_MPU_Disable();
/* Initialize the background region */
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.Number = index;
MPU_InitStruct.BaseAddress = 0x0;
MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
MPU_InitStruct.SubRegionDisable = 0x87;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
index++;
/* Initialize the non cacheable region */
#if defined ( __ICCARM__ )
/* get the region attribute form the icf file */
extern uint32_t NONCACHEABLEBUFFER_start;
extern uint32_t NONCACHEABLEBUFFER_size;
address = (uint32_t)&NONCACHEABLEBUFFER_start;
size = (uint32_t)&NONCACHEABLEBUFFER_size;
#elif defined (__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$RW_NONCACHEABLEBUFFER$$Base;
extern uint32_t Image$$RW_NONCACHEABLEBUFFER$$Length;
extern uint32_t Image$$RW_NONCACHEABLEBUFFER$$ZI$$Length;
address = (uint32_t)&Image$$RW_NONCACHEABLEBUFFER$$Base;
size = (uint32_t)&Image$$RW_NONCACHEABLEBUFFER$$Length + (uint32_t)&Image$$RW_NONCACHEABLEBUFFER$$ZI$$Length;
#elif defined ( __GNUC__ )
extern int __NONCACHEABLEBUFFER_BEGIN;
extern int __NONCACHEABLEBUFFER_END;
address = (uint32_t)&__NONCACHEABLEBUFFER_BEGIN;
size = (uint32_t)&__NONCACHEABLEBUFFER_END - (uint32_t)&__NONCACHEABLEBUFFER_BEGIN;
#else
#error "Compiler toolchain is unsupported"
#endif
if (size != 0)
{
/* Configure the MPU attributes as Normal Non Cacheable */
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
MPU_InitStruct.Number = index;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
MPU_InitStruct.SubRegionDisable = 0x00;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
MPU_AdjustRegionAddressSize(address, size, &MPU_InitStruct);
HAL_MPU_ConfigRegion(&MPU_InitStruct);
index++;
}
/* Initialize the region corresponding to the execution area
(external or internal flash or external or internal RAM
depending on scatter file definition) */
#if defined ( __ICCARM__ )
extern uint32_t __ICFEDIT_region_ROM_start__;
extern uint32_t __ICFEDIT_region_ROM_end__;
address = (uint32_t)&__ICFEDIT_region_ROM_start__;
size = (uint32_t)&__ICFEDIT_region_ROM_end__ - (uint32_t)&__ICFEDIT_region_ROM_start__ + 1;
#elif defined (__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$ER_ROM$$Base;
extern uint32_t Image$$ER_ROM$$Limit;
address = (uint32_t)&Image$$ER_ROM$$Base;
size = (uint32_t)&Image$$ER_ROM$$Limit-(uint32_t)&Image$$ER_ROM$$Base;
#elif defined ( __GNUC__ )
extern uint32_t __FLASH_BEGIN;
extern uint32_t __FLASH_SIZE;
address = (uint32_t)&__FLASH_BEGIN;
size = (uint32_t)&__FLASH_SIZE;
#else
#error "Compiler toolchain is unsupported"
#endif
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.Number = index;
MPU_InitStruct.SubRegionDisable = 0u;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
MPU_AdjustRegionAddressSize(address, size, &MPU_InitStruct);
HAL_MPU_ConfigRegion(&MPU_InitStruct);
index++;
/* Reset unused MPU regions */
for(; index < __MPU_REGIONCOUNT ; index++)
{
/* All unused regions disabled */
MPU_InitStruct.Enable = MPU_REGION_DISABLE;
MPU_InitStruct.Number = index;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
}
/* Enable the MPU */
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
}
/**
* @brief This function adjusts the MPU region Address and Size within an MPU configuration.
* @param Address memory address
* @param Size memory size
* @param pInit pointer to an MPU initialization structure
* @retval None
*/
static void MPU_AdjustRegionAddressSize(uint32_t Address, uint32_t Size, MPU_Region_InitTypeDef* pInit)
{
/* Compute the MPU region size */
pInit->Size = ((31 - __CLZ(Size)) - 1);
if (Size > (1u << (pInit->Size + 1)))
{
pInit->Size++;
}
uint32_t Modulo = Address % (1 << (pInit->Size - 1));
if (0 != Modulo)
{
/* Align address with MPU region size considering there is no need to increase the size */
pInit->BaseAddress = Address - Modulo;
}
else
{
pInit->BaseAddress = Address;
}
}
void board_init(void) {
HAL_Init();
MPU_Config();
SCB_EnableICache();
SCB_EnableDCache();
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
// Implemented in board.h
SystemClock_Config();

6
hw/bsp/stm32h7rs/family.cmake
View File

@@ -54,7 +54,7 @@ function(add_board_target BOARD_TARGET)
set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
if(NOT DEFINED LD_FILE_GNU)
set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash.ld)
set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${MCU_VARIANT}_flash.ld)
endif()
set(LD_FILE_Clang ${LD_FILE_GNU})
if(NOT DEFINED LD_FILE_IAR)
@@ -87,8 +87,8 @@ function(add_board_target BOARD_TARGET)
BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
BOARD_TUH_RHPORT=${RHPORT_HOST}
BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
SEGGER_RTT_SECTION="noncacheable_buffer"
BUFFER_SIZE_UP=0x3000
SEGGER_RTT_SECTION=\"noncacheable_buffer\"
BUFFER_SIZE_UP=0x300
)
update_board(${BOARD_TARGET})

6
hw/bsp/stm32h7rs/family.mk
View File

@@ -43,8 +43,8 @@ CFLAGS += \
-DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \
-DBOARD_TUH_RHPORT=${RHPORT_HOST} \
-DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \
-DSEGGER_RTT_SECTION=\"noncacheable_buffer\" \
-DBUFFER_SIZE_UP=0x3000 \
-DSEGGER_RTT_SECTION="noncacheable_buffer" \
-DBUFFER_SIZE_UP=0x300 \
# GCC Flags
CFLAGS_GCC += \
@@ -91,5 +91,5 @@ SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s
SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
# Linker
LD_FILE_GCC ?= $(ST_CMSIS)/Source/Templates/gcc/linker/$(MCU_VARIANT)_flash.ld
LD_FILE_GCC ?= $(FAMILY_PATH)/linker/$(MCU_VARIANT)_flash.ld
LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf

4
hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/stm32h7s3xx_flash.ld → hw/bsp/stm32h7rs/linker/stm32h7s3xx_flash.ld
View File

@@ -43,7 +43,7 @@ __FLASH_SIZE = 0x00010000;
__RAM_BEGIN = 0x24000000;
__RAM_SIZE = 0x4FC00;
__RAM_NONCACHEABLEBUFFER_SIZE = 0x4000;
__RAM_NONCACHEABLEBUFFER_SIZE = 0x400;
/* Memories definition */
MEMORY
@@ -182,7 +182,7 @@ SECTIONS
{
__NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */
KEEP(*(noncacheable_buffer))
__NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */
__NONCACHEABLEBUFFER_END = .; /* create symbol for end of section */
} > RAM_NONCACHEABLEBUFFER
/* User_heap_stack section, used to check that there is enough "DTCM" Ram type memory left */

1
hw/bsp/stm32l4/family.mk
View File

@@ -1,5 +1,4 @@
ST_FAMILY = l4
DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver

1
hw/bsp/stm32u5/family.mk
View File

@@ -1,5 +1,4 @@
ST_FAMILY = u5
DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver

2
hw/bsp/xmc4000/family.mk
View File

@@ -1,8 +1,6 @@
UF2_FAMILY_ID = 0x00
SDK_DIR = hw/mcu/infineon/mtb-xmclib-cat3
DEPS_SUBMODULES += ${SDK_DIR}
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m4