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@@ -105,7 +105,7 @@ bool tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length, bool i
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uint8_t const ep_out = cdch_data[dev_addr-1].ep_out;
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if ( usbh_edpt_busy(dev_addr, ep_out) ) return false;
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return usbh_edpt_xfer(dev_addr, ep_out, (void *) p_data, length);
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return usbh_edpt_xfer(dev_addr, ep_out, (void*)(uintptr_t) p_data, length);
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}
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bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is_notify)
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@@ -263,7 +263,7 @@ bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_
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memcpy(cbw.command, &cmd_write10, cbw.cmd_len);
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return tuh_msc_scsi_command(dev_addr, &cbw, (void*) buffer, complete_cb);
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return tuh_msc_scsi_command(dev_addr, &cbw, (void*)(uintptr_t) buffer, complete_cb);
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}
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#if 0
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@@ -1002,7 +1002,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
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tusb_control_request_t mod_request = *p_request;
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mod_request.wLength = CFG_TUD_ENDPOINT0_SIZE;
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tud_control_xfer(rhport, &mod_request, desc_device, CFG_TUD_ENDPOINT0_SIZE);
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return tud_control_xfer(rhport, &mod_request, desc_device, CFG_TUD_ENDPOINT0_SIZE);
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}else
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{
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return tud_control_xfer(rhport, p_request, desc_device, sizeof(tusb_desc_device_t));
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@@ -894,11 +894,10 @@ static bool enum_get_9byte_config_desc_complete(uint8_t dev_addr, tusb_control_r
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TU_ASSERT(XFER_RESULT_SUCCESS == result);
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// TODO not enough buffer to hold configuration descriptor
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tusb_desc_configuration_t const * desc_config = (tusb_desc_configuration_t const*) _usbh_ctrl_buf;
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uint16_t total_len;
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uint8_t const * desc_config = _usbh_ctrl_buf;
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// Use offsetof to avoid pointer to the odd/misaligned address
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memcpy(&total_len, (uint8_t*) desc_config + offsetof(tusb_desc_configuration_t, wTotalLength), 2);
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uint16_t const total_len = tu_le16toh( tu_unaligned_read16(desc_config + offsetof(tusb_desc_configuration_t, wTotalLength)) );
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TU_ASSERT(total_len <= CFG_TUH_ENUMERATION_BUFSIZE);
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@@ -128,7 +128,7 @@ static inline ehci_qtd_t* qtd_find_free (void);
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static inline ehci_qtd_t* qtd_next (ehci_qtd_t const * p_qtd);
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static inline void qtd_insert_to_qhd (ehci_qhd_t *p_qhd, ehci_qtd_t *p_qtd_new);
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static inline void qtd_remove_1st_from_qhd (ehci_qhd_t *p_qhd);
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static void qtd_init (ehci_qtd_t* p_qtd, void* buffer, uint16_t total_bytes);
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static void qtd_init (ehci_qtd_t* p_qtd, void const* buffer, uint16_t total_bytes);
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static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type);
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static inline ehci_link_t* list_next (ehci_link_t *p_link_pointer);
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@@ -392,7 +392,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
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ehci_qhd_t* qhd = &ehci_data.control[dev_addr].qhd;
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ehci_qtd_t* td = &ehci_data.control[dev_addr].qtd;
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qtd_init(td, (void*) setup_packet, 8);
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qtd_init(td, setup_packet, 8);
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td->pid = EHCI_PID_SETUP;
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td->int_on_complete = 1;
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td->next.terminate = 1;
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@@ -857,7 +857,7 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c
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}
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}
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static void qtd_init(ehci_qtd_t* p_qtd, void* buffer, uint16_t total_bytes)
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static void qtd_init(ehci_qtd_t* p_qtd, void const* buffer, uint16_t total_bytes)
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{
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tu_memclr(p_qtd, sizeof(ehci_qtd_t));
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@@ -636,7 +636,7 @@ void dcd_int_handler(uint8_t rhport)
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// 23.10.10.2 Operational model for setup transfers
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dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;
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dcd_event_setup_received(rhport, (uint8_t*) &_dcd_data.qhd[0][0].setup_request, true);
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dcd_event_setup_received(rhport, (uint8_t*)(uintptr_t) &_dcd_data.qhd[0][0].setup_request, true);
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}
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// 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
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@@ -259,7 +259,7 @@ static inline void pipe_wait_for_ready(unsigned num)
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static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
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{
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hw_fifo_t *reg = (hw_fifo_t*)fifo;
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volatile hw_fifo_t *reg = (volatile hw_fifo_t*) fifo;
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uintptr_t addr = (uintptr_t)buf;
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while (len >= 2) {
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reg->u16 = *(const uint16_t *)addr;
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@@ -275,7 +275,7 @@ static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
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static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
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{
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uint8_t *p = (uint8_t*)buf;
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uint8_t *reg = (uint8_t*)fifo; /* byte access is always at base register address */
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volatile uint8_t *reg = (volatile uint8_t*)fifo; /* byte access is always at base register address */
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while (len--) *p++ = *reg;
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}
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@@ -976,7 +976,7 @@ static void handle_rxflvl_ints(uint8_t rhport, USB_OTG_OUTEndpointTypeDef * out_
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if (xfer->ff)
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{
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// Ring buffer
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tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void *) rx_fifo, bcnt);
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tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void *)(uintptr_t) rx_fifo, bcnt);
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}
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else
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{
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@@ -1096,7 +1096,7 @@ static void handle_epin_ints(uint8_t rhport, USB_OTG_DeviceTypeDef * dev, USB_OT
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if (xfer->ff)
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{
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usb_fifo_t tx_fifo = FIFO_BASE(rhport, n);
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tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *) tx_fifo, packet_size);
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tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *)(uintptr_t) tx_fifo, packet_size);
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}
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else
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{
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@@ -314,13 +314,13 @@ static void dcd_reset(void)
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usb_in_ctrl_write(1 << CSR_USB_IN_CTRL_RESET_OFFSET);
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usb_out_ctrl_write(1 << CSR_USB_OUT_CTRL_RESET_OFFSET);
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memset((void *)rx_buffer, 0, sizeof(rx_buffer));
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memset((void *)rx_buffer_max, 0, sizeof(rx_buffer_max));
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memset((void *)rx_buffer_offset, 0, sizeof(rx_buffer_offset));
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memset((void *)(uintptr_t) rx_buffer, 0, sizeof(rx_buffer));
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memset((void *)(uintptr_t) rx_buffer_max, 0, sizeof(rx_buffer_max));
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memset((void *)(uintptr_t) rx_buffer_offset, 0, sizeof(rx_buffer_offset));
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memset((void *)tx_buffer, 0, sizeof(tx_buffer));
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memset((void *)tx_buffer_max, 0, sizeof(tx_buffer_max));
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memset((void *)tx_buffer_offset, 0, sizeof(tx_buffer_offset));
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memset((void *)(uintptr_t) tx_buffer, 0, sizeof(tx_buffer));
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memset((void *)(uintptr_t) tx_buffer_max, 0, sizeof(tx_buffer_max));
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memset((void *)(uintptr_t) tx_buffer_offset, 0, sizeof(tx_buffer_offset));
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tx_ep = 0;
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tx_active = false;
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