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better multiple interfaces support for cdc device

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This commit is contained in:
hathach
2018-07-13 00:32:02 +07:00
parent a4292e5906
commit a623f0c179
5 changed files with 112 additions and 78 deletions
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134
src/class/cdc/cdc_device.c
View File

@@ -51,18 +51,19 @@
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
typedef struct {
CFG_TUSB_MEM_ALIGN cdc_line_coding_t line_coding;
typedef struct
{
/*------------- usbd_itf_t compatible -------------*/
uint8_t itf_num;
uint8_t ep_count;
uint8_t ep_notif;
uint8_t ep_in;
uint8_t ep_out;
cdc_acm_capability_t acm_cap;
// Bit 0: DTR (Data Terminal Ready), Bit 1: RTS (Request to Send)
uint8_t line_state;
CFG_TUSB_MEM_ALIGN cdc_line_coding_t line_coding;
}cdcd_interface_t;
//--------------------------------------------------------------------+
@@ -71,8 +72,11 @@ typedef struct {
CFG_TUSB_ATTR_USBRAM CFG_TUSB_MEM_ALIGN static uint8_t _tmp_rx_buf[64];
CFG_TUSB_ATTR_USBRAM CFG_TUSB_MEM_ALIGN static uint8_t _tmp_tx_buf[64];
TU_FIFO_DEF(_rx_ff, CFG_TUD_CDC_RX_BUFSIZE, uint8_t, true);
TU_FIFO_DEF(_tx_ff, CFG_TUD_CDC_TX_BUFSIZE, uint8_t, false);
uint8_t _rx_ff_buf[CFG_TUD_CDC][CFG_TUD_CDC_RX_BUFSIZE];
uint8_t _tx_ff_buf[CFG_TUD_CDC][CFG_TUD_CDC_RX_BUFSIZE];
tu_fifo_t _rx_ff[CFG_TUD_CDC];
tu_fifo_t _tx_ff[CFG_TUD_CDC];
CFG_TUSB_ATTR_USBRAM
static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC];
@@ -80,66 +84,66 @@ static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC];
//--------------------------------------------------------------------+
// APPLICATION API
//--------------------------------------------------------------------+
bool tud_cdc_n_connected(uint8_t rhport)
bool tud_cdc_n_connected(uint8_t itf)
{
// DTR (bit 0) active isconsidered as connected
return BIT_TEST_(_cdcd_itf[rhport].line_state, 0);
return BIT_TEST_(_cdcd_itf[itf].line_state, 0);
}
uint8_t tud_cdc_n_get_line_state (uint8_t rhport)
uint8_t tud_cdc_n_get_line_state (uint8_t itf)
{
return _cdcd_itf[rhport].line_state;
return _cdcd_itf[itf].line_state;
}
void tud_cdc_n_get_line_coding (uint8_t rhport, cdc_line_coding_t* coding)
void tud_cdc_n_get_line_coding (uint8_t itf, cdc_line_coding_t* coding)
{
(*coding) = _cdcd_itf[0].line_coding;
(*coding) = _cdcd_itf[itf].line_coding;
}
//--------------------------------------------------------------------+
// READ API
//--------------------------------------------------------------------+
uint32_t tud_cdc_n_available(uint8_t rhport)
uint32_t tud_cdc_n_available(uint8_t itf)
{
return tu_fifo_count(&_rx_ff);
return tu_fifo_count(&_rx_ff[itf]);
}
int8_t tud_cdc_n_read_char(uint8_t rhport)
int8_t tud_cdc_n_read_char(uint8_t itf)
{
int8_t ch;
return tu_fifo_read(&_rx_ff, &ch) ? ch : (-1);
return tu_fifo_read(&_rx_ff[itf], &ch) ? ch : (-1);
}
uint32_t tud_cdc_n_read(uint8_t rhport, void* buffer, uint32_t bufsize)
uint32_t tud_cdc_n_read(uint8_t itf, void* buffer, uint32_t bufsize)
{
return tu_fifo_read_n(&_rx_ff, buffer, bufsize);
return tu_fifo_read_n(&_rx_ff[itf], buffer, bufsize);
}
//--------------------------------------------------------------------+
// WRITE API
//--------------------------------------------------------------------+
uint32_t tud_cdc_n_write_char(uint8_t rhport, char ch)
uint32_t tud_cdc_n_write_char(uint8_t itf, char ch)
{
return tu_fifo_write(&_tx_ff, &ch) ? 1 : 0;
return tu_fifo_write(&_tx_ff[itf], &ch) ? 1 : 0;
}
uint32_t tud_cdc_n_write(uint8_t rhport, void const* buffer, uint32_t bufsize)
uint32_t tud_cdc_n_write(uint8_t itf, void const* buffer, uint32_t bufsize)
{
return tu_fifo_write_n(&_tx_ff, buffer, bufsize);
return tu_fifo_write_n(&_tx_ff[itf], buffer, bufsize);
}
bool tud_cdc_n_flush (uint8_t rhport)
bool tud_cdc_n_flush (uint8_t itf)
{
uint8_t edpt = _cdcd_itf[rhport].ep_in;
VERIFY( !dcd_edpt_busy(rhport, edpt) ); // skip if previous transfer not complete
uint8_t edpt = _cdcd_itf[itf].ep_in;
VERIFY( !dcd_edpt_busy(TUD_RHPORT, edpt) ); // skip if previous transfer not complete
uint16_t count = tu_fifo_read_n(&_tx_ff, _tmp_tx_buf, sizeof(_tmp_tx_buf));
uint16_t count = tu_fifo_read_n(&_tx_ff[itf], _tmp_tx_buf, sizeof(_tmp_tx_buf));
VERIFY( tud_cdc_n_connected(rhport) ); // fifo is empty if not connected
VERIFY( tud_cdc_n_connected(itf) ); // fifo is empty if not connected
if ( count ) TU_ASSERT( dcd_edpt_xfer(rhport, edpt, _tmp_tx_buf, count) );
if ( count ) TU_ASSERT( dcd_edpt_xfer(TUD_RHPORT, edpt, _tmp_tx_buf, count) );
return true;
}
@@ -152,13 +156,10 @@ void cdcd_init(void)
{
arrclr_(_cdcd_itf);
// default line coding is : stop bit = 1, parity = none, data bits = 8
for(uint8_t i=0; i<CFG_TUD_CDC; i++)
{
_cdcd_itf[i].line_coding.bit_rate = 115200;
_cdcd_itf[i].line_coding.stop_bits = 0;
_cdcd_itf[i].line_coding.parity = 0;
_cdcd_itf[i].line_coding.data_bits = 8;
tu_fifo_config(&_rx_ff[i], _rx_ff_buf[i], CFG_TUD_CDC_RX_BUFSIZE, 1, true);
tu_fifo_config(&_tx_ff[i], _tx_ff_buf[i], CFG_TUD_CDC_TX_BUFSIZE, 1, false);
}
}
@@ -172,20 +173,27 @@ tusb_error_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const * p_interface
return TUSB_ERROR_CDC_UNSUPPORTED_PROTOCOL;
}
uint8_t const * p_desc = descriptor_next ( (uint8_t const *) p_interface_desc );
cdcd_interface_t * p_cdc = &_cdcd_itf[rhport];
// Find available interface
cdcd_interface_t * p_cdc = NULL;
for(uint8_t i=0; i<CFG_TUD_CDC; i++)
{
if ( _cdcd_itf[i].ep_count == 0 )
{
p_cdc = &_cdcd_itf[i];
break;
}
}
//------------- Communication Interface -------------//
//------------- Control Interface -------------//
p_cdc->itf_num = p_interface_desc->bInterfaceNumber;
p_cdc->ep_count = p_interface_desc->bNumEndpoints;
uint8_t const * p_desc = descriptor_next ( (uint8_t const *) p_interface_desc );
(*p_length) = sizeof(tusb_desc_interface_t);
// Communication Functional Descriptors
while( TUSB_DESC_CLASS_SPECIFIC == p_desc[DESCRIPTOR_OFFSET_TYPE] )
{
if ( CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc) )
{ // save ACM bmCapabilities
p_cdc->acm_cap = ((cdc_desc_func_acm_t const *) p_desc)->bmCapabilities;
}
(*p_length) += p_desc[DESCRIPTOR_OFFSET_LENGTH];
p_desc = descriptor_next(p_desc);
}
@@ -204,6 +212,10 @@ tusb_error_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const * p_interface
if ( (TUSB_DESC_INTERFACE == p_desc[DESCRIPTOR_OFFSET_TYPE]) &&
(TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const *) p_desc)->bInterfaceClass) )
{
// p_cdc->itf_num =
p_cdc->ep_count += ((tusb_desc_interface_t const *) p_desc)->bNumEndpoints;
// next to endpoint descritpor
(*p_length) += p_desc[DESCRIPTOR_OFFSET_LENGTH];
p_desc = descriptor_next(p_desc);
@@ -214,8 +226,6 @@ tusb_error_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const * p_interface
(*p_length) += 2*sizeof(tusb_desc_endpoint_t);
}
p_cdc->itf_num = p_interface_desc->bInterfaceNumber;
// Prepare for incoming data
TU_ASSERT( dcd_edpt_xfer(rhport, p_cdc->ep_out, _tmp_rx_buf, sizeof(_tmp_rx_buf)), TUSB_ERROR_DCD_EDPT_XFER);
@@ -225,10 +235,15 @@ tusb_error_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const * p_interface
void cdcd_close(uint8_t rhport)
{
// no need to close opened pipe, dcd bus reset will put controller's endpoints to default state
memclr_(&_cdcd_itf[rhport], sizeof(cdcd_interface_t));
(void) rhport;
tu_fifo_clear(&_rx_ff);
tu_fifo_clear(&_tx_ff);
arrclr_(_cdcd_itf);
for(uint8_t i=0; i<CFG_TUD_CDC; i++)
{
tu_fifo_clear(&_rx_ff[i]);
tu_fifo_clear(&_tx_ff[i]);
}
}
tusb_error_t cdcd_control_request_st(uint8_t rhport, tusb_control_request_t const * p_request)
@@ -238,16 +253,19 @@ tusb_error_t cdcd_control_request_st(uint8_t rhport, tusb_control_request_t cons
//------------- Class Specific Request -------------//
if (p_request->bmRequestType_bit.type != TUSB_REQ_TYPE_CLASS) return TUSB_ERROR_DCD_CONTROL_REQUEST_NOT_SUPPORT;
// TODO Support multiple interface
// TODO Support multiple interfaces
uint8_t const itf = 0;
cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
if ( (CDC_REQUEST_GET_LINE_CODING == p_request->bRequest) || (CDC_REQUEST_SET_LINE_CODING == p_request->bRequest) )
{
uint16_t len = min16_of(sizeof(cdc_line_coding_t), p_request->wLength);
usbd_control_xfer_st(rhport, p_request->bmRequestType_bit.direction, (uint8_t*) &_cdcd_itf[0].line_coding, len);
usbd_control_xfer_st(rhport, p_request->bmRequestType_bit.direction, &p_cdc->line_coding, len);
// Invoke callback
if (CDC_REQUEST_SET_LINE_CODING == p_request->bRequest)
{
if ( tud_cdc_line_coding_cb ) tud_cdc_line_coding_cb(rhport, &_cdcd_itf[0].line_coding);
if ( tud_cdc_line_coding_cb ) tud_cdc_line_coding_cb(itf, &p_cdc->line_coding);
}
}
else if (CDC_REQUEST_SET_CONTROL_LINE_STATE == p_request->bRequest )
@@ -257,14 +275,13 @@ tusb_error_t cdcd_control_request_st(uint8_t rhport, tusb_control_request_t cons
// This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR (Data Terminal Ready)
// Bit 1: Carrier control for half-duplex modems.
// This signal corresponds to V.24 signal 105 and RS-232 signal RTS (Request to Send)
cdcd_interface_t * p_cdc = &_cdcd_itf[rhport];
p_cdc->line_state = (uint8_t) p_request->wValue;
dcd_control_status(rhport, p_request->bmRequestType_bit.direction); // ACK control request
// Invoke callback
if ( tud_cdc_line_state_cb) tud_cdc_line_state_cb(rhport, BIT_TEST_(p_request->wValue, 0), BIT_TEST_(p_request->wValue, 1));
if ( tud_cdc_line_state_cb) tud_cdc_line_state_cb(itf, BIT_TEST_(p_request->wValue, 0), BIT_TEST_(p_request->wValue, 1));
}
else
{
@@ -276,17 +293,19 @@ tusb_error_t cdcd_control_request_st(uint8_t rhport, tusb_control_request_t cons
tusb_error_t cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, tusb_event_t event, uint32_t xferred_bytes)
{
cdcd_interface_t const * p_cdc = &_cdcd_itf[rhport];
// TODO Support multiple interfaces
uint8_t const itf = 0;
cdcd_interface_t const * p_cdc = &_cdcd_itf[itf];
if ( ep_addr == p_cdc->ep_out )
{
tu_fifo_write_n(&_rx_ff, _tmp_rx_buf, xferred_bytes);
tu_fifo_write_n(&_rx_ff[itf], _tmp_rx_buf, xferred_bytes);
// preparing for next
TU_ASSERT( dcd_edpt_xfer(rhport, p_cdc->ep_out, _tmp_rx_buf, sizeof(_tmp_rx_buf)), TUSB_ERROR_DCD_EDPT_XFER );
// fire callback
if (tud_cdc_rx_cb) tud_cdc_rx_cb(rhport);
if (tud_cdc_rx_cb) tud_cdc_rx_cb(itf);
}
return TUSB_ERROR_NONE;
@@ -295,7 +314,10 @@ tusb_error_t cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, tusb_event_t event, u
#if CFG_TUD_CDC_FLUSH_ON_SOF
void cdcd_sof(uint8_t rhport)
{
tud_cdc_n_flush(rhport);
for(uint8_t i=0; i<CFG_TUD_CDC; i++)
{
tud_cdc_n_flush(i);
}
}
#endif

28
src/class/cdc/cdc_device.h
View File

@@ -56,24 +56,24 @@
// APPLICATION API (Multiple Interfaces)
// CFG_TUD_CDC > 1
//--------------------------------------------------------------------+
bool tud_cdc_n_connected (uint8_t rhport);
uint8_t tud_cdc_n_get_line_state (uint8_t rhport);
void tud_cdc_n_get_line_coding (uint8_t rhport, cdc_line_coding_t* coding);
bool tud_cdc_n_connected (uint8_t itf);
uint8_t tud_cdc_n_get_line_state (uint8_t itf);
void tud_cdc_n_get_line_coding (uint8_t itf, cdc_line_coding_t* coding);
uint32_t tud_cdc_n_available (uint8_t rhport);
int8_t tud_cdc_n_read_char (uint8_t rhport);
uint32_t tud_cdc_n_read (uint8_t rhport, void* buffer, uint32_t bufsize);
uint32_t tud_cdc_n_available (uint8_t itf);
int8_t tud_cdc_n_read_char (uint8_t itf);
uint32_t tud_cdc_n_read (uint8_t itf, void* buffer, uint32_t bufsize);
uint32_t tud_cdc_n_write_char (uint8_t rhport, char ch);
uint32_t tud_cdc_n_write (uint8_t rhport, void const* buffer, uint32_t bufsize);
bool tud_cdc_n_flush (uint8_t rhport);
uint32_t tud_cdc_n_write_char (uint8_t itf, char ch);
uint32_t tud_cdc_n_write (uint8_t itf, void const* buffer, uint32_t bufsize);
bool tud_cdc_n_flush (uint8_t itf);
//--------------------------------------------------------------------+
// APPLICATION API (Interface0)
//--------------------------------------------------------------------+
static inline bool tud_cdc_connected (void) { return tud_cdc_n_connected(0); }
static inline uint8_t tud_cdc_get_line_state (uint8_t rhport) { return tud_cdc_n_get_line_state(0); }
static inline void tud_cdc_get_line_coding (uint8_t rhport, cdc_line_coding_t* coding) { return tud_cdc_get_line_coding(0, coding); }
static inline uint8_t tud_cdc_get_line_state (void) { return tud_cdc_n_get_line_state(0); }
static inline void tud_cdc_get_line_coding (cdc_line_coding_t* coding) { return tud_cdc_n_get_line_coding(0, coding);}
static inline uint32_t tud_cdc_available (void) { return tud_cdc_n_available(0); }
static inline int8_t tud_cdc_read_char (void) { return tud_cdc_n_read_char(0); }
@@ -86,9 +86,9 @@ static inline bool tud_cdc_flush (void)
//--------------------------------------------------------------------+
// APPLICATION CALLBACK API (WEAK is optional)
//--------------------------------------------------------------------+
ATTR_WEAK void tud_cdc_rx_cb(uint8_t rhport);
ATTR_WEAK void tud_cdc_line_state_cb(uint8_t rhport, bool dtr, bool rts);
ATTR_WEAK void tud_cdc_line_coding_cb(uint8_t rhport, cdc_line_coding_t const* p_line_coding);
ATTR_WEAK void tud_cdc_rx_cb(uint8_t itf);
ATTR_WEAK void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts);
ATTR_WEAK void tud_cdc_line_coding_cb(uint8_t itf, cdc_line_coding_t const* p_line_coding);
//--------------------------------------------------------------------+
// USBD-CLASS DRIVER API

2
src/device/usbd.c
View File

@@ -528,6 +528,8 @@ void dcd_bus_event(uint8_t rhport, usbd_bus_event_type_t bus_event)
varclr_(&_usbd_dev);
osal_queue_flush(_usbd_q);
osal_semaphore_reset_isr(_usbd_ctrl_sem);
// TODO move to unplugged
for (uint8_t i = 0; i < USBD_CLASS_DRIVER_COUNT; i++)
{
if ( usbd_class_drivers[i].close ) usbd_class_drivers[i].close( rhport );

10
src/device/usbd_pvt.h
View File

@@ -45,6 +45,14 @@
// for used by usbd_control_xfer_st() only, must not be used directly
extern osal_semaphore_t _usbd_ctrl_sem;
typedef struct
{
uint8_t itf_num;
uint8_t ep_count;
uint8_t ep_arr[1];
}usbd_itf_t;
//--------------------------------------------------------------------+
// INTERNAL API for stack management
//--------------------------------------------------------------------+
@@ -63,7 +71,7 @@ tusb_error_t usbd_open_edpt_pair(uint8_t rhport, tusb_desc_endpoint_t const* p_d
do {\
if (_len) { \
tusb_error_t err;\
dcd_control_xfer(_rhport, _dir, _buffer, _len);\
dcd_control_xfer(_rhport, _dir, (uint8_t*) _buffer, _len);\
osal_semaphore_wait( _usbd_ctrl_sem, OSAL_TIMEOUT_CONTROL_XFER, &err );\
STASK_ASSERT_ERR( err );\
}\

2
src/tusb_option.h
View File

@@ -107,6 +107,8 @@
#define MODE_HOST_SUPPORTED (CONTROLLER_HOST_NUMBER > 0)
#define MODE_DEVICE_SUPPORTED (CONTROLLER_DEVICE_NUMBER > 0)
#define TUD_RHPORT ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE) ? 0 : ((CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) ? 1 : -1))
#if !MODE_HOST_SUPPORTED && !MODE_DEVICE_SUPPORTED
#error please configure at least 1 CFG_TUSB_CONTROLLER_N_MODE to OPT_MODE_HOST and/or OPT_MODE_DEVICE
#endif