change IAR TUSB_CFG_ATTR_USBRAM to _Pragma("location=\".ahb_sram1\"") instead of @ .ahb_sram1 so that we can place it before the variable for a cleaner code
change pipe xfer API buffer from void* to uint8_t* change FIFO_DEF to have a separated buffer to be compatible with IAR\ refractor IAR data alignment pragma
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@@ -62,7 +62,7 @@ typedef struct {
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ATTR_USB_MIN_ALIGNMENT msc_cmd_status_wrapper_t csw;
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}mscd_interface_t;
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STATIC_VAR mscd_interface_t mscd_data TUSB_CFG_ATTR_USBRAM;
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TUSB_CFG_ATTR_USBRAM STATIC_VAR mscd_interface_t mscd_data;
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//--------------------------------------------------------------------+
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// INTERNAL OBJECT & FUNCTION DECLARATION
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//--------------------------------------------------------------------+
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@@ -109,7 +109,7 @@ tusb_error_t mscd_open(uint8_t coreid, tusb_descriptor_interface_t const * p_int
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(*p_length) += sizeof(tusb_descriptor_interface_t) + 2*sizeof(tusb_descriptor_endpoint_t);
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//------------- Queue Endpoint OUT for Command Block Wrapper -------------//
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ASSERT_STATUS( dcd_pipe_xfer(p_msc->edpt_out, &p_msc->cbw, sizeof(msc_cmd_block_wrapper_t), true) );
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ASSERT_STATUS( dcd_pipe_xfer(p_msc->edpt_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cmd_block_wrapper_t), true) );
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return TUSB_ERROR_NONE;
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}
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@@ -202,10 +202,10 @@ tusb_error_t mscd_xfer_cb(endpoint_handle_t edpt_hdl, tusb_event_t event, uint32
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// Either bulk in & out can be stalled in the data phase, dcd must make sure these queued transfer will be resumed after host clear stall
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if (!is_waiting_read10_write10)
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{
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ASSERT_STATUS( dcd_pipe_xfer( p_msc->edpt_in , p_csw, sizeof(msc_cmd_status_wrapper_t), false) );
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ASSERT_STATUS( dcd_pipe_xfer( p_msc->edpt_in , (uint8_t*) p_csw, sizeof(msc_cmd_status_wrapper_t), false) );
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//------------- Queue the next CBW -------------//
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ASSERT_STATUS( dcd_pipe_xfer( p_msc->edpt_out, p_cbw, sizeof(msc_cmd_block_wrapper_t), true) );
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ASSERT_STATUS( dcd_pipe_xfer( p_msc->edpt_out, (uint8_t*) p_cbw, sizeof(msc_cmd_block_wrapper_t), true) );
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}
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return TUSB_ERROR_NONE;
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