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change IAR TUSB_CFG_ATTR_USBRAM to _Pragma("location=\".ahb_sram1\"") instead of @ .ahb_sram1 so that we can place it before the variable for a cleaner code

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change pipe xfer API buffer from void* to uint8_t*
change FIFO_DEF to have a separated buffer to be compatible with IAR\
refractor IAR data alignment pragma
This commit is contained in:
hathach
2014-03-10 13:13:13 +07:00
parent 1c73d2f923
commit ad72db5aea
26 changed files with 1029 additions and 1020 deletions
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2
demos/device/src/tusb_config.h
View File

@@ -123,7 +123,7 @@
#elif __ICCARM__ // compiled with IAR
#define TUSB_CFG_ATTR_USBRAM @ ".ahb_sram1"
#define TUSB_CFG_ATTR_USBRAM _Pragma("location=\".ahb_sram1\"")
#else

133
demos/host/host_os_none/.cproject
View File

@@ -123,7 +123,7 @@
<builder buildPath="${workspace_loc:/host/Debug}" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.CWDLocator" id="com.crt.advproject.builder.exe.debug.1432862600" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug"/>
<tool id="com.crt.advproject.cpp.exe.debug.964171687" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug"/>
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${CFLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GCCErrorParser" id="com.crt.advproject.gcc.exe.debug.502985594" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug">
<option id="com.crt.advproject.gcc.arch.625803892" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm3" valueType="enumerated"/>
<option id="com.crt.advproject.gcc.arch.625803892" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm4" valueType="enumerated"/>
<option id="com.crt.advproject.gcc.thumb.1149795974" name="Thumb mode" superClass="com.crt.advproject.gcc.thumb" value="true" valueType="boolean"/>
<option id="gnu.c.compiler.option.preprocessor.def.symbols.510918973" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" valueType="definedSymbols">
<listOptionValue builtIn="false" value="__REDLIB__"/>
@@ -151,7 +151,7 @@
<inputType id="com.crt.advproject.compiler.input.772057054" superClass="com.crt.advproject.compiler.input"/>
</tool>
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.gas.exe.debug.973267950" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.debug">
<option id="com.crt.advproject.gas.arch.733211533" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm3" valueType="enumerated"/>
<option id="com.crt.advproject.gas.arch.733211533" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm4" valueType="enumerated"/>
<option id="com.crt.advproject.gas.thumb.154920324" name="Thumb mode" superClass="com.crt.advproject.gas.thumb" value="true" valueType="boolean"/>
<option id="gnu.both.asm.option.flags.crt.220166654" name="Assembler flags" superClass="gnu.both.asm.option.flags.crt" value="-c -x assembler-with-cpp -D__REDLIB__ -DDEBUG -D__CODE_RED" valueType="string"/>
<option id="com.crt.advproject.gas.fpu.464699791" name="Floating point" superClass="com.crt.advproject.gas.fpu" value="com.crt.advproject.gas.fpu.fpv4" valueType="enumerated"/>
@@ -160,7 +160,7 @@
</tool>
<tool id="com.crt.advproject.link.cpp.exe.debug.1510590263" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.debug"/>
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GLDErrorParser" id="com.crt.advproject.link.exe.debug.1770663329" name="MCU Linker" superClass="com.crt.advproject.link.exe.debug">
<option id="com.crt.advproject.link.arch.1264750550" name="Architecture" superClass="com.crt.advproject.link.arch" value="com.crt.advproject.link.target.cm3" valueType="enumerated"/>
<option id="com.crt.advproject.link.arch.1264750550" name="Architecture" superClass="com.crt.advproject.link.arch" value="com.crt.advproject.link.target.cm4" valueType="enumerated"/>
<option id="com.crt.advproject.link.thumb.1129500777" name="Thumb mode" superClass="com.crt.advproject.link.thumb" value="true" valueType="boolean"/>
<option id="com.crt.advproject.link.script.1484718299" name="Linker script" superClass="com.crt.advproject.link.script" value="&quot;host_os_none_Board_EA4357.ld&quot;" valueType="string"/>
<option id="com.crt.advproject.link.manage.887685321" name="Manage linker script" superClass="com.crt.advproject.link.manage" value="true" valueType="boolean"/>
@@ -566,73 +566,86 @@
<storageModule moduleId="com.crt.config">
<projectStorage>&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
&lt;TargetConfig&gt;&#13;
&lt;Properties property_0="" property_3="NXP" property_4="LPC1769" property_count="5" version="1"/&gt;&#13;
&lt;infoList vendor="NXP"&gt;&lt;info chip="LPC1769" match_id="0x26113F37" name="LPC1769" package="lpc17_lqfp100.xml"&gt;&lt;chip&gt;&lt;name&gt;LPC1769&lt;/name&gt;&#13;
&lt;family&gt;LPC17xx&lt;/family&gt;&#13;
&lt;Properties property_0="" property_2="LPC18x7_43x7_2x512_BootA.cfx" property_3="NXP" property_4="LPC4357" property_count="5" version="1"/&gt;&#13;
&lt;infoList vendor="NXP"&gt;&lt;info chip="LPC4357" flash_driver="LPC18x7_43x7_2x512_BootA.cfx" match_id="0x0" name="LPC4357" resetscript="LPC18LPC43InternalFLASHBootResetscript.scp" stub="crt_emu_lpc18_43_nxp"&gt;&lt;chip&gt;&lt;name&gt;LPC4357&lt;/name&gt;&#13;
&lt;family&gt;LPC43xx&lt;/family&gt;&#13;
&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
&lt;clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/&gt;&#13;
&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
&lt;memory id="RAM" type="RAM"/&gt;&#13;
&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
&lt;memoryInstance derived_from="Flash" id="MFlash512" location="0x0" size="0x80000"/&gt;&#13;
&lt;memoryInstance derived_from="Flash" id="MFlashA512" location="0x1a000000" size="0x80000"/&gt;&#13;
&lt;memoryInstance derived_from="Flash" id="MFlashB512" location="0x1b000000" size="0x80000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RamLoc32" location="0x10000000" size="0x8000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RamAHB32" location="0x2007c000" size="0x8000"/&gt;&#13;
&lt;prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/&gt;&#13;
&lt;prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_NVIC" id="NVIC" location="0xE000E000"/&gt;&#13;
&lt;peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM0&amp;amp;0x1" id="TIMER0" location="0x40004000"/&gt;&#13;
&lt;peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM1&amp;amp;0x1" id="TIMER1" location="0x40008000"/&gt;&#13;
&lt;peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM2&amp;amp;0x1" id="TIMER2" location="0x40090000"/&gt;&#13;
&lt;peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM3&amp;amp;0x1" id="TIMER3" location="0x40094000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_RIT" enable="SYSCTL.PCONP.PCRIT&amp;amp;0x1" id="RIT" location="0x400B0000"/&gt;&#13;
&lt;peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO0" location="0x2009C000"/&gt;&#13;
&lt;peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO1" location="0x2009C020"/&gt;&#13;
&lt;peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO2" location="0x2009C040"/&gt;&#13;
&lt;peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO3" location="0x2009C060"/&gt;&#13;
&lt;peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&amp;amp;0x1" id="GPIO4" location="0x2009C080"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_I2S" enable="SYSCTL.PCONP&amp;amp;0x08000000" id="I2S" location="0x400A8000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_SYSCTL" id="SYSCTL" location="0x400FC000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_DAC" enable="PCB.PINSEL1.P0_26&amp;amp;0x2=2" id="DAC" location="0x4008C000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17xx_UART" enable="SYSCTL.PCONP.PCUART0&amp;amp;0x1" id="UART0" location="0x4000C000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17xx_UART_MODEM" enable="SYSCTL.PCONP.PCUART1&amp;amp;0x1" id="UART1" location="0x40010000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17xx_UART" enable="SYSCTL.PCONP.PCUART2&amp;amp;0x1" id="UART2" location="0x40098000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17xx_UART" enable="SYSCTL.PCONP.PCUART3&amp;amp;0x1" id="UART3" location="0x4009C000"/&gt;&#13;
&lt;peripheralInstance derived_from="SPI" enable="SYSCTL.PCONP.PCSPI&amp;amp;0x1" id="SPI" location="0x40020000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_SSP" enable="SYSCTL.PCONP.PCSSP0&amp;amp;0x1" id="SSP0" location="0x40088000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_SSP" enable="SYSCTL.PCONP.PCSSP1&amp;amp;0x1" id="SSP1" location="0x40030000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_ADC" enable="SYSCTL.PCONP.PCAD&amp;amp;0x1" id="ADC" location="0x40034000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_USBINTST" enable="USBCLKCTL.USBClkCtrl&amp;amp;0x12" id="USBINTSTAT" location="0x400fc1c0"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_USB_CLK_CTL" id="USBCLKCTL" location="0x5000cff4"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_USBDEV" enable="USBCLKCTL.USBClkSt&amp;amp;0x12=0x12" id="USBDEV" location="0x5000C200"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_PWM" enable="SYSCTL.PCONP.PWM1&amp;amp;0x1" id="PWM" location="0x40018000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_I2C" enable="SYSCTL.PCONP.PCI2C0&amp;amp;0x1" id="I2C0" location="0x4001C000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_I2C" enable="SYSCTL.PCONP.PCI2C1&amp;amp;0x1" id="I2C1" location="0x4005C000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_I2C" enable="SYSCTL.PCONP.PCI2C2&amp;amp;0x1" id="I2C2" location="0x400A0000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_DMA" enable="SYSCTL.PCONP.PCGPDMA&amp;amp;0x1" id="DMA" location="0x50004000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_ENET" enable="SYSCTL.PCONP.PCENET&amp;amp;0x1" id="ENET" location="0x50000000"/&gt;&#13;
&lt;peripheralInstance derived_from="CM3_DCR" id="DCR" location="0xE000EDF0"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_PCB" id="PCB" location="0x4002c000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_QEI" enable="SYSCTL.PCONP.PCQEI&amp;amp;0x1" id="QEI" location="0x400bc000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_USBHOST" enable="USBCLKCTL.USBClkSt&amp;amp;0x11=0x11" id="USBHOST" location="0x5000C000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_USBOTG" enable="USBCLKCTL.USBClkSt&amp;amp;0x1c=0x1c" id="USBOTG" location="0x5000C000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_RTC" enable="SYSCTL.PCONP.PCRTC&amp;amp;0x1" id="RTC" location="0x40024000"/&gt;&#13;
&lt;peripheralInstance derived_from="MPU" id="MPU" location="0xE000ED90"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC1x_WDT" id="WDT" location="0x40000000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_FLASHCFG" id="FLASHACCEL" location="0x400FC000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO_INT" id="GPIOINTMAP" location="0x40028080"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_CANAFR" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1|SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANAFR" location="0x4003C000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_CANCEN" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1|SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANCEN" location="0x40040000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_CANWAKESLEEP" id="CANWAKESLEEP" location="0x400FC110"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_CANCON" enable="SYSCTL.PCONP.PCCAN1&amp;amp;0x1" id="CANCON1" location="0x40044000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_CANCON" enable="SYSCTL.PCONP.PCCAN2&amp;amp;0x1" id="CANCON2" location="0x40048000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_MCPWM" enable="SYSCTL.PCONP.PCMCPWM&amp;amp;0x1" id="MCPWM" location="0x400B8000"/&gt;&#13;
&lt;peripheralInstance derived_from="LPC17_FMC" id="FMC" location="0x40084000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RamLoc40" location="0x10080000" size="0xa000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RamAHB32" location="0x20000000" size="0x8000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RamAHB16" location="0x20008000" size="0x4000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RamAHB_ETB16" location="0x2000c000" size="0x4000"/&gt;&#13;
&lt;prog_flash blocksz="0x2000" location="0x1a000000" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/&gt;&#13;
&lt;prog_flash blocksz="0x10000" location="0x1a010000" maxprgbuff="0x400" progwithcode="TRUE" size="0x70000"/&gt;&#13;
&lt;prog_flash blocksz="0x2000" location="0x1b000000" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/&gt;&#13;
&lt;prog_flash blocksz="0x10000" location="0x1b010000" maxprgbuff="0x400" progwithcode="TRUE" size="0x70000"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_ITM" id="ITM" location="0xe0000000"/&gt;&#13;
&lt;peripheralInstance derived_from="SCT" id="SCT" location="0x40000000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPDMA" id="GPDMA" location="0x40002000"/&gt;&#13;
&lt;peripheralInstance derived_from="SPIFI" id="SPIFI" location="0x40003000"/&gt;&#13;
&lt;peripheralInstance derived_from="SDMMC" id="SDMMC" location="0x40004000"/&gt;&#13;
&lt;peripheralInstance derived_from="EMC" id="EMC" location="0x40005000"/&gt;&#13;
&lt;peripheralInstance derived_from="USB0" id="USB0" location="0x40006000"/&gt;&#13;
&lt;peripheralInstance derived_from="USB1" id="USB1" location="0x40007000"/&gt;&#13;
&lt;peripheralInstance derived_from="LCD" id="LCD" location="0x40008000"/&gt;&#13;
&lt;peripheralInstance derived_from="EEPROM" id="EEPROM" location="0x4000e000"/&gt;&#13;
&lt;peripheralInstance derived_from="ETHERNET" id="ETHERNET" location="0x40010000"/&gt;&#13;
&lt;peripheralInstance derived_from="ATIMER" id="ATIMER" location="0x40040000"/&gt;&#13;
&lt;peripheralInstance derived_from="REGFILE" id="REGFILE" location="0x40041000"/&gt;&#13;
&lt;peripheralInstance derived_from="PMC" id="PMC" location="0x40042000"/&gt;&#13;
&lt;peripheralInstance derived_from="CREG" id="CREG" location="0x40043000"/&gt;&#13;
&lt;peripheralInstance derived_from="EVENTROUTER" id="EVENTROUTER" location="0x40044000"/&gt;&#13;
&lt;peripheralInstance derived_from="RTC" id="RTC" location="0x40046000"/&gt;&#13;
&lt;peripheralInstance derived_from="CGU" id="CGU" location="0x40050000"/&gt;&#13;
&lt;peripheralInstance derived_from="CCU1" id="CCU1" location="0x40051000"/&gt;&#13;
&lt;peripheralInstance derived_from="CCU2" id="CCU2" location="0x40052000"/&gt;&#13;
&lt;peripheralInstance derived_from="RGU" id="RGU" location="0x40053000"/&gt;&#13;
&lt;peripheralInstance derived_from="WWDT" id="WWDT" location="0x40080000"/&gt;&#13;
&lt;peripheralInstance derived_from="USART0" id="USART0" location="0x40081000"/&gt;&#13;
&lt;peripheralInstance derived_from="USART2" id="USART2" location="0x400c1000"/&gt;&#13;
&lt;peripheralInstance derived_from="USART3" id="USART3" location="0x400c2000"/&gt;&#13;
&lt;peripheralInstance derived_from="UART1" id="UART1" location="0x40082000"/&gt;&#13;
&lt;peripheralInstance derived_from="SSP0" id="SSP0" location="0x40083000"/&gt;&#13;
&lt;peripheralInstance derived_from="SSP1" id="SSP1" location="0x400c5000"/&gt;&#13;
&lt;peripheralInstance derived_from="TIMER0" id="TIMER0" location="0x40084000"/&gt;&#13;
&lt;peripheralInstance derived_from="TIMER1" id="TIMER1" location="0x40085000"/&gt;&#13;
&lt;peripheralInstance derived_from="TIMER2" id="TIMER2" location="0x400c3000"/&gt;&#13;
&lt;peripheralInstance derived_from="TIMER3" id="TIMER3" location="0x400c4000"/&gt;&#13;
&lt;peripheralInstance derived_from="SCU" id="SCU" location="0x40086000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-PIN-INT" id="GPIO-PIN-INT" location="0x40087000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-GROUP-INT0" id="GPIO-GROUP-INT0" location="0x40088000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-GROUP-INT1" id="GPIO-GROUP-INT1" location="0x40089000"/&gt;&#13;
&lt;peripheralInstance derived_from="MCPWM" id="MCPWM" location="0x400a0000"/&gt;&#13;
&lt;peripheralInstance derived_from="I2C0" id="I2C0" location="0x400a1000"/&gt;&#13;
&lt;peripheralInstance derived_from="I2C1" id="I2C1" location="0x400e0000"/&gt;&#13;
&lt;peripheralInstance derived_from="I2S0" id="I2S0" location="0x400a2000"/&gt;&#13;
&lt;peripheralInstance derived_from="I2S1" id="I2S1" location="0x400a3000"/&gt;&#13;
&lt;peripheralInstance derived_from="C-CAN1" id="C-CAN1" location="0x400a4000"/&gt;&#13;
&lt;peripheralInstance derived_from="RITIMER" id="RITIMER" location="0x400c0000"/&gt;&#13;
&lt;peripheralInstance derived_from="QEI" id="QEI" location="0x400c6000"/&gt;&#13;
&lt;peripheralInstance derived_from="GIMA" id="GIMA" location="0x400c7000"/&gt;&#13;
&lt;peripheralInstance derived_from="DAC" id="DAC" location="0x400e1000"/&gt;&#13;
&lt;peripheralInstance derived_from="C-CAN0" id="C-CAN0" location="0x400e2000"/&gt;&#13;
&lt;peripheralInstance derived_from="ADC0" id="ADC0" location="0x400e3000"/&gt;&#13;
&lt;peripheralInstance derived_from="ADC1" id="ADC1" location="0x400e4000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-PORT" id="GPIO-PORT" location="0x400f4000"/&gt;&#13;
&lt;peripheralInstance derived_from="SPI" id="SPI" location="0x40100000"/&gt;&#13;
&lt;peripheralInstance derived_from="SGPIO" id="SGPIO" location="0x40101000"/&gt;&#13;
&lt;/chip&gt;&#13;
&lt;processor&gt;&lt;name gcc_name="cortex-m3"&gt;Cortex-M3&lt;/name&gt;&#13;
&lt;processor&gt;&lt;name gcc_name="cortex-m4"&gt;Cortex-M4&lt;/name&gt;&#13;
&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
&lt;/processor&gt;&#13;
&lt;link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
&lt;link href="nxp_lpc43xx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
&lt;/info&gt;&#13;
&lt;/infoList&gt;&#13;
&lt;/TargetConfig&gt;</projectStorage>

4
demos/host/src/cdc_serial_app.c
View File

@@ -51,8 +51,8 @@ OSAL_SEM_DEF(serial_semaphore);
static osal_semaphore_handle_t sem_hdl;
static uint8_t serial_in_buffer[32] TUSB_CFG_ATTR_USBRAM;
static uint8_t serial_out_buffer[32] TUSB_CFG_ATTR_USBRAM;
TUSB_CFG_ATTR_USBRAM static uint8_t serial_in_buffer[32];
TUSB_CFG_ATTR_USBRAM static uint8_t serial_out_buffer[32];
static uint8_t received_bytes; // set by transfer complete callback

2
demos/host/src/cli.c
View File

@@ -135,8 +135,8 @@ static cli_cmdfunc_t cli_command_tbl[] =
//--------------------------------------------------------------------+
// INTERNAL OBJECT & FUNCTION DECLARATION
//--------------------------------------------------------------------+
TUSB_CFG_ATTR_USBRAM uint8_t fileread_buffer[CLI_FILE_READ_BUFFER];
static char cli_buffer[CLI_MAX_BUFFER];
uint8_t fileread_buffer[CLI_FILE_READ_BUFFER] TUSB_CFG_ATTR_USBRAM;
static char volume_label[20];
static inline void drive_number2letter(char * p_path) ATTR_ALWAYS_INLINE;

2
demos/host/src/keyboard_app.c
View File

@@ -56,7 +56,7 @@ OSAL_TASK_DEF(keyboard_app_task, 128, KEYBOARD_APP_TASK_PRIO);
OSAL_QUEUE_DEF(queue_kbd_def, QUEUE_KEYBOARD_REPORT_DEPTH, hid_keyboard_report_t);
static osal_queue_handle_t queue_kbd_hdl;
static hid_keyboard_report_t usb_keyboard_report TUSB_CFG_ATTR_USBRAM;
TUSB_CFG_ATTR_USBRAM static hid_keyboard_report_t usb_keyboard_report;
static inline uint8_t keycode_to_ascii(uint8_t modifier, uint8_t keycode) ATTR_CONST ATTR_ALWAYS_INLINE;
static inline void process_kbd_report(hid_keyboard_report_t const * report);

2
demos/host/src/mouse_app.c
View File

@@ -56,7 +56,7 @@ OSAL_TASK_DEF(mouse_app_task, 128, MOUSE_APP_TASK_PRIO);
OSAL_QUEUE_DEF(queue_mouse_def, QUEUE_MOUSE_REPORT_DEPTH, hid_mouse_report_t);
static osal_queue_handle_t queue_mouse_hdl;
static hid_mouse_report_t usb_mouse_report TUSB_CFG_ATTR_USBRAM;
TUSB_CFG_ATTR_USBRAM static hid_mouse_report_t usb_mouse_report;
static inline void process_mouse_report(hid_mouse_report_t const * p_report);

2
demos/host/src/msc_app.c
View File

@@ -57,7 +57,7 @@
//--------------------------------------------------------------------+
OSAL_TASK_DEF(msc_app_task, 512, MSC_APP_TASK_PRIO);
static FATFS fatfs[TUSB_CFG_HOST_DEVICE_MAX] TUSB_CFG_ATTR_USBRAM;
TUSB_CFG_ATTR_USBRAM static FATFS fatfs[TUSB_CFG_HOST_DEVICE_MAX];
//--------------------------------------------------------------------+
// tinyusb callback (ISR context)

2
demos/host/src/tusb_config.h
View File

@@ -115,7 +115,7 @@
#elif defined __ICCARM__ // compiled with IAR
#define TUSB_CFG_ATTR_USBRAM @ ".ahb_sram1"
#define TUSB_CFG_ATTR_USBRAM _Pragma("location=\".ahb_sram1\"")
#else

8
tinyusb/class/cdc_device.c
View File

@@ -50,8 +50,8 @@
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
ATTR_USB_MIN_ALIGNMENT
static cdc_line_coding_t cdcd_line_coding[CONTROLLER_DEVICE_NUMBER] TUSB_CFG_ATTR_USBRAM;
TUSB_CFG_ATTR_USBRAM ATTR_USB_MIN_ALIGNMENT
static cdc_line_coding_t cdcd_line_coding[CONTROLLER_DEVICE_NUMBER];
typedef struct {
uint8_t interface_number;
@@ -191,12 +191,12 @@ tusb_error_t cdcd_control_request_subtask(uint8_t coreid, tusb_control_request_t
{
case CDC_REQUEST_GET_LINE_CODING:
dcd_pipe_control_xfer(coreid, p_request->bmRequestType_bit.direction,
&cdcd_line_coding[coreid], min16_of(sizeof(cdc_line_coding_t), p_request->wLength), false );
(uint8_t*) &cdcd_line_coding[coreid], min16_of(sizeof(cdc_line_coding_t), p_request->wLength), false );
break;
case CDC_REQUEST_SET_LINE_CODING:
dcd_pipe_control_xfer(coreid, p_request->bmRequestType_bit.direction,
&cdcd_line_coding[coreid], min16_of(sizeof(cdc_line_coding_t), p_request->wLength), false );
(uint8_t*) &cdcd_line_coding[coreid], min16_of(sizeof(cdc_line_coding_t), p_request->wLength), false );
// TODO notify application on xfer completea
break;

4
tinyusb/class/cdc_rndis_host.c
View File

@@ -54,8 +54,8 @@
//--------------------------------------------------------------------+
#define RNDIS_MSG_PAYLOAD_MAX (1024*4)
static uint8_t msg_notification[TUSB_CFG_HOST_DEVICE_MAX][8] TUSB_CFG_ATTR_USBRAM;
ATTR_ALIGNED(4) static uint8_t msg_payload[RNDIS_MSG_PAYLOAD_MAX] TUSB_CFG_ATTR_USBRAM;
TUSB_CFG_ATTR_USBRAM static uint8_t msg_notification[TUSB_CFG_HOST_DEVICE_MAX][8];
TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(4) static uint8_t msg_payload[RNDIS_MSG_PAYLOAD_MAX];
STATIC_VAR rndish_data_t rndish_data[TUSB_CFG_HOST_DEVICE_MAX];

17
tinyusb/class/hid_device.c
View File

@@ -108,14 +108,15 @@ static hidd_class_driver_t const hidd_class_driver[HIDD_NUMBER_OF_SUBCLASS] =
};
#if TUSB_CFG_DEVICE_HID_KEYBOARD || TUSB_CFG_DEVICE_HID_MOUSE
ATTR_USB_MIN_ALIGNMENT uint8_t m_control_data[ MAX_OF(sizeof(hid_keyboard_report_t), sizeof(hid_mouse_report_t)) ] TUSB_CFG_ATTR_USBRAM;
TUSB_CFG_ATTR_USBRAM ATTR_USB_MIN_ALIGNMENT
uint8_t m_control_data[ MAX_OF(sizeof(hid_keyboard_report_t), sizeof(hid_mouse_report_t)) ];
#endif
//--------------------------------------------------------------------+
// KEYBOARD APPLICATION API
//--------------------------------------------------------------------+
#if TUSB_CFG_DEVICE_HID_KEYBOARD
STATIC_VAR TUSB_CFG_ATTR_USBRAM hidd_interface_t keyboardd_data;
TUSB_CFG_ATTR_USBRAM STATIC_VAR hidd_interface_t keyboardd_data;
bool tusbd_hid_keyboard_is_busy(uint8_t coreid)
{
@@ -128,7 +129,7 @@ tusb_error_t tusbd_hid_keyboard_send(uint8_t coreid, hid_keyboard_report_t const
hidd_interface_t * p_kbd = &keyboardd_data; // TODO &keyboardd_data[coreid];
ASSERT_STATUS( dcd_pipe_xfer(p_kbd->ept_handle, p_report, sizeof(hid_keyboard_report_t), true) ) ;
ASSERT_STATUS( dcd_pipe_xfer(p_kbd->ept_handle, (void*) p_report, sizeof(hid_keyboard_report_t), true) ) ;
return TUSB_ERROR_NONE;
}
@@ -138,7 +139,7 @@ tusb_error_t tusbd_hid_keyboard_send(uint8_t coreid, hid_keyboard_report_t const
// MOUSE APPLICATION API
//--------------------------------------------------------------------+
#if TUSB_CFG_DEVICE_HID_MOUSE
STATIC_VAR TUSB_CFG_ATTR_USBRAM hidd_interface_t moused_data;
TUSB_CFG_ATTR_USBRAM STATIC_VAR hidd_interface_t moused_data;
bool tusbd_hid_mouse_is_busy(uint8_t coreid)
{
@@ -151,7 +152,7 @@ tusb_error_t tusbd_hid_mouse_send(uint8_t coreid, hid_mouse_report_t const *p_re
hidd_interface_t * p_mouse = &moused_data; // TODO &keyboardd_data[coreid];
ASSERT_STATUS( dcd_pipe_xfer(p_mouse->ept_handle, p_report, sizeof(hid_mouse_report_t), true) ) ;
ASSERT_STATUS( dcd_pipe_xfer(p_mouse->ept_handle, (void*) p_report, sizeof(hid_mouse_report_t), true) ) ;
return TUSB_ERROR_NONE;
}
@@ -217,7 +218,7 @@ tusb_error_t hidd_control_request_subtask(uint8_t coreid, tusb_control_request_t
ASSERT ( p_request->bRequest == TUSB_REQUEST_GET_DESCRIPTOR && desc_type == HID_DESC_TYPE_REPORT,
TUSB_ERROR_DCD_CONTROL_REQUEST_NOT_SUPPORT);
dcd_pipe_control_xfer(coreid, TUSB_DIR_DEV_TO_HOST, p_driver->p_report_desc, p_hid->report_length, false);
dcd_pipe_control_xfer(coreid, TUSB_DIR_DEV_TO_HOST, (uint8_t*) p_driver->p_report_desc, p_hid->report_length, false);
}
//------------- Class Specific Request -------------//
else if (p_request->bmRequestType_bit.type == TUSB_REQUEST_TYPE_CLASS)
@@ -241,13 +242,13 @@ tusb_error_t hidd_control_request_subtask(uint8_t coreid, tusb_control_request_t
// wValue = Report Type | Report ID
tusb_error_t error;
dcd_pipe_control_xfer(coreid, p_request->bmRequestType_bit.direction, &m_control_data, p_request->wLength, true);
dcd_pipe_control_xfer(coreid, p_request->bmRequestType_bit.direction, m_control_data, p_request->wLength, true);
osal_semaphore_wait(usbd_control_xfer_sem_hdl, OSAL_TIMEOUT_NORMAL, &error); // wait for control xfer complete
SUBTASK_ASSERT_STATUS(error);
p_driver->set_report_cb(coreid, (hid_request_report_type_t) u16_high_u8(p_request->wValue),
&m_control_data, p_request->wLength);
m_control_data, p_request->wLength);
}
else if (HID_REQUEST_CONTROL_SET_IDLE == p_request->bRequest)
{

2
tinyusb/class/hid_host.c
View File

@@ -180,7 +180,7 @@ void hidh_init(void)
}
#if 0
uint8_t report_descriptor[256] TUSB_CFG_ATTR_USBRAM;
TUSB_CFG_ATTR_USBRAM uint8_t report_descriptor[256];
#endif
tusb_error_t hidh_open_subtask(uint8_t dev_addr, tusb_descriptor_interface_t const *p_interface_desc, uint16_t *p_length)

8
tinyusb/class/msc_device.c
View File

@@ -62,7 +62,7 @@ typedef struct {
ATTR_USB_MIN_ALIGNMENT msc_cmd_status_wrapper_t csw;
}mscd_interface_t;
STATIC_VAR mscd_interface_t mscd_data TUSB_CFG_ATTR_USBRAM;
TUSB_CFG_ATTR_USBRAM STATIC_VAR mscd_interface_t mscd_data;
//--------------------------------------------------------------------+
// INTERNAL OBJECT & FUNCTION DECLARATION
//--------------------------------------------------------------------+
@@ -109,7 +109,7 @@ tusb_error_t mscd_open(uint8_t coreid, tusb_descriptor_interface_t const * p_int
(*p_length) += sizeof(tusb_descriptor_interface_t) + 2*sizeof(tusb_descriptor_endpoint_t);
//------------- Queue Endpoint OUT for Command Block Wrapper -------------//
ASSERT_STATUS( dcd_pipe_xfer(p_msc->edpt_out, &p_msc->cbw, sizeof(msc_cmd_block_wrapper_t), true) );
ASSERT_STATUS( dcd_pipe_xfer(p_msc->edpt_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cmd_block_wrapper_t), true) );
return TUSB_ERROR_NONE;
}
@@ -202,10 +202,10 @@ tusb_error_t mscd_xfer_cb(endpoint_handle_t edpt_hdl, tusb_event_t event, uint32
// Either bulk in & out can be stalled in the data phase, dcd must make sure these queued transfer will be resumed after host clear stall
if (!is_waiting_read10_write10)
{
ASSERT_STATUS( dcd_pipe_xfer( p_msc->edpt_in , p_csw, sizeof(msc_cmd_status_wrapper_t), false) );
ASSERT_STATUS( dcd_pipe_xfer( p_msc->edpt_in , (uint8_t*) p_csw, sizeof(msc_cmd_status_wrapper_t), false) );
//------------- Queue the next CBW -------------//
ASSERT_STATUS( dcd_pipe_xfer( p_msc->edpt_out, p_cbw, sizeof(msc_cmd_block_wrapper_t), true) );
ASSERT_STATUS( dcd_pipe_xfer( p_msc->edpt_out, (uint8_t*) p_cbw, sizeof(msc_cmd_block_wrapper_t), true) );
}
return TUSB_ERROR_NONE;

4
tinyusb/class/msc_host.c
View File

@@ -51,7 +51,7 @@
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
STATIC_VAR msch_interface_t msch_data[TUSB_CFG_HOST_DEVICE_MAX] TUSB_CFG_ATTR_USBRAM;
TUSB_CFG_ATTR_USBRAM STATIC_VAR msch_interface_t msch_data[TUSB_CFG_HOST_DEVICE_MAX];
//------------- Initalization Data -------------//
@@ -59,7 +59,7 @@ OSAL_SEM_DEF(msch_semaphore);
static osal_semaphore_handle_t msch_sem_hdl;
// buffer used to read scsi information when mounted, largest response data currently is inquiry
ATTR_ALIGNED(4) STATIC_VAR uint8_t msch_buffer[sizeof(scsi_inquiry_data_t)] TUSB_CFG_ATTR_USBRAM;
TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(4) STATIC_VAR uint8_t msch_buffer[sizeof(scsi_inquiry_data_t)];
//--------------------------------------------------------------------+
// INTERNAL OBJECT & FUNCTION DECLARATION

4
tinyusb/common/compiler/compiler.h
View File

@@ -49,6 +49,7 @@
#ifndef _TEST_
#define STATIC_ static
#define INLINE_ inline
#define ATTR_TEST_WEAK
#if TUSB_CFG_DEBUG == 3
#define ATTR_ALWAYS_INLINE // no inline for debug = 3
@@ -56,12 +57,13 @@
#else
#define STATIC_VAR static
#endif
#define ATTR_TEST_WEAK
#else
#define ATTR_ALWAYS_INLINE
#define STATIC_
#define STATIC_VAR
#define INLINE_
#endif
#if defined(__GNUC__)

12
tinyusb/common/compiler/compiler_iar.h
View File

@@ -57,17 +57,9 @@
#define ATTR_PACKED_STRUCT(x) __packed x
#define ATTR_PREPACKED __packed
#define ATTR_PACKED
//#define ATTR_SECTION(section) _Pragma((#section))
#define ATTR_ALIGNED(Bytes) ATTR_ALIGNED_##Bytes
#define ATTR_ALIGNED_4096 _Pragma("data_alignment=4096")
#define ATTR_ALIGNED_2048 _Pragma("data_alignment=2048")
#define ATTR_ALIGNED_256 _Pragma("data_alignment=256")
#define ATTR_ALIGNED_128 _Pragma("data_alignment=128")
#define ATTR_ALIGNED_64 _Pragma("data_alignment=64")
#define ATTR_ALIGNED_48 _Pragma("data_alignment=48")
#define ATTR_ALIGNED_32 _Pragma("data_alignment=32")
#define ATTR_ALIGNED_16 _Pragma("data_alignment=16")
#define ATTR_ALIGNED_4 _Pragma("data_alignment=4")
#define ATTR_ALIGNED(bytes) _Pragma(XSTRING_(data_alignment=##bytes))
#ifndef ATTR_ALWAYS_INLINE
/// Generally, functions are not inlined unless optimization is specified. For functions declared inline, this attribute inlines the function even if no optimization level is specified

5
tinyusb/common/fifo.h
View File

@@ -55,23 +55,24 @@
*/
typedef struct
{
uint8_t* const buffer ; ///< buffer pointer
uint16_t const depth ; ///< max items
uint16_t const item_size ; ///< size of each item
volatile uint16_t count ; ///< number of items in queue
volatile uint16_t wr_idx ; ///< write pointer
volatile uint16_t rd_idx ; ///< read pointer
bool overwritable ;
uint8_t buffer[] ; ///< buffer pointer
// IRQn_Type irq;
} fifo_t;
#define FIFO_DEF(name, ff_depth, type, is_overwritable) /*, irq_mutex)*/ \
uint8_t name##_buffer[ff_depth*sizeof(type)];\
fifo_t name = {\
.buffer = name##_buffer,\
.depth = ff_depth,\
.item_size = sizeof(type),\
.overwritable = is_overwritable,\
/*.irq = irq_mutex*/\
.buffer = { [ff_depth*sizeof(type) - 1] = 0 },\
}
bool fifo_write(fifo_t* f, void const * p_data);

14
tinyusb/device/dcd.h
View File

@@ -75,18 +75,18 @@ tusb_error_t dcd_init(void) ATTR_WARN_UNUSED_RESULT;
void dcd_isr(uint8_t coreid);
//------------- Controller API -------------//
void dcd_controller_connect(uint8_t coreid);
void dcd_controller_disconnect(uint8_t coreid);
void dcd_controller_set_address(uint8_t coreid, uint8_t dev_addr);
void dcd_controller_set_configuration(uint8_t coreid);
void dcd_controller_connect (uint8_t coreid);
void dcd_controller_disconnect (uint8_t coreid);
void dcd_controller_set_address (uint8_t coreid, uint8_t dev_addr);
void dcd_controller_set_configuration (uint8_t coreid);
//------------- PIPE API -------------//
tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, void * p_buffer, uint16_t length, bool int_on_complete);
tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, uint8_t * p_buffer, uint16_t length, bool int_on_complete);
void dcd_pipe_control_stall(uint8_t coreid);
endpoint_handle_t dcd_pipe_open(uint8_t coreid, tusb_descriptor_endpoint_t const * p_endpoint_desc, uint8_t class_code) ATTR_WARN_UNUSED_RESULT;
tusb_error_t dcd_pipe_queue_xfer(endpoint_handle_t edpt_hdl, void * buffer, uint16_t total_bytes) ATTR_WARN_UNUSED_RESULT; // only queue, not transferring yet
tusb_error_t dcd_pipe_xfer(endpoint_handle_t edpt_hdl, void * buffer, uint16_t total_bytes, bool int_on_complete) ATTR_WARN_UNUSED_RESULT;
tusb_error_t dcd_pipe_queue_xfer(endpoint_handle_t edpt_hdl, uint8_t * buffer, uint16_t total_bytes) ATTR_WARN_UNUSED_RESULT; // only queue, not transferring yet
tusb_error_t dcd_pipe_xfer(endpoint_handle_t edpt_hdl, uint8_t * buffer, uint16_t total_bytes, bool int_on_complete) ATTR_WARN_UNUSED_RESULT;
tusb_error_t dcd_pipe_stall(endpoint_handle_t edpt_hdl) ATTR_WARN_UNUSED_RESULT;
bool dcd_pipe_is_busy(endpoint_handle_t edpt_hdl) ATTR_WARN_UNUSED_RESULT ;

8
tinyusb/device/dcd_lpc175x_6x.c
View File

@@ -68,7 +68,7 @@ typedef struct {
}dcd_data_t;
STATIC_ dcd_data_t dcd_data TUSB_CFG_ATTR_USBRAM;
TUSB_CFG_ATTR_USBRAM STATIC_ dcd_data_t dcd_data;
//--------------------------------------------------------------------+
// INTERNAL OBJECT & FUNCTION DECLARATION
@@ -372,7 +372,7 @@ void dcd_pipe_control_stall(uint8_t coreid)
sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS+0, 1, SIE_SET_ENDPOINT_STALLED_MASK | SIE_SET_ENDPOINT_CONDITION_STALLED_MASK);
}
tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, void * p_buffer, uint16_t length, bool int_on_complete)
tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, uint8_t * p_buffer, uint16_t length, bool int_on_complete)
{
(void) coreid;
@@ -473,7 +473,7 @@ void dd_xfer_init(dcd_dma_descriptor_t* p_dd, void* buffer, uint16_t total_bytes
p_dd->present_count = 0;
}
tusb_error_t dcd_pipe_queue_xfer(endpoint_handle_t edpt_hdl, void * buffer, uint16_t total_bytes)
tusb_error_t dcd_pipe_queue_xfer(endpoint_handle_t edpt_hdl, uint8_t * buffer, uint16_t total_bytes)
{ // NOTE for sure the qhd has no dds
dcd_dma_descriptor_t* const p_fixed_dd = &dcd_data.dd[edpt_hdl.index][0]; // always queue with the fixed DD
@@ -484,7 +484,7 @@ tusb_error_t dcd_pipe_queue_xfer(endpoint_handle_t edpt_hdl, void * buffer, uint
return TUSB_ERROR_NONE;
}
tusb_error_t dcd_pipe_xfer(endpoint_handle_t edpt_hdl, void * buffer, uint16_t total_bytes, bool int_on_complete)
tusb_error_t dcd_pipe_xfer(endpoint_handle_t edpt_hdl, uint8_t* buffer, uint16_t total_bytes, bool int_on_complete)
{
dcd_dma_descriptor_t* const p_first_dd = &dcd_data.dd[edpt_hdl.index][0];

4
tinyusb/device/dcd_lpc43xx.c
View File

@@ -168,11 +168,11 @@ typedef struct {
}dcd_data_t;
#if (TUSB_CFG_CONTROLLER_0_MODE & TUSB_MODE_DEVICE)
ATTR_ALIGNED(2048) dcd_data_t dcd_data0 TUSB_CFG_ATTR_USBRAM;
TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(2048) dcd_data_t dcd_data0;
#endif
#if (TUSB_CFG_CONTROLLER_1_MODE & TUSB_MODE_DEVICE)
ATTR_ALIGNED(2048) dcd_data_t dcd_data1 TUSB_CFG_ATTR_USBRAM;
TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(2048) dcd_data_t dcd_data1;
#endif
static LPC_USB0_Type * const LPC_USB[2] = { LPC_USB0, ((LPC_USB0_Type*) LPC_USB1_BASE) };

2
tinyusb/device/dcd_lpc_11uxx_13uxx.c
View File

@@ -133,7 +133,7 @@ typedef struct {
//--------------------------------------------------------------------+
// INTERNAL OBJECT & FUNCTION DECLARATION
//--------------------------------------------------------------------+
ATTR_ALIGNED(256) static dcd_11u_13u_data_t dcd_data TUSB_CFG_ATTR_USBRAM;
TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(256) static dcd_11u_13u_data_t dcd_data;
static inline uint16_t addr_offset(void const * p_buffer) ATTR_CONST ATTR_ALWAYS_INLINE;
static inline uint16_t addr_offset(void const * p_buffer)

6
tinyusb/host/ehci/ehci.c
View File

@@ -57,12 +57,12 @@
//--------------------------------------------------------------------+
// INTERNAL OBJECT & FUNCTION DECLARATION
//--------------------------------------------------------------------+
STATIC_VAR ehci_data_t ehci_data TUSB_CFG_ATTR_USBRAM;
TUSB_CFG_ATTR_USBRAM STATIC_VAR ehci_data_t ehci_data;
#if EHCI_PERIODIC_LIST
#if (TUSB_CFG_CONTROLLER_0_MODE & TUSB_MODE_HOST)
ATTR_ALIGNED(4096) STATIC_VAR ehci_link_t period_frame_list0[EHCI_FRAMELIST_SIZE] TUSB_CFG_ATTR_USBRAM;
TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(4096) STATIC_VAR ehci_link_t period_frame_list0[EHCI_FRAMELIST_SIZE];
#ifndef __ICCARM__ // IAR cannot able to determine the alignment with datalignment pragma
STATIC_ASSERT( ALIGN_OF(period_frame_list0) == 4096, "Period Framelist must be 4k alginment"); // validation
@@ -70,7 +70,7 @@ STATIC_VAR ehci_data_t ehci_data TUSB_CFG_ATTR_USBRAM;
#endif
#if (TUSB_CFG_CONTROLLER_1_MODE & TUSB_MODE_HOST)
STATIC_VAR ehci_link_t period_frame_list1[EHCI_FRAMELIST_SIZE] ATTR_ALIGNED(4096) TUSB_CFG_ATTR_USBRAM;
TUSB_CFG_ATTR_USBRAM STATIC_VAR ehci_link_t period_frame_list1[EHCI_FRAMELIST_SIZE] ATTR_ALIGNED(4096);
#ifndef __ICCARM__ // IAR cannot able to determine the alignment with datalignment pragma
STATIC_ASSERT( ALIGN_OF(period_frame_list1) == 4096, "Period Framelist must be 4k alginment"); // validation

4
tinyusb/host/hub.c
View File

@@ -58,8 +58,8 @@ typedef struct {
uint8_t status_change; // data from status change interrupt endpoint
}usbh_hub_t;
usbh_hub_t hub_data[TUSB_CFG_HOST_DEVICE_MAX] TUSB_CFG_ATTR_USBRAM;
uint8_t hub_enum_buffer[sizeof(descriptor_hub_desc_t)] TUSB_CFG_ATTR_USBRAM;
TUSB_CFG_ATTR_USBRAM usbh_hub_t hub_data[TUSB_CFG_HOST_DEVICE_MAX];
TUSB_CFG_ATTR_USBRAM uint8_t hub_enum_buffer[sizeof(descriptor_hub_desc_t)];
//OSAL_SEM_DEF(hub_enum_semaphore);
//static osal_semaphore_handle_t hub_enum_sem_hdl;

2
tinyusb/host/ohci/ohci.c
View File

@@ -135,7 +135,7 @@ enum {
//--------------------------------------------------------------------+
// INTERNAL OBJECT & FUNCTION DECLARATION
//--------------------------------------------------------------------+
STATIC_VAR ohci_data_t ohci_data TUSB_CFG_ATTR_USBRAM;
TUSB_CFG_ATTR_USBRAM STATIC_VAR ohci_data_t ohci_data;
static ohci_ed_t * const p_ed_head[] =
{

4
tinyusb/host/usbh.c
View File

@@ -106,14 +106,14 @@ static host_class_driver_t const usbh_class_drivers[TUSB_CLASS_MAPPED_INDEX_END]
//--------------------------------------------------------------------+
// INTERNAL OBJECT & FUNCTION DECLARATION
//--------------------------------------------------------------------+
usbh_device_info_t usbh_devices[TUSB_CFG_HOST_DEVICE_MAX+1] TUSB_CFG_ATTR_USBRAM; // including zero-address
TUSB_CFG_ATTR_USBRAM usbh_device_info_t usbh_devices[TUSB_CFG_HOST_DEVICE_MAX+1]; // including zero-address
//------------- Enumeration Task Data -------------//
OSAL_TASK_DEF(usbh_enumeration_task, 200, TUSB_CFG_OS_TASK_PRIO);
OSAL_QUEUE_DEF(enum_queue_def, ENUM_QUEUE_DEPTH, uint32_t);
static osal_queue_handle_t enum_queue_hdl;
ATTR_ALIGNED(4) STATIC_VAR uint8_t enum_data_buffer[TUSB_CFG_HOST_ENUM_BUFFER_SIZE] TUSB_CFG_ATTR_USBRAM;
TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(4) STATIC_VAR uint8_t enum_data_buffer[TUSB_CFG_HOST_ENUM_BUFFER_SIZE];
//------------- Reporter Task Data -------------//