able to get usbpd irq handler
- handle cc1, cc2 voltage changes - get order set, rx message end interrupt - add segger rtt support for cmake
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@@ -58,7 +58,7 @@
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// RCC Clock
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//--------------------------------------------------------------------+
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// CPU Frequency (Core Clock) is 170MHz
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// CPU Frequency (Core Clock) is 150MHz
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static inline void board_clock_init(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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@@ -68,16 +68,16 @@ static inline void board_clock_init(void)
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HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
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/* Activate PLL with HSI as source */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
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RCC_OscInitStruct.PLL.PLLN = 85;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV10;
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RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
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RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
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RCC_OscInitStruct.PLL.PLLN = 75;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4;
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RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
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HAL_RCC_OscConfig(&RCC_OscInitStruct);
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// Initializes the CPU, AHB and APB buses clocks
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@@ -87,7 +87,7 @@ static inline void board_clock_init(void)
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8);
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HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
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//------------- HSI48 and CRS for USB -------------//
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RCC_OscInitTypeDef osc_hsi48 = {0};
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