get hpri triggered
This commit is contained in:
@@ -486,8 +486,8 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
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// Enable required interrupts
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// Enable required interrupts
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dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM;
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dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM;
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// Configure TX FIFO empty level for interrupt. Default is complete empty
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// Enable global interrupt
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dwc2->gahbcfg |= GAHBCFG_TXFELVL;
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dwc2->gahbcfg |= GAHBCFG_GINT;
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dcd_connect(rhport);
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dcd_connect(rhport);
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return true;
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return true;
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@@ -44,14 +44,17 @@ static void reset_core(dwc2_regs_t* dwc2) {
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// reset core
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// reset core
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dwc2->grstctl |= GRSTCTL_CSRST;
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dwc2->grstctl |= GRSTCTL_CSRST;
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// wait for reset bit is cleared
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if ((dwc2->gsnpsid & DWC2_CORE_REV_MASK) < (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) {
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// TODO version 4.20a should wait for RESET DONE mask
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// prior v42.0 CSRST is self-clearing
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while (dwc2->grstctl & GRSTCTL_CSRST) {}
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while (dwc2->grstctl & GRSTCTL_CSRST) {}
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} else {
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// From v4.20a CSRST bit is write only, CSRT_DONE (w1c) is introduced for checking.
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// CSRST must also be explicitly cleared
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while (!(dwc2->grstctl & GRSTCTL_CSRST_DONE)) {}
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dwc2->grstctl = (dwc2->grstctl & ~GRSTCTL_CSRST) | GRSTCTL_CSRST_DONE;
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}
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// wait for AHB master IDLE
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while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) {} // wait for AHB master IDLE
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while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) {}
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// wait for device mode ?
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}
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}
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bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) {
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bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) {
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@@ -71,11 +74,14 @@ bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init
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return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED;
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return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED;
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}
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}
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static void phy_fs_init(dwc2_regs_t* dwc2) {
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static void phy_fs_init(dwc2_regs_t* dwc2, tusb_role_t role) {
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TU_LOG(DWC2_COMMON_DEBUG, "Fullspeed PHY init\r\n");
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TU_LOG(DWC2_COMMON_DEBUG, "Fullspeed PHY init\r\n");
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uint32_t gusbcfg = dwc2->gusbcfg;
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// Select FS PHY
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// Select FS PHY
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dwc2->gusbcfg |= GUSBCFG_PHYSEL;
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gusbcfg |= GUSBCFG_PHYSEL;
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dwc2->gusbcfg = gusbcfg;
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// MCU specific PHY init before reset
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// MCU specific PHY init before reset
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dwc2_phy_init(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
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dwc2_phy_init(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
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@@ -86,13 +92,33 @@ static void phy_fs_init(dwc2_regs_t* dwc2) {
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// USB turnaround time is critical for certification where long cables and 5-Hubs are used.
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// USB turnaround time is critical for certification where long cables and 5-Hubs are used.
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// So if you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical,
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// So if you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical,
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// these bits can be programmed to a larger value. Default is 5
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// these bits can be programmed to a larger value. Default is 5
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dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (5u << GUSBCFG_TRDT_Pos);
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gusbcfg &= ~GUSBCFG_TRDT_Msk;
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gusbcfg |= 5u << GUSBCFG_TRDT_Pos;
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dwc2->gusbcfg = gusbcfg;
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// FS/LS PHY Clock Select
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if (role == TUSB_ROLE_HOST) {
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uint32_t hcfg = dwc2->hcfg;
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hcfg |= HCFG_FSLS_ONLY;
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hcfg &= ~HCFG_FSLS_PHYCLK_SEL;
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if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI &&
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dwc2->ghwcfg2_bm.fs_phy_type == GHWCFG2_FSPHY_DEDICATED) {
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// dedicated FS PHY with 48 mhz
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hcfg |= HCFG_FSLS_PHYCLK_SEL_48MHZ;
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} else {
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// shared HS PHY running at full speed
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hcfg |= HCFG_FSLS_PHYCLK_SEL_30_60MHZ;
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}
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dwc2->hcfg = hcfg;
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}
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// MCU specific PHY update post reset
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// MCU specific PHY update post reset
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dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
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dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
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}
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}
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static void phy_hs_init(dwc2_regs_t* dwc2) {
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static void phy_hs_init(dwc2_regs_t* dwc2, tusb_role_t role) {
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(void) role;
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uint32_t gusbcfg = dwc2->gusbcfg;
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uint32_t gusbcfg = dwc2->gusbcfg;
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// De-select FS PHY
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// De-select FS PHY
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@@ -138,6 +164,10 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
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// Reset core after selecting PHY
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// Reset core after selecting PHY
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reset_core(dwc2);
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reset_core(dwc2);
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if (role == TUSB_ROLE_HOST) {
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dwc2->hcfg &= ~HCFG_FSLS_ONLY;
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}
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// Set turn-around, must after core reset otherwise it will be clear
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// Set turn-around, must after core reset otherwise it will be clear
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// - 9 if using 8-bit PHY interface
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// - 9 if using 8-bit PHY interface
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// - 5 if using 16-bit PHY interface
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// - 5 if using 16-bit PHY interface
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@@ -182,9 +212,9 @@ bool dwc2_core_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
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TU_ASSERT(check_dwc2(dwc2));
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TU_ASSERT(check_dwc2(dwc2));
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if (dwc2_core_is_highspeed(dwc2, rh_init)) {
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if (dwc2_core_is_highspeed(dwc2, rh_init)) {
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phy_hs_init(dwc2); // Highspeed
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phy_hs_init(dwc2, rh_init->role);
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} else {
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} else {
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phy_fs_init(dwc2); // core does not support highspeed or hs phy is not present
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phy_fs_init(dwc2, rh_init->role);
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}
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}
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/* Set HS/FS Timeout Calibration to 7 (max available value).
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/* Set HS/FS Timeout Calibration to 7 (max available value).
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@@ -211,9 +241,9 @@ bool dwc2_core_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
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int_mask = dwc2->gotgint;
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int_mask = dwc2->gotgint;
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dwc2->gotgint |= int_mask;
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dwc2->gotgint |= int_mask;
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dwc2->gintmsk = GINTMSK_OTGINT;
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dwc2->gintmsk = 0;
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if (dwc2_dma_enabled(dwc2, TUSB_ROLE_DEVICE)) {
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if (dwc2_dma_enabled(dwc2, rh_init->role)) {
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const uint16_t epinfo_base = dma_cal_epfifo_base(rhport);
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const uint16_t epinfo_base = dma_cal_epfifo_base(rhport);
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dwc2->gdfifocfg = (epinfo_base << GDFIFOCFG_EPINFOBASE_SHIFT) | epinfo_base;
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dwc2->gdfifocfg = (epinfo_base << GDFIFOCFG_EPINFOBASE_SHIFT) | epinfo_base;
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@@ -223,8 +253,8 @@ bool dwc2_core_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
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dwc2->gintmsk |= GINTMSK_RXFLVLM;
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dwc2->gintmsk |= GINTMSK_RXFLVLM;
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}
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}
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// Enable global interrupt
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// Configure TX FIFO empty level for interrupt. Default is complete empty
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dwc2->gahbcfg |= GAHBCFG_GINT;
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dwc2->gahbcfg |= GAHBCFG_TXFELVL;
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return true;
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return true;
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}
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}
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@@ -124,13 +124,19 @@ static const dwc2_controller_t _dwc2_controller[] = {
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// SystemCoreClock is already included by family header
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// SystemCoreClock is already included by family header
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// extern uint32_t SystemCoreClock;
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// extern uint32_t SystemCoreClock;
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TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) {
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TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) {
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NVIC_EnableIRQ((IRQn_Type) _dwc2_controller[rhport].irqnum);
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(void) role;
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const IRQn_Type irqn = (IRQn_Type) _dwc2_controller[rhport].irqnum;
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if (enabled) {
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NVIC_EnableIRQ(irqn);
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} else {
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NVIC_DisableIRQ(irqn);
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}
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}
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}
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TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) {
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#define dwc2_dcd_int_enable(_rhport) dwc2_int_set(_rhport, TUSB_ROLE_DEVICE, true)
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NVIC_DisableIRQ((IRQn_Type) _dwc2_controller[rhport].irqnum);
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#define dwc2_dcd_int_disable(_rhport) dwc2_int_set(_rhport, TUSB_ROLE_DEVICE, false)
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}
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TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
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TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
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// try to delay for 1 ms
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// try to delay for 1 ms
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@@ -566,14 +566,15 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size");
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#define GOTGCTL_OTGVER GOTGCTL_OTGVER_Msk // OTG version
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#define GOTGCTL_OTGVER GOTGCTL_OTGVER_Msk // OTG version
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/******************** Bit definition for HCFG register ********************/
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/******************** Bit definition for HCFG register ********************/
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#define HCFG_FSLSPCS_Pos (0U)
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#define HCFG_FSLS_PHYCLK_SEL_Pos (0U)
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#define HCFG_FSLSPCS_Msk (0x3UL << HCFG_FSLSPCS_Pos) // 0x00000003
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#define HCFG_FSLS_PHYCLK_SEL_Msk (0x3UL << HCFG_FSLS_PHYCLK_SEL_Pos) // 0x00000003
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#define HCFG_FSLSPCS HCFG_FSLSPCS_Msk // FS/LS PHY clock select
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#define HCFG_FSLS_PHYCLK_SEL HCFG_FSLS_PHYCLK_SEL_Msk // FS/LS PHY clock select
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#define HCFG_FSLSPCS_0 (0x1UL << HCFG_FSLSPCS_Pos) // 0x00000001
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#define HCFG_FSLS_PHYCLK_SEL_30_60MHZ (0x0UL << HCFG_FSLS_PHYCLK_SEL_Pos) // 0x00000000
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#define HCFG_FSLSPCS_1 (0x2UL << HCFG_FSLSPCS_Pos) // 0x00000002
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#define HCFG_FSLS_PHYCLK_SEL_48MHZ (0x1UL << HCFG_FSLS_PHYCLK_SEL_Pos) // 0x00000001
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#define HCFG_FSLSS_Pos (2U)
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#define HCFG_FSLSS_Msk (0x1UL << HCFG_FSLSS_Pos) // 0x00000004
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#define HCFG_FSLS_ONLY_Pos (2U)
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#define HCFG_FSLSS HCFG_FSLSS_Msk // FS- and LS-only support
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#define HCFG_FSLS_ONLY_Msk (0x1UL << HCFG_FSLS_ONLY_Pos) // 0x00000004
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#define HCFG_FSLS_ONLY HCFG_FSLS_ONLY_Msk // FS- and LS-only support
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/******************** Bit definition for PCGCR register ********************/
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/******************** Bit definition for PCGCR register ********************/
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#define PCGCR_STPPCLK_Pos (0U)
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#define PCGCR_STPPCLK_Pos (0U)
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@@ -828,8 +829,8 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size");
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#define GRSTCTL_TXFNUM_2 (0x04UL << GRSTCTL_TXFNUM_Pos) // 0x00000100
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#define GRSTCTL_TXFNUM_2 (0x04UL << GRSTCTL_TXFNUM_Pos) // 0x00000100
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#define GRSTCTL_TXFNUM_3 (0x08UL << GRSTCTL_TXFNUM_Pos) // 0x00000200
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#define GRSTCTL_TXFNUM_3 (0x08UL << GRSTCTL_TXFNUM_Pos) // 0x00000200
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#define GRSTCTL_TXFNUM_4 (0x10UL << GRSTCTL_TXFNUM_Pos) // 0x00000400
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#define GRSTCTL_TXFNUM_4 (0x10UL << GRSTCTL_TXFNUM_Pos) // 0x00000400
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#define GRSTCTL_CSFTRST_DONE_Pos (29)
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#define GRSTCTL_CSRST_DONE_Pos (29)
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#define GRSTCTL_CSFTRST_DONE (1u << GRSTCTL_CSFTRST_DONE_Pos) // Reset Done, only available from v4.20a
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#define GRSTCTL_CSRST_DONE (1u << GRSTCTL_CSRST_DONE_Pos) // Reset Done, only available from v4.20a
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#define GRSTCTL_DMAREQ_Pos (30U)
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#define GRSTCTL_DMAREQ_Pos (30U)
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#define GRSTCTL_DMAREQ_Msk (0x1UL << GRSTCTL_DMAREQ_Pos) // 0x40000000
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#define GRSTCTL_DMAREQ_Msk (0x1UL << GRSTCTL_DMAREQ_Pos) // 0x40000000
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#define GRSTCTL_DMAREQ GRSTCTL_DMAREQ_Msk // DMA request signal
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#define GRSTCTL_DMAREQ GRSTCTL_DMAREQ_Msk // DMA request signal
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@@ -1475,9 +1476,9 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size");
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#define HPRT_CONN_STATUS_Pos (0U)
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#define HPRT_CONN_STATUS_Pos (0U)
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#define HPRT_CONN_STATUS_Msk (0x1UL << HPRT_CONN_STATUS_Pos) // 0x00000001
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#define HPRT_CONN_STATUS_Msk (0x1UL << HPRT_CONN_STATUS_Pos) // 0x00000001
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#define HPRT_CONN_STATUS HPRT_CONN_STATUS_Msk // Port connect status
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#define HPRT_CONN_STATUS HPRT_CONN_STATUS_Msk // Port connect status
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#define HPRT_CONN_DETECTEDT_Pos (1U)
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#define HPRT_CONN_DETECT_Pos (1U)
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#define HPRT_CONN_DETECTEDT_Msk (0x1UL << HPRT_CONN_DETECTEDT_Pos) // 0x00000002
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#define HPRT_CONN_DETECT_Msk (0x1UL << HPRT_CONN_DETECT_Pos) // 0x00000002
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#define HPRT_CONN_DETECTEDT HPRT_CONN_DETECTEDT_Msk // Port connect detected
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#define HPRT_CONN_DETECT HPRT_CONN_DETECT_Msk // Port connect detected
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#define HPRT_ENABLE_Pos (2U)
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#define HPRT_ENABLE_Pos (2U)
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#define HPRT_ENABLE_Msk (0x1UL << HPRT_ENABLE_Pos) // 0x00000004
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#define HPRT_ENABLE_Msk (0x1UL << HPRT_ENABLE_Pos) // 0x00000004
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#define HPRT_ENABLE HPRT_ENABLE_Msk // Port enable
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#define HPRT_ENABLE HPRT_ENABLE_Msk // Port enable
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@@ -34,6 +34,10 @@
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#include "host/hcd.h"
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#include "host/hcd.h"
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#include "dwc2_common.h"
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#include "dwc2_common.h"
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enum {
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HPRT_W1C_MASK = HPRT_CONN_DETECT | HPRT_ENABLE | HPRT_EN_CHANGE | HPRT_OVER_CURRENT_CHANGE
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};
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// Controller API
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// Controller API
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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@@ -54,40 +58,41 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
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// Core Initialization
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// Core Initialization
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TU_ASSERT(dwc2_core_init(rhport, rh_init));
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TU_ASSERT(dwc2_core_init(rhport, rh_init));
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//------------- 3.1 Host Initialization -------------//
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// max speed
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// if (dwc2_core_is_highspeed(dwc2, rh_init)) {
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// dwc2->hcfg &= ~HCFG_FSLS_ONLY;
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// } else {
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// dwc2->hcfg |= HCFG_FSLS_ONLY;
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// }
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// force host mode
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// force host mode
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dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FDMOD) | GUSBCFG_FHMOD;
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dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FDMOD) | GUSBCFG_FHMOD;
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//------------- 3.1 Host Initialization -------------//
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dwc2->hprt = HPRT_W1C_MASK; // clear all write-1-clear bits
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dwc2->hprt = HPRT_POWER; // port power on -> drive VBUS
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// Enable required interrupts
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// Enable required interrupts
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dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_PRTIM | GINTMSK_WUIM;
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dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_PRTIM | GINTMSK_WUIM;
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dwc2->gahbcfg |= GAHBCFG_GINT; // Enable global interrupt
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// max speed
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if (dwc2_core_is_highspeed(dwc2, rh_init)) {
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dwc2->hcfg &= ~HCFG_FSLSS;
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} else {
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dwc2->hcfg |= HCFG_FSLSS;
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}
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// port power on -> drive VBUS
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dwc2->hprt = HPRT_POWER;
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return true;
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return true;
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}
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}
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// Enable USB interrupt
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// Enable USB interrupt
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void hcd_int_enable (uint8_t rhport) {
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void hcd_int_enable (uint8_t rhport) {
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(void) rhport;
|
dwc2_int_set(rhport, TUSB_ROLE_HOST, true);
|
||||||
}
|
}
|
||||||
|
|
||||||
// Disable USB interrupt
|
// Disable USB interrupt
|
||||||
void hcd_int_disable(uint8_t rhport) {
|
void hcd_int_disable(uint8_t rhport) {
|
||||||
(void) rhport;
|
dwc2_int_set(rhport, TUSB_ROLE_HOST, false);
|
||||||
}
|
}
|
||||||
|
|
||||||
// Get frame number (1ms)
|
// Get frame number (1ms)
|
||||||
uint32_t hcd_frame_number(uint8_t rhport) {
|
uint32_t hcd_frame_number(uint8_t rhport) {
|
||||||
(void) rhport;
|
(void) rhport;
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -97,20 +102,23 @@ uint32_t hcd_frame_number(uint8_t rhport) {
|
|||||||
|
|
||||||
// Get the current connect status of roothub port
|
// Get the current connect status of roothub port
|
||||||
bool hcd_port_connect_status(uint8_t rhport) {
|
bool hcd_port_connect_status(uint8_t rhport) {
|
||||||
(void) rhport;
|
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||||
|
return dwc2->hprt & HPRT_CONN_STATUS;
|
||||||
return false;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
|
// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
|
||||||
// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
|
// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
|
||||||
void hcd_port_reset(uint8_t rhport) {
|
void hcd_port_reset(uint8_t rhport) {
|
||||||
(void) rhport;
|
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||||
|
dwc2->hprt = HPRT_RESET;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Complete bus reset sequence, may be required by some controllers
|
// Complete bus reset sequence, may be required by some controllers
|
||||||
void hcd_port_reset_end(uint8_t rhport) {
|
void hcd_port_reset_end(uint8_t rhport) {
|
||||||
(void) rhport;
|
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||||
|
uint32_t hprt = dwc2->hprt & ~HPRT_W1C_MASK; // skip w1c bits
|
||||||
|
hprt &= ~HPRT_RESET;
|
||||||
|
dwc2->hprt = hprt;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Get port link speed
|
// Get port link speed
|
||||||
@@ -182,6 +190,101 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
|
|||||||
// HCD Event Handler
|
// HCD Event Handler
|
||||||
//--------------------------------------------------------------------
|
//--------------------------------------------------------------------
|
||||||
|
|
||||||
|
#if 1
|
||||||
|
static void handle_rxflvl_irq(uint8_t rhport) {
|
||||||
|
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||||
|
volatile uint32_t const* rx_fifo = dwc2->fifo[0];
|
||||||
|
|
||||||
|
// Pop control word off FIFO
|
||||||
|
uint32_t const grxstsp = dwc2->grxstsp;
|
||||||
|
uint8_t const pktsts = (grxstsp & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos;
|
||||||
|
uint8_t const epnum = (grxstsp & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos;
|
||||||
|
uint16_t const bcnt = (grxstsp & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos;
|
||||||
|
// dwc2_epout_t* epout = &dwc2->epout[epnum];
|
||||||
|
|
||||||
|
(void) epnum; (void) bcnt; (void) rx_fifo;
|
||||||
|
|
||||||
|
TU_LOG1_INT(pktsts);
|
||||||
|
|
||||||
|
// switch (pktsts) {
|
||||||
|
// // Global OUT NAK: do nothing
|
||||||
|
// case GRXSTS_PKTSTS_GLOBALOUTNAK:
|
||||||
|
// break;
|
||||||
|
//
|
||||||
|
// case GRXSTS_PKTSTS_SETUPRX:
|
||||||
|
// // Setup packet received
|
||||||
|
// // We can receive up to three setup packets in succession, but only the last one is valid.
|
||||||
|
// _setup_packet[0] = (*rx_fifo);
|
||||||
|
// _setup_packet[1] = (*rx_fifo);
|
||||||
|
// break;
|
||||||
|
//
|
||||||
|
// case GRXSTS_PKTSTS_SETUPDONE:
|
||||||
|
// // Setup packet done:
|
||||||
|
// // After popping this out, dwc2 asserts a DOEPINT_SETUP interrupt which is handled by handle_epout_irq()
|
||||||
|
// epout->doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
|
||||||
|
// break;
|
||||||
|
//
|
||||||
|
// case GRXSTS_PKTSTS_OUTRX: {
|
||||||
|
// // Out packet received
|
||||||
|
// xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
|
||||||
|
//
|
||||||
|
// // Read packet off RxFIFO
|
||||||
|
// if (xfer->ff) {
|
||||||
|
// // Ring buffer
|
||||||
|
// tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, bcnt);
|
||||||
|
// } else {
|
||||||
|
// // Linear buffer
|
||||||
|
// dfifo_read_packet(rhport, xfer->buffer, bcnt);
|
||||||
|
//
|
||||||
|
// // Increment pointer to xfer data
|
||||||
|
// xfer->buffer += bcnt;
|
||||||
|
// }
|
||||||
|
//
|
||||||
|
// // Truncate transfer length in case of short packet
|
||||||
|
// if (bcnt < xfer->max_size) {
|
||||||
|
// xfer->total_len -= (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos;
|
||||||
|
// if (epnum == 0) {
|
||||||
|
// xfer->total_len -= ep0_pending[TUSB_DIR_OUT];
|
||||||
|
// ep0_pending[TUSB_DIR_OUT] = 0;
|
||||||
|
// }
|
||||||
|
// }
|
||||||
|
// break;
|
||||||
|
// }
|
||||||
|
//
|
||||||
|
// case GRXSTS_PKTSTS_OUTDONE:
|
||||||
|
// /* Out packet done
|
||||||
|
// After this entry is popped from the receive FIFO, dwc2 asserts a Transfer Completed interrupt on
|
||||||
|
// the specified OUT endpoint which will be handled by handle_epout_irq() */
|
||||||
|
// break;
|
||||||
|
//
|
||||||
|
// default:
|
||||||
|
// TU_BREAKPOINT();
|
||||||
|
// break;
|
||||||
|
// }
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Handle Host Port interrupt, possible source are:
|
||||||
|
- Connection Detection
|
||||||
|
- Enable Change
|
||||||
|
- Over Current Change
|
||||||
|
*/
|
||||||
|
TU_ATTR_ALWAYS_INLINE static inline void handle_hprt_irq(uint8_t rhport, bool in_isr) {
|
||||||
|
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||||
|
uint32_t hprt = dwc2->hprt;
|
||||||
|
|
||||||
|
if (hprt & HPRT_CONN_DETECT) {
|
||||||
|
// Port Connect Detect
|
||||||
|
dwc2->hprt = HPRT_CONN_DETECT; // clear
|
||||||
|
|
||||||
|
if (hprt & HPRT_CONN_STATUS) {
|
||||||
|
hcd_event_device_attach(rhport, in_isr);
|
||||||
|
} else {
|
||||||
|
hcd_event_device_remove(rhport, in_isr);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
/* Interrupt Hierarchy
|
/* Interrupt Hierarchy
|
||||||
|
|
||||||
HCINTn.XferCompl HCINTMSKn.XferComplMsk
|
HCINTn.XferCompl HCINTMSKn.XferComplMsk
|
||||||
@@ -201,7 +304,6 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
|
|||||||
IRQn
|
IRQn
|
||||||
*/
|
*/
|
||||||
void hcd_int_handler(uint8_t rhport, bool in_isr) {
|
void hcd_int_handler(uint8_t rhport, bool in_isr) {
|
||||||
(void) in_isr;
|
|
||||||
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||||
|
|
||||||
const uint32_t int_mask = dwc2->gintmsk;
|
const uint32_t int_mask = dwc2->gintmsk;
|
||||||
@@ -209,7 +311,21 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
|
|||||||
|
|
||||||
if (int_status & GINTSTS_HPRTINT) {
|
if (int_status & GINTSTS_HPRTINT) {
|
||||||
TU_LOG1_HEX(dwc2->hprt);
|
TU_LOG1_HEX(dwc2->hprt);
|
||||||
|
handle_hprt_irq(rhport, in_isr);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
// RxFIFO non-empty interrupt handling.
|
||||||
|
if (int_status & GINTSTS_RXFLVL) {
|
||||||
|
// RXFLVL bit is read-only
|
||||||
|
dwc2->gintmsk &= ~GINTMSK_RXFLVLM; // disable RXFLVL interrupt while reading
|
||||||
|
|
||||||
|
do {
|
||||||
|
handle_rxflvl_irq(rhport); // read all packets
|
||||||
|
} while(dwc2->gintsts & GINTSTS_RXFLVL);
|
||||||
|
|
||||||
|
dwc2->gintmsk |= GINTMSK_RXFLVLM;
|
||||||
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
@@ -77,6 +77,7 @@ bool tusb_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
|
|||||||
|
|
||||||
// new API with explicit rhport and role
|
// new API with explicit rhport and role
|
||||||
TU_ASSERT(rhport < TUP_USBIP_CONTROLLER_NUM && rh_init->role != TUSB_ROLE_INVALID);
|
TU_ASSERT(rhport < TUP_USBIP_CONTROLLER_NUM && rh_init->role != TUSB_ROLE_INVALID);
|
||||||
|
_rhport_role[rhport] = rh_init->role;
|
||||||
|
|
||||||
#if CFG_TUD_ENABLED
|
#if CFG_TUD_ENABLED
|
||||||
if (rh_init->role == TUSB_ROLE_DEVICE) {
|
if (rh_init->role == TUSB_ROLE_DEVICE) {
|
||||||
@@ -90,7 +91,6 @@ bool tusb_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
|
|||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
_rhport_role[rhport] = rh_init->role;
|
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
Reference in New Issue
Block a user