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rename and add both CFG_TUH_DWC2_SLAVE_ENABLE/CFG_TUH_DWC2_DMA_ENABLE better out dma handle

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hathach
2024-11-01 17:54:10 +07:00
parent 4c8ce9733a
commit b7ff10f59c
5 changed files with 302 additions and 283 deletions
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9
src/portable/synopsys/dwc2/dwc2_common.c
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@@ -194,7 +194,7 @@ bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, tusb_role_t role) {
* In addition, UTMI+/ULPI can be shared to run at fullspeed mode with 48Mhz
*
*/
bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) {
bool dwc2_core_init(uint8_t rhport, bool is_highspeed) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
// Check Synopsys ID register, failed if controller clock/power is not enabled
@@ -235,13 +235,6 @@ bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) {
dwc2->gintmsk = 0;
if (is_dma) {
// DMA seems to be only settable after a core reset, and not possible to switch on-the-fly
dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2;
} else {
dwc2->gintmsk |= GINTMSK_RXFLVLM;
}
return true;
}