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inital support for usb typec and pd example

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This commit is contained in:
hathach
2023-06-07 15:10:40 +07:00
parent 914e82b25d
commit b893f1d541
16 changed files with 651 additions and 145 deletions
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8
hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h
View File

@@ -58,7 +58,7 @@
// RCC Clock
//--------------------------------------------------------------------+
// CPU Frequency (Core Clock) is 150MHz
// CPU Frequency (Core Clock) is 170 MHz
static inline void board_clock_init(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
@@ -74,9 +74,9 @@ static inline void board_clock_init(void)
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
RCC_OscInitStruct.PLL.PLLN = 75;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4;
RCC_OscInitStruct.PLL.PLLN = 85;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV10;
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
HAL_RCC_OscConfig(&RCC_OscInitStruct);

133
hw/bsp/stm32g4/family.c
View File

@@ -30,132 +30,6 @@
#include "bsp/board.h"
#include "board.h"
//--------------------------------------------------------------------+
// USB PD
//--------------------------------------------------------------------+
void usbpd_init(uint8_t port_num, tusb_typec_port_type_t port_type) {
(void) port_num;
// Initialization phase: CFG1
UCPD1->CFG1 = (0x0d << UCPD_CFG1_HBITCLKDIV_Pos) | (0x10 << UCPD_CFG1_IFRGAP_Pos) | (0x07 << UCPD_CFG1_TRANSWIN_Pos) |
(0x01 << UCPD_CFG1_PSC_UCPDCLK_Pos) | (0x1f << UCPD_CFG1_RXORDSETEN_Pos) |
( 0 << UCPD_CFG1_TXDMAEN_Pos) | (0 << UCPD_CFG1_RXDMAEN_Pos);
UCPD1->CFG1 |= UCPD_CFG1_UCPDEN;
// General programming sequence (with UCPD configured then enabled)
if (port_type == TUSB_TYPEC_PORT_SNK) {
// Enable both CC Phy
UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | (0x03 << UCPD_CR_CCENABLE_Pos);
// Read Voltage State on CC1 & CC2 fore initial state
uint32_t vstate_cc[2];
vstate_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
vstate_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03;
TU_LOG1_INT(vstate_cc[0]);
TU_LOG1_INT(vstate_cc[1]);
// Enable CC1 & CC2 Interrupt
UCPD1->IMR = UCPD_IMR_TYPECEVT1IE | UCPD_IMR_TYPECEVT2IE;
}
// Enable interrupt
NVIC_EnableIRQ(UCPD1_IRQn);
}
uint8_t pd_rx_buf[262];
uint32_t pd_rx_count = 0;
void UCPD1_IRQHandler(void) {
uint32_t sr = UCPD1->SR;
sr &= UCPD1->IMR;
// TU_LOG1("UCPD1_IRQHandler: sr = 0x%08X\n", sr);
if (sr & (UCPD_SR_TYPECEVT1 | UCPD_SR_TYPECEVT2)) {
uint32_t vstate_cc[2];
vstate_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
vstate_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03;
TU_LOG1("VState CC1 = %u, CC2 = %u\n", vstate_cc[0], vstate_cc[1]);
uint32_t cr = UCPD1->CR;
// TODO only support SNK for now, required highest voltage for now
if ((sr & UCPD_SR_TYPECEVT1) && (vstate_cc[0] == 3)) {
TU_LOG1("Attach CC1\n");
cr &= ~UCPD_CR_PHYCCSEL;
cr |= UCPD_CR_PHYRXEN;
} else if ((sr & UCPD_SR_TYPECEVT2) && (vstate_cc[1] == 3)) {
TU_LOG1("Attach CC2\n");
cr |= UCPD_CR_PHYCCSEL;
cr |= UCPD_CR_PHYRXEN;
} else {
TU_LOG1("Detach\n");
cr &= ~UCPD_CR_PHYRXEN;
}
if (cr & UCPD_CR_PHYRXEN) {
// Enable Interrupt
UCPD1->IMR |= UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
UCPD_IMR_RXNEIE | UCPD_IMR_RXORDDETIE | UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE |
UCPD_IMR_RXMSGENDIE | UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE;
}
// Enable PD RX
UCPD1->CR = cr;
// ack
UCPD1->ICR = UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF;
}
//------------- Receive -------------//
if (sr & UCPD_SR_RXORDDET) {
// SOP: Start of Packet.
// uint8_t order_set = UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk;
// reset count when received SOP
pd_rx_count = 0;
// ack
UCPD1->ICR = UCPD_ICR_RXORDDETCF;
}
if (sr & UCPD_SR_RXNE) {
// TODO DMA later
do {
pd_rx_buf[pd_rx_count++] = UCPD1->RXDR;
} while (UCPD1->SR & UCPD_SR_RXNE);
}
if (sr & UCPD_SR_RXMSGEND) {
// End of message
uint32_t payload_size = UCPD1->RX_PAYSZ;
// ack
UCPD1->ICR = UCPD_ICR_RXMSGENDCF;
}
if (sr & UCPD_SR_RXOVR) {
TU_LOG1("RXOVR\n");
TU_LOG1_HEX(pd_rx_count);
// ack
UCPD1->ICR = UCPD_ICR_RXOVRCF;
}
// if (sr & UCPD_SR_RXNE) {
// uint8_t data = UCPD1->RXDR;
// pd_rx_buf[pd_rx_count++] = data;
// TU_LOG1_HEX(data);
// }
// else {
// TU_LOG_LOCATION();
// }
}
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
//--------------------------------------------------------------------+
@@ -174,6 +48,11 @@ void USBWakeUp_IRQHandler(void)
tud_int_handler(0);
}
// USB PD
void UCPD1_IRQHandler(void) {
tuc_int_handler(0);
}
//--------------------------------------------------------------------+
// MACRO TYPEDEF CONSTANT ENUM
//--------------------------------------------------------------------+
@@ -274,8 +153,6 @@ void board_init(void)
// Default CC1/CC2 is PB4/PB6
// PB4 ------> UCPD1_CC2
// PB6 ------> UCPD1_CC1
usbpd_init(0, TUSB_TYPEC_PORT_SNK);
#endif
}

1
hw/bsp/stm32g4/family.cmake
View File

@@ -90,6 +90,7 @@ function(family_configure_example TARGET)
target_sources(${TARGET} PUBLIC
# TinyUSB Port
${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
${TOP}/src/portable/st/typec/typec_stm32.c
# BSP
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c