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fix: allow FreeRTOS examples to compile

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This commit is contained in:
James Sandison
2025-06-04 13:52:35 +10:00
parent 5c4b2c75d2
commit b956d10487
3 changed files with 15 additions and 10 deletions
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5
hw/bsp/stm32n6/FreeRTOSConfig/FreeRTOSConfig.h
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@@ -44,10 +44,11 @@
// skip if included from IAR assembler // skip if included from IAR assembler
#ifndef __IASMARM__ #ifndef __IASMARM__
#include "stm32h7rsxx.h" #include "stm32n6xx.h"
#endif #endif
/* Cortex M23/M33 port configuration. */ /* Cortex M55 port configuration. */
#define configENABLE_MVE 0
#define configENABLE_MPU 0 #define configENABLE_MPU 0
#define configENABLE_FPU 1 #define configENABLE_FPU 1
#define configENABLE_TRUSTZONE 0 #define configENABLE_TRUSTZONE 0

10
hw/bsp/stm32n6/family.c
View File

@@ -145,7 +145,7 @@ void board_init(void) {
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); NVIC_SetPriority(USB1_OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
#endif #endif
@@ -173,7 +173,9 @@ void board_init(void) {
__HAL_RCC_USB1_OTG_HS_CLK_ENABLE(); __HAL_RCC_USB1_OTG_HS_CLK_ENABLE();
/* Required few clock cycles before accessing USB PHY Controller Registers */ /* Required few clock cycles before accessing USB PHY Controller Registers */
HAL_Delay(1); for (volatile uint32_t i = 0; i < 10; i++) {
__NOP(); // No Operation instruction to create a delay
}
USB1_HS_PHYC->USBPHYC_CR &= ~(0x7 << 0x4); USB1_HS_PHYC->USBPHYC_CR &= ~(0x7 << 0x4);
@@ -185,7 +187,9 @@ void board_init(void) {
__HAL_RCC_USB1_OTG_HS_PHY_RELEASE_RESET(); __HAL_RCC_USB1_OTG_HS_PHY_RELEASE_RESET();
/* Required few clock cycles before Releasing Reset */ /* Required few clock cycles before Releasing Reset */
HAL_Delay(1); for (volatile uint32_t i = 0; i < 10; i++) {
__NOP(); // No Operation instruction to create a delay
}
__HAL_RCC_USB1_OTG_HS_RELEASE_RESET(); __HAL_RCC_USB1_OTG_HS_RELEASE_RESET();

10
hw/bsp/stm32n6/stm32n6xx_hal_conf.h
View File

@@ -48,7 +48,7 @@
/*#define HAL_GFXMMU_MODULE_ENABLED */ /*#define HAL_GFXMMU_MODULE_ENABLED */
/*#define HAL_GFXTIM_MODULE_ENABLED */ /*#define HAL_GFXTIM_MODULE_ENABLED */
/*#define HAL_HASH_MODULE_ENABLED */ /*#define HAL_HASH_MODULE_ENABLED */
#define HAL_HCD_MODULE_ENABLED /*#define HAL_HCD_MODULE_ENABLED */
#define HAL_I2C_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED
/*#define HAL_I2S_MODULE_ENABLED */ /*#define HAL_I2S_MODULE_ENABLED */
/*#define HAL_I3C_MODULE_ENABLED */ /*#define HAL_I3C_MODULE_ENABLED */
@@ -63,11 +63,11 @@
/*#define HAL_MMC_MODULE_ENABLED */ /*#define HAL_MMC_MODULE_ENABLED */
/*#define HAL_NAND_MODULE_ENABLED */ /*#define HAL_NAND_MODULE_ENABLED */
/*#define HAL_NOR_MODULE_ENABLED */ /*#define HAL_NOR_MODULE_ENABLED */
#define HAL_PCD_MODULE_ENABLED /*#define HAL_PCD_MODULE_ENABLED */
/*#define HAL_PKA_MODULE_ENABLED */ /*#define HAL_PKA_MODULE_ENABLED */
/*#define HAL_PSSI_MODULE_ENABLED */ /*#define HAL_PSSI_MODULE_ENABLED */
/*#define HAL_RAMCFG_MODULE_ENABLED */ /*#define HAL_RAMCFG_MODULE_ENABLED */
#define HAL_RIF_MODULE_ENABLED /*#define HAL_RIF_MODULE_ENABLED */
/*#define HAL_RNG_MODULE_ENABLED */ /*#define HAL_RNG_MODULE_ENABLED */
/*#define HAL_RTC_MODULE_ENABLED */ /*#define HAL_RTC_MODULE_ENABLED */
/*#define HAL_SAI_MODULE_ENABLED */ /*#define HAL_SAI_MODULE_ENABLED */
@@ -79,9 +79,9 @@
/*#define HAL_SPDIFRX_MODULE_ENABLED */ /*#define HAL_SPDIFRX_MODULE_ENABLED */
/*#define HAL_SPI_MODULE_ENABLED */ /*#define HAL_SPI_MODULE_ENABLED */
/*#define HAL_SRAM_MODULE_ENABLED */ /*#define HAL_SRAM_MODULE_ENABLED */
#define HAL_TIM_MODULE_ENABLED /*#define HAL_TIM_MODULE_ENABLED */
#define HAL_UART_MODULE_ENABLED #define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED /*#define HAL_USART_MODULE_ENABLED */
/*#define HAL_WWDG_MODULE_ENABLED */ /*#define HAL_WWDG_MODULE_ENABLED */
/*#define HAL_XSPI_MODULE_ENABLED */ /*#define HAL_XSPI_MODULE_ENABLED */
/*#define HAL_CACHEAXI_MODULE_ENABLED */ /*#define HAL_CACHEAXI_MODULE_ENABLED */