Rework ci (#2631)

* add name field to usbd_class_driver_t
* ci: use set matrix py script
* add riscv32 and cmake support for ch32v307, fomu,  gd32vf103
* update build_cmake.py to take --family --board --toolchain
* separate hil test to its own workflow
* move esp32 board into separated hil json
* add make build to ci
* remov build_make.py
* build.py support esp32 board
* setup toolchain support esp-idf
* fix missing click
* merge family in matrix build to reduce jobs
* skip cifuzz since it still has issue with get_deps and click

examples/build_system/cmake/cpu/rv32i-ilp32.cmake

@@ -0,0 +1,19 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -march=rv32i
+    -mabi=ilp32
+    )
+  set(FREERTOS_PORT GCC_RISC_V CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -march=rv32i
+    -mabi=ilp32
+    )
+  set(FREERTOS_PORT GCC_RISC_V CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  message(FATAL_ERROR "IAR not supported")
+  set(FREERTOS_PORT IAR_RISC_V CACHE INTERNAL "")
+
+endif ()

examples/build_system/cmake/cpu/rv32imac-ilp32.cmake

@@ -0,0 +1,18 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -march=rv32imac
+    -mabi=ilp32
+    )
+  set(FREERTOS_PORT GCC_RISC_V CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -march=rv32imac
+    -mabi=ilp32
+    )
+  set(FREERTOS_PORT GCC_RISC_V CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  message(FATAL_ERROR "IAR not supported")
+  set(FREERTOS_PORT IAR_RISC_V CACHE INTERNAL "")
+endif ()

examples/build_system/cmake/toolchain/riscv_gcc.cmake

@@ -0,0 +1,21 @@
+if (NOT DEFINED CMAKE_C_COMPILER)
+  set(CMAKE_C_COMPILER "riscv-none-embed-gcc")
+endif ()
+
+if (NOT DEFINED CMAKE_CXX_COMPILER)
+  set(CMAKE_CXX_COMPILER "riscv-none-embed-g++")
+endif ()
+
+set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER})
+set(CMAKE_SIZE "riscv-none-embed-size" CACHE FILEPATH "")
+set(CMAKE_OBJCOPY "riscv-none-embed-objcopy" CACHE FILEPATH "")
+set(CMAKE_OBJDUMP "riscv-none-embed-objdump" CACHE FILEPATH "")
+
+include(${CMAKE_CURRENT_LIST_DIR}/common.cmake)
+
+get_property(IS_IN_TRY_COMPILE GLOBAL PROPERTY IN_TRY_COMPILE)
+if (IS_IN_TRY_COMPILE)
+  set(CMAKE_C_LINK_FLAGS "${CMAKE_C_LINK_FLAGS} -nostdlib")
+  set(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_LINK_FLAGS} -nostdlib")
+  cmake_print_variables(CMAKE_C_LINK_FLAGS)
+endif ()

examples/build_system/make/cpu/rv32i-ilp32.mk

@@ -0,0 +1,13 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -march=rv32i \
+    -mabi=ilp32 \
+
+else ifeq ($(TOOLCHAIN),iar)
+	#CFLAGS += --cpu cortex-a53
+	#ASFLAGS += --cpu cortex-a53
+
+endif
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V

examples/build_system/make/cpu/rv32imac-ilp32.mk

@@ -0,0 +1,13 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -march=rv32imac \
+    -mabi=ilp32 \
+
+else ifeq ($(TOOLCHAIN),iar)
+	#CFLAGS += --cpu cortex-a53
+	#ASFLAGS += --cpu cortex-a53
+
+endif
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V

examples/build_system/make/toolchain/riscv_gcc.mk

@@ -0,0 +1,20 @@
+# makefile for arm gcc toolchain
+
+# Can be set by family, default to ARM GCC
+CROSS_COMPILE ?= riscv-none-embed-
+
+CC = $(CROSS_COMPILE)gcc
+CXX = $(CROSS_COMPILE)g++
+AS = $(CC) -x assembler-with-cpp
+LD = $(CC)
+
+GDB = $(CROSS_COMPILE)gdb
+OBJCOPY = $(CROSS_COMPILE)objcopy
+SIZE = $(CROSS_COMPILE)size
+
+CFLAGS += \
+  -fsingle-precision-constant \
+
+LIBS += -lgcc -lm -lnosys
+
+include ${TOP}/examples/build_system/make/toolchain/gcc_common.mk