Merge pull request #2104 from hathach/g4-pd
Initial support for USB PD stack
This commit is contained in:
Ha Thach
369
src/portable/st/typec/typec_stm32.c
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369
src/portable/st/typec/typec_stm32.c
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2023 Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "tusb_option.h"
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#include "typec/tcd.h"
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#if CFG_TUC_ENABLED && defined(TUP_USBIP_TYPEC_STM32)
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#include "common/tusb_common.h"
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#if CFG_TUSB_MCU == OPT_MCU_STM32G4
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#include "stm32g4xx.h"
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#include "stm32g4xx_ll_dma.h" // for UCPD REQID
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#else
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#error "Unsupported STM32 family"
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#endif
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//--------------------------------------------------------------------+
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//
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//--------------------------------------------------------------------+
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enum {
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IMR_ATTACHED = UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
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UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | UCPD_IMR_RXMSGENDIE | UCPD_IMR_RXORDDETIE |
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UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE | UCPD_IMR_FRSEVTIE
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};
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#define PHY_SYNC1 0x18u
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#define PHY_SYNC2 0x11u
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#define PHY_SYNC3 0x06u
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#define PHY_RST1 0x07u
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#define PHY_RST2 0x19u
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#define PHY_EOP 0x0Du
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#define PHY_ORDERED_SET_SOP (PHY_SYNC1 | (PHY_SYNC1<<5u) | (PHY_SYNC1<<10u) | (PHY_SYNC2<<15u)) // SOP Ordered set coding
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#define PHY_ORDERED_SET_SOP_P (PHY_SYNC1 | (PHY_SYNC1<<5u) | (PHY_SYNC3<<10u) | (PHY_SYNC3<<15u)) // SOP' Ordered set coding
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#define PHY_ORDERED_SET_SOP_PP (PHY_SYNC1 | (PHY_SYNC3<<5u) | (PHY_SYNC1<<10u) | (PHY_SYNC3<<15u)) // SOP'' Ordered set coding
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#define PHY_ORDERED_SET_HARD_RESET (PHY_RST1 | (PHY_RST1<<5u) | (PHY_RST1<<10u) | (PHY_RST2<<15u )) // Hard Reset Ordered set coding
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#define PHY_ORDERED_SET_CABLE_RESET (PHY_RST1 | (PHY_SYNC1<<5u) | (PHY_RST1<<10u) | (PHY_SYNC3<<15u)) // Cable Reset Ordered set coding
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#define PHY_ORDERED_SET_SOP_P_DEBUG (PHY_SYNC1 | (PHY_RST2<<5u) | (PHY_RST2<<10u) | (PHY_SYNC3<<15u)) // SOP' Debug Ordered set coding
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#define PHY_ORDERED_SET_SOP_PP_DEBUG (PHY_SYNC1 | (PHY_RST2<<5u) | (PHY_SYNC3<<10u) | (PHY_SYNC2<<15u)) // SOP'' Debug Ordered set coding
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static uint8_t const* _rx_buf;
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static uint8_t const* _tx_pending_buf;
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static uint16_t _tx_pending_bytes;
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static uint16_t _tx_xferring_bytes;
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static pd_header_t _good_crc = {
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.msg_type = PD_CTRL_GOOD_CRC,
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.data_role = 0, // UFP
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.specs_rev = PD_REV_20,
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.power_role = 0, // Sink
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.msg_id = 0,
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.n_data_obj = 0,
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.extended = 0
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};
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// address of DMA channel rx, tx for each port
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#define CFG_TUC_STM32_DMA { { DMA1_Channel1_BASE, DMA1_Channel2_BASE } }
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//--------------------------------------------------------------------+
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// DMA
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//--------------------------------------------------------------------+
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static const uint32_t _dma_addr_arr[TUP_TYPEC_RHPORTS_NUM][2] = CFG_TUC_STM32_DMA;
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TU_ATTR_ALWAYS_INLINE static inline uint32_t dma_get_addr(uint8_t rhport, bool is_rx) {
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return _dma_addr_arr[rhport][is_rx ? 0 : 1];
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}
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static void dma_init(uint8_t rhport, bool is_rx) {
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uint32_t dma_addr = dma_get_addr(rhport, is_rx);
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DMA_Channel_TypeDef* dma_ch = (DMA_Channel_TypeDef*) dma_addr;
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uint32_t req_id;
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if (is_rx) {
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// Peripheral -> Memory, Memory inc, 8-bit, High priority
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dma_ch->CCR = DMA_CCR_MINC | DMA_CCR_PL_1;
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dma_ch->CPAR = (uint32_t) &UCPD1->RXDR;
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req_id = LL_DMAMUX_REQ_UCPD1_RX;
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} else {
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// Memory -> Peripheral, Memory inc, 8-bit, High priority
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dma_ch->CCR = DMA_CCR_MINC | DMA_CCR_PL_1 | DMA_CCR_DIR;
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dma_ch->CPAR = (uint32_t) &UCPD1->TXDR;
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req_id = LL_DMAMUX_REQ_UCPD1_TX;
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}
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// find and set up mux channel TODO support mcu with multiple DMAMUXs
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enum {
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CH_DIFF = DMA1_Channel2_BASE - DMA1_Channel1_BASE
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};
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uint32_t mux_ch_num;
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#ifdef DMA2_BASE
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if (dma_addr > DMA2_BASE) {
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mux_ch_num = 8 * ((dma_addr - DMA2_Channel1_BASE) / CH_DIFF);
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} else
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#endif
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{
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mux_ch_num = (dma_addr - DMA1_Channel1_BASE) / CH_DIFF;
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}
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DMAMUX_Channel_TypeDef* mux_ch = DMAMUX1_Channel0 + mux_ch_num;
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uint32_t mux_ccr = mux_ch->CCR & ~(DMAMUX_CxCR_DMAREQ_ID);
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mux_ccr |= req_id;
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mux_ch->CCR = mux_ccr;
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}
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TU_ATTR_ALWAYS_INLINE static inline void dma_start(uint8_t rhport, bool is_rx, void const* buf, uint16_t len) {
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DMA_Channel_TypeDef* dma_ch = (DMA_Channel_TypeDef*) dma_get_addr(rhport, is_rx);
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dma_ch->CMAR = (uint32_t) buf;
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dma_ch->CNDTR = len;
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dma_ch->CCR |= DMA_CCR_EN;
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}
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TU_ATTR_ALWAYS_INLINE static inline void dma_stop(uint8_t rhport, bool is_rx) {
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DMA_Channel_TypeDef* dma_ch = (DMA_Channel_TypeDef*) dma_get_addr(rhport, is_rx);
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dma_ch->CCR &= ~DMA_CCR_EN;
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}
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TU_ATTR_ALWAYS_INLINE static inline bool dma_enabled(uint8_t rhport, bool is_rx) {
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DMA_Channel_TypeDef* dma_ch = (DMA_Channel_TypeDef*) dma_get_addr(rhport, is_rx);
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return dma_ch->CCR & DMA_CCR_EN;
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}
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TU_ATTR_ALWAYS_INLINE static inline void dma_tx_start(uint8_t rhport, void const* buf, uint16_t len) {
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UCPD1->TX_ORDSET = PHY_ORDERED_SET_SOP;
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UCPD1->TX_PAYSZ = len;
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dma_start(rhport, false, buf, len);
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UCPD1->CR |= UCPD_CR_TXSEND;
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}
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TU_ATTR_ALWAYS_INLINE static inline void dma_tx_stop(uint8_t rhport) {
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dma_stop(rhport, false);
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}
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//--------------------------------------------------------------------+
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//
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//--------------------------------------------------------------------+
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bool tcd_init(uint8_t rhport, uint32_t port_type) {
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(void) rhport;
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// Init DMA for RX, TX
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dma_init(rhport, true);
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dma_init(rhport, false);
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// Initialization phase: CFG1, detect all SOPs
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UCPD1->CFG1 = (0x0d << UCPD_CFG1_HBITCLKDIV_Pos) | (0x10 << UCPD_CFG1_IFRGAP_Pos) | (0x07 << UCPD_CFG1_TRANSWIN_Pos) |
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(0x01 << UCPD_CFG1_PSC_UCPDCLK_Pos) | (0x1f << UCPD_CFG1_RXORDSETEN_Pos);
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UCPD1->CFG1 |= UCPD_CFG1_UCPDEN;
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// General programming sequence (with UCPD configured then enabled)
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if (port_type == TUSB_TYPEC_PORT_SNK) {
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// Set analog mode enable both CC Phy
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UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | (UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1);
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// Read Voltage State on CC1 & CC2 fore initial state
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uint32_t v_cc[2];
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v_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
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v_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03;
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TU_LOG1("Initial VState CC1 = %u, CC2 = %u\r\n", v_cc[0], v_cc[1]);
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// Enable CC1 & CC2 Interrupt
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UCPD1->IMR = UCPD_IMR_TYPECEVT1IE | UCPD_IMR_TYPECEVT2IE;
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}
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// Disable dead battery in PWR's CR3
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PWR->CR3 |= PWR_CR3_UCPD_DBDIS;
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return true;
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}
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// Enable interrupt
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void tcd_int_enable (uint8_t rhport) {
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(void) rhport;
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NVIC_EnableIRQ(UCPD1_IRQn);
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}
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// Disable interrupt
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void tcd_int_disable(uint8_t rhport) {
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(void) rhport;
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NVIC_DisableIRQ(UCPD1_IRQn);
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}
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bool tcd_msg_receive(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes) {
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_rx_buf = buffer;
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dma_start(rhport, true, buffer, total_bytes);
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return true;
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}
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bool tcd_msg_send(uint8_t rhport, uint8_t const* buffer, uint16_t total_bytes) {
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(void) rhport;
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if (dma_enabled(rhport, false)) {
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// DMA is busy, probably sending GoodCRC, save as pending TX
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_tx_pending_buf = buffer;
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_tx_pending_bytes = total_bytes;
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}else {
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// DMA is free, start sending
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_tx_pending_buf = NULL;
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_tx_pending_bytes = 0;
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_tx_xferring_bytes = total_bytes;
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dma_tx_start(rhport, buffer, total_bytes);
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}
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return true;
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}
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void tcd_int_handler(uint8_t rhport) {
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(void) rhport;
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uint32_t sr = UCPD1->SR;
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sr &= UCPD1->IMR;
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if (sr & (UCPD_SR_TYPECEVT1 | UCPD_SR_TYPECEVT2)) {
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uint32_t v_cc[2];
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v_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
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v_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03;
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TU_LOG3("VState CC1 = %u, CC2 = %u\n", v_cc[0], v_cc[1]);
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uint32_t cr = UCPD1->CR;
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// TODO only support SNK for now, required highest voltage for now
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// Enable PHY on active CC and disable Rd on other CC
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// FIXME somehow CC2 is vstate is not correct, always 1 even not attached.
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// on DPOW1 board, it is connected to PA10 (USBPD_DBCC2), we probably miss something.
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if ((sr & UCPD_SR_TYPECEVT1) && (v_cc[0] == 3)) {
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TU_LOG3("Attach CC1\n");
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cr &= ~(UCPD_CR_PHYCCSEL | UCPD_CR_CCENABLE);
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cr |= UCPD_CR_PHYRXEN | UCPD_CR_CCENABLE_0;
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} else if ((sr & UCPD_SR_TYPECEVT2) && (v_cc[1] == 3)) {
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TU_LOG3("Attach CC2\n");
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cr &= ~UCPD_CR_CCENABLE;
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cr |= (UCPD_CR_PHYCCSEL | UCPD_CR_PHYRXEN | UCPD_CR_CCENABLE_1);
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} else {
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TU_LOG3("Detach\n");
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cr &= ~UCPD_CR_PHYRXEN;
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cr |= UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1;
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}
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if (cr & UCPD_CR_PHYRXEN) {
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// Attached
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UCPD1->IMR |= IMR_ATTACHED;
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UCPD1->CFG1 |= UCPD_CFG1_RXDMAEN | UCPD_CFG1_TXDMAEN;
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}else {
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// Detached
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UCPD1->CFG1 &= ~(UCPD_CFG1_RXDMAEN | UCPD_CFG1_TXDMAEN);
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UCPD1->IMR &= ~IMR_ATTACHED;
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}
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// notify stack
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tcd_event_cc_changed(rhport, v_cc[0], v_cc[1], true);
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UCPD1->CR = cr;
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// ack
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UCPD1->ICR = UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF;
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}
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//------------- RX -------------//
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if (sr & UCPD_SR_RXORDDET) {
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// SOP: Start of Packet.
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TU_LOG3("SOP\n");
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// UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk;
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// ack
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UCPD1->ICR = UCPD_ICR_RXORDDETCF;
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}
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// Received full message
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if (sr & UCPD_SR_RXMSGEND) {
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TU_LOG3("RX MSG END\n");
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// stop TX
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dma_stop(rhport, true);
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uint8_t result;
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if (!(sr & UCPD_SR_RXERR)) {
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// response with good crc
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_good_crc.msg_id = ((pd_header_t const*) _rx_buf)->msg_id;
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dma_tx_start(rhport, &_good_crc, 2);
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result = XFER_RESULT_SUCCESS;
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}else {
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// CRC failed
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result = XFER_RESULT_FAILED;
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}
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// notify stack
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tcd_event_rx_complete(rhport, UCPD1->RX_PAYSZ, result, true);
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// ack
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UCPD1->ICR = UCPD_ICR_RXMSGENDCF;
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}
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if (sr & UCPD_SR_RXOVR) {
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TU_LOG3("RXOVR\n");
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// ack
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UCPD1->ICR = UCPD_ICR_RXOVRCF;
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}
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//------------- TX -------------//
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// All tx events: complete and error
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if (sr & (UCPD_SR_TXMSGSENT | (UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND))) {
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// force TX stop
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dma_tx_stop(rhport);
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uint16_t const xferred_bytes = _tx_xferring_bytes - UCPD1->TX_PAYSZ;
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uint8_t result;
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if ( sr & UCPD_SR_TXMSGSENT ) {
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TU_LOG3("TX MSG SENT\n");
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result = XFER_RESULT_SUCCESS;
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// ack
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UCPD1->ICR = UCPD_ICR_TXMSGSENTCF;
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}else {
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TU_LOG3("TX Error\n");
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result = XFER_RESULT_FAILED;
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// ack
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UCPD1->ICR = UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND;
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}
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// start pending TX if any
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if (_tx_pending_buf && _tx_pending_bytes ) {
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// Start the pending TX
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dma_tx_start(rhport, _tx_pending_buf, _tx_pending_bytes);
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// clear pending
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_tx_pending_buf = NULL;
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_tx_pending_bytes = 0;
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}
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// notify stack
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tcd_event_tx_complete(rhport, xferred_bytes, result, true);
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}
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}
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#endif
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