hcd dwc2 add dcache support, usbh correctly use cache line size with TUH_EPBUF_DEF

2024-11-26 10:20:38 +07:00
parent 62f0e87bf1
commit be25aa31f6
5 changed files with 78 additions and 33 deletions
--- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
+++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
@@ -18,7 +18,8 @@ list(APPEND compile_definitions
 if (target STREQUAL esp32p4)
  # P4 change alignment to 64 (DCache line size) for possible DMA configuration
  list(APPEND compile_definitions
-    CFG_TUSB_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\)
+    CFG_TUD_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\)
+    CFG_TUH_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\)
    )
 endif ()